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| author | Shengjiu Wang <shengjiu.wang@freescale.com> | 2014-09-09 17:13:25 +0800 |
|---|---|---|
| committer | Shawn Guo <shawn.guo@freescale.com> | 2014-09-16 10:09:39 +0800 |
| commit | dbaf381ffbf3acd4ac9a987f567a2b1a5edf6e62 (patch) | |
| tree | 7ef673b04004f91218d0532bc7768831a6769db2 /tools/perf/scripts/python | |
| parent | dc4805c2e78ba5a22ea1632f3e3e4ee601a1743b (diff) | |
ARM: clk-imx6sl: refine clock tree for SSI
Each SSI has "ssi", "ssi_ipg" clocks, and they share same gate bits.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions