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| author | Tomi Valkeinen <tomi.valkeinen@ti.com> | 2014-08-07 14:29:24 +0300 |
|---|---|---|
| committer | Tomi Valkeinen <tomi.valkeinen@ti.com> | 2014-11-12 13:40:23 +0200 |
| commit | dbb26e53e5a6eda5ee53fb36cdf3ca2517cfb135 (patch) | |
| tree | 0215be4607f4d85776cc9adc469a382f74ea37bb /tools/perf/scripts/python | |
| parent | acf604b709e6b933638bd72d52c5b2e0ff37ff16 (diff) | |
OMAPDSS: DSI: features: combine dsi & dispc hsdivs
The HSDIV outputs of DSI PLL (and also other PLLs) all have the same
bit width for the divider value.
Simplify the code by merging HSDIV divider widths into one width.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions