diff options
Diffstat (limited to 'arch/arm/mach-shmobile/intc-sh73a0.c')
| -rw-r--r-- | arch/arm/mach-shmobile/intc-sh73a0.c | 187 |
1 files changed, 187 insertions, 0 deletions
diff --git a/arch/arm/mach-shmobile/intc-sh73a0.c b/arch/arm/mach-shmobile/intc-sh73a0.c index a911a60e771..1eda6b0b69e 100644 --- a/arch/arm/mach-shmobile/intc-sh73a0.c +++ b/arch/arm/mach-shmobile/intc-sh73a0.c @@ -22,6 +22,8 @@ #include <linux/irq.h> #include <linux/io.h> #include <linux/sh_intc.h> +#include <mach/intc.h> +#include <mach/sh73a0.h> #include <asm/hardware/gic.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> @@ -255,20 +257,205 @@ static int sh73a0_set_wake(struct irq_data *data, unsigned int on) return 0; /* always allow wakeup */ } +#define RELOC_BASE 0x1000 + +/* INTCA IRQ pins at INTCS + 0x1000 to make space for GIC+INTC handling */ +#define INTCS_VECT_RELOC(n, vect) INTCS_VECT((n), (vect) + RELOC_BASE) + +INTC_IRQ_PINS_32(intca_irq_pins, 0xe6900000, + INTCS_VECT_RELOC, "sh73a0-intca-irq-pins"); + +static int to_gic_irq(struct irq_data *data) +{ + unsigned int vect = irq2evt(data->irq) - INTCS_VECT_BASE; + + if (vect >= 0x3200) + vect -= 0x3000; + else + vect -= 0x0200; + + return gic_spi((vect >> 5) + 1); +} + +static int to_intca_reloc_irq(struct irq_data *data) +{ + return data->irq + (RELOC_BASE >> 5); +} + +#define irq_cb(cb, irq) irq_get_chip(irq)->cb(irq_get_irq_data(irq)) +#define irq_cbp(cb, irq, p...) irq_get_chip(irq)->cb(irq_get_irq_data(irq), p) + +static void intca_gic_enable(struct irq_data *data) +{ + irq_cb(irq_unmask, to_intca_reloc_irq(data)); + irq_cb(irq_unmask, to_gic_irq(data)); +} + +static void intca_gic_disable(struct irq_data *data) +{ + irq_cb(irq_mask, to_gic_irq(data)); + irq_cb(irq_mask, to_intca_reloc_irq(data)); +} + +static void intca_gic_mask_ack(struct irq_data *data) +{ + irq_cb(irq_mask, to_gic_irq(data)); + irq_cb(irq_mask_ack, to_intca_reloc_irq(data)); +} + +static void intca_gic_eoi(struct irq_data *data) +{ + irq_cb(irq_eoi, to_gic_irq(data)); +} + +static int intca_gic_set_type(struct irq_data *data, unsigned int type) +{ + return irq_cbp(irq_set_type, to_intca_reloc_irq(data), type); +} + +static int intca_gic_set_wake(struct irq_data *data, unsigned int on) +{ + return irq_cbp(irq_set_wake, to_intca_reloc_irq(data), on); +} + +#ifdef CONFIG_SMP +static int intca_gic_set_affinity(struct irq_data *data, + const struct cpumask *cpumask, + bool force) +{ + return irq_cbp(irq_set_affinity, to_gic_irq(data), cpumask, force); +} +#endif + +struct irq_chip intca_gic_irq_chip = { + .name = "INTCA-GIC", + .irq_mask = intca_gic_disable, + .irq_unmask = intca_gic_enable, + .irq_mask_ack = intca_gic_mask_ack, + .irq_eoi = intca_gic_eoi, + .irq_enable = intca_gic_enable, + .irq_disable = intca_gic_disable, + .irq_shutdown = intca_gic_disable, + .irq_set_type = intca_gic_set_type, + .irq_set_wake = intca_gic_set_wake, +#ifdef CONFIG_SMP + .irq_set_affinity = intca_gic_set_affinity, +#endif +}; + +static int to_intc_vect(int irq) +{ + unsigned int irq_pin = irq - gic_spi(1); + unsigned int offs; + + if (irq_pin < 16) + offs = 0x0200; + else + offs = 0x3000; + + return offs + (irq_pin << 5); +} + +static irqreturn_t sh73a0_irq_pin_demux(int irq, void *dev_id) +{ + generic_handle_irq(intcs_evt2irq(to_intc_vect(irq))); + return IRQ_HANDLED; +} + +static struct irqaction sh73a0_irq_pin_cascade[32]; + +#define PINTER0 0xe69000a0 +#define PINTER1 0xe69000a4 +#define PINTRR0 0xe69000d0 +#define PINTRR1 0xe69000d4 + +#define PINT0A_IRQ(n, irq) INTC_IRQ((n), SH73A0_PINT0_IRQ(irq)) +#define PINT0B_IRQ(n, irq) INTC_IRQ((n), SH73A0_PINT0_IRQ(irq + 8)) +#define PINT0C_IRQ(n, irq) INTC_IRQ((n), SH73A0_PINT0_IRQ(irq + 16)) +#define PINT0D_IRQ(n, irq) INTC_IRQ((n), SH73A0_PINT0_IRQ(irq + 24)) +#define PINT1E_IRQ(n, irq) INTC_IRQ((n), SH73A0_PINT1_IRQ(irq)) + +INTC_PINT(intc_pint0, PINTER0, 0xe69000b0, "sh73a0-pint0", \ + INTC_PINT_E(A), INTC_PINT_E(B), INTC_PINT_E(C), INTC_PINT_E(D), \ + INTC_PINT_V(A, PINT0A_IRQ), INTC_PINT_V(B, PINT0B_IRQ), \ + INTC_PINT_V(C, PINT0C_IRQ), INTC_PINT_V(D, PINT0D_IRQ), \ + INTC_PINT_E(A), INTC_PINT_E(B), INTC_PINT_E(C), INTC_PINT_E(D), \ + INTC_PINT_E(A), INTC_PINT_E(B), INTC_PINT_E(C), INTC_PINT_E(D)); + +INTC_PINT(intc_pint1, PINTER1, 0xe69000c0, "sh73a0-pint1", \ + INTC_PINT_E(E), INTC_PINT_E_EMPTY, INTC_PINT_E_EMPTY, INTC_PINT_E_EMPTY, \ + INTC_PINT_V(E, PINT1E_IRQ), INTC_PINT_V_NONE, \ + INTC_PINT_V_NONE, INTC_PINT_V_NONE, \ + INTC_PINT_E_NONE, INTC_PINT_E_NONE, INTC_PINT_E_NONE, INTC_PINT_E(E), \ + INTC_PINT_E(E), INTC_PINT_E_NONE, INTC_PINT_E_NONE, INTC_PINT_E_NONE); + +static struct irqaction sh73a0_pint0_cascade; +static struct irqaction sh73a0_pint1_cascade; + +static void pint_demux(unsigned long rr, unsigned long er, int base_irq) +{ + unsigned long value = ioread32(rr) & ioread32(er); + int k; + + for (k = 0; k < 32; k++) { + if (value & (1 << (31 - k))) { + generic_handle_irq(base_irq + k); + iowrite32(~(1 << (31 - k)), rr); + } + } +} + +static irqreturn_t sh73a0_pint0_demux(int irq, void *dev_id) +{ + pint_demux(PINTRR0, PINTER0, SH73A0_PINT0_IRQ(0)); + return IRQ_HANDLED; +} + +static irqreturn_t sh73a0_pint1_demux(int irq, void *dev_id) +{ + pint_demux(PINTRR1, PINTER1, SH73A0_PINT1_IRQ(0)); + return IRQ_HANDLED; +} + void __init sh73a0_init_irq(void) { void __iomem *gic_dist_base = __io(0xf0001000); void __iomem *gic_cpu_base = __io(0xf0000100); void __iomem *intevtsa = ioremap_nocache(0xffd20100, PAGE_SIZE); + int k, n; gic_init(0, 29, gic_dist_base, gic_cpu_base); gic_arch_extn.irq_set_wake = sh73a0_set_wake; register_intc_controller(&intcs_desc); + register_intc_controller(&intca_irq_pins_desc); + register_intc_controller(&intc_pint0_desc); + register_intc_controller(&intc_pint1_desc); /* demux using INTEVTSA */ sh73a0_intcs_cascade.name = "INTCS cascade"; sh73a0_intcs_cascade.handler = sh73a0_intcs_demux; sh73a0_intcs_cascade.dev_id = intevtsa; setup_irq(gic_spi(50), &sh73a0_intcs_cascade); + + /* IRQ pins require special handling through INTCA and GIC */ + for (k = 0; k < 32; k++) { + sh73a0_irq_pin_cascade[k].name = "INTCA-GIC cascade"; + sh73a0_irq_pin_cascade[k].handler = sh73a0_irq_pin_demux; + setup_irq(gic_spi(1 + k), &sh73a0_irq_pin_cascade[k]); + + n = intcs_evt2irq(to_intc_vect(gic_spi(1 + k))); + irq_set_chip_and_handler_name(n, &intca_gic_irq_chip, + handle_level_irq, "level"); + set_irq_flags(n, IRQF_VALID); /* yuck */ + } + + /* PINT pins are sanely tied to the GIC as SPI */ + sh73a0_pint0_cascade.name = "PINT0 cascade"; + sh73a0_pint0_cascade.handler = sh73a0_pint0_demux; + setup_irq(gic_spi(33), &sh73a0_pint0_cascade); + + sh73a0_pint1_cascade.name = "PINT1 cascade"; + sh73a0_pint1_cascade.handler = sh73a0_pint1_demux; + setup_irq(gic_spi(34), &sh73a0_pint1_cascade); } |