diff options
Diffstat (limited to 'arch/arm/mach-ux500/include/mach')
| -rw-r--r-- | arch/arm/mach-ux500/include/mach/db5500-regs.h | 103 | ||||
| -rw-r--r-- | arch/arm/mach-ux500/include/mach/db8500-regs.h | 135 | ||||
| -rw-r--r-- | arch/arm/mach-ux500/include/mach/debug-macro.S | 12 | ||||
| -rw-r--r-- | arch/arm/mach-ux500/include/mach/devices.h | 29 | ||||
| -rw-r--r-- | arch/arm/mach-ux500/include/mach/entry-macro.S | 2 | ||||
| -rw-r--r-- | arch/arm/mach-ux500/include/mach/gpio.h | 50 | ||||
| -rw-r--r-- | arch/arm/mach-ux500/include/mach/hardware.h | 197 | ||||
| -rw-r--r-- | arch/arm/mach-ux500/include/mach/irqs.h | 9 | ||||
| -rw-r--r-- | arch/arm/mach-ux500/include/mach/setup.h | 24 |
9 files changed, 454 insertions, 107 deletions
diff --git a/arch/arm/mach-ux500/include/mach/db5500-regs.h b/arch/arm/mach-ux500/include/mach/db5500-regs.h new file mode 100644 index 00000000000..545c80fc802 --- /dev/null +++ b/arch/arm/mach-ux500/include/mach/db5500-regs.h @@ -0,0 +1,103 @@ +/* + * Copyright (C) ST-Ericsson SA 2010 + * + * License terms: GNU General Public License (GPL) version 2 + */ + +#ifndef __MACH_DB5500_REGS_H +#define __MACH_DB5500_REGS_H + +#define U5500_PER1_BASE 0xA0020000 +#define U5500_PER2_BASE 0xA0010000 +#define U5500_PER3_BASE 0x80140000 +#define U5500_PER4_BASE 0x80150000 +#define U5500_PER5_BASE 0x80100000 +#define U5500_PER6_BASE 0x80120000 + +#define U5500_GIC_DIST_BASE 0xA0411000 +#define U5500_GIC_CPU_BASE 0xA0410100 +#define U5500_DMA_BASE 0x90030000 +#define U5500_MCDE_BASE 0xA0400000 +#define U5500_MODEM_BASE 0xB0000000 +#define U5500_L2CC_BASE 0xA0412000 +#define U5500_SCU_BASE 0xA0410000 +#define U5500_DSI1_BASE 0xA0401000 +#define U5500_DSI2_BASE 0xA0402000 +#define U5500_SIA_BASE 0xA0100000 +#define U5500_SVA_BASE 0x80200000 +#define U5500_HSEM_BASE 0xA0000000 +#define U5500_NAND0_BASE 0x60000000 +#define U5500_NAND1_BASE 0x70000000 +#define U5500_TWD_BASE 0xa0410600 +#define U5500_B2R2_BASE 0xa0200000 + +#define U5500_FSMC_BASE (U5500_PER1_BASE + 0x0000) +#define U5500_SDI0_BASE (U5500_PER1_BASE + 0x1000) +#define U5500_SDI2_BASE (U5500_PER1_BASE + 0x2000) +#define U5500_UART0_BASE (U5500_PER1_BASE + 0x3000) +#define U5500_I2C1_BASE (U5500_PER1_BASE + 0x4000) +#define U5500_MSP0_BASE (U5500_PER1_BASE + 0x5000) +#define U5500_GPIO0_BASE (U5500_PER1_BASE + 0xE000) +#define U5500_CLKRST1_BASE (U5500_PER1_BASE + 0xF000) + +#define U5500_USBOTG_BASE (U5500_PER2_BASE + 0x0000) +#define U5500_GPIO1_BASE (U5500_PER2_BASE + 0xE000) +#define U5500_CLKRST2_BASE (U5500_PER2_BASE + 0xF000) + +#define U5500_KEYPAD_BASE (U5500_PER3_BASE + 0x0000) +#define U5500_PWM_BASE (U5500_PER3_BASE + 0x1000) +#define U5500_GPIO3_BASE (U5500_PER3_BASE + 0xE000) +#define U5500_CLKRST3_BASE (U5500_PER3_BASE + 0xF000) + +#define U5500_BACKUPRAM0_BASE (U5500_PER4_BASE + 0x0000) +#define U5500_BACKUPRAM1_BASE (U5500_PER4_BASE + 0x1000) +#define U5500_RTT0_BASE (U5500_PER4_BASE + 0x2000) +#define U5500_RTT1_BASE (U5500_PER4_BASE + 0x3000) +#define U5500_RTC_BASE (U5500_PER4_BASE + 0x4000) +#define U5500_SCR_BASE (U5500_PER4_BASE + 0x5000) +#define U5500_DMC_BASE (U5500_PER4_BASE + 0x6000) +#define U5500_PRCMU_BASE (U5500_PER4_BASE + 0x7000) +#define U5500_MSP1_BASE (U5500_PER4_BASE + 0x9000) +#define U5500_GPIO2_BASE (U5500_PER4_BASE + 0xA000) +#define U5500_CDETECT_BASE (U5500_PER4_BASE + 0xF000) + +#define U5500_SPI0_BASE (U5500_PER5_BASE + 0x0000) +#define U5500_SPI1_BASE (U5500_PER5_BASE + 0x1000) +#define U5500_SPI2_BASE (U5500_PER5_BASE + 0x2000) +#define U5500_SPI3_BASE (U5500_PER5_BASE + 0x3000) +#define U5500_UART1_BASE (U5500_PER5_BASE + 0x4000) +#define U5500_UART2_BASE (U5500_PER5_BASE + 0x5000) +#define U5500_UART3_BASE (U5500_PER5_BASE + 0x6000) +#define U5500_SDI1_BASE (U5500_PER5_BASE + 0x7000) +#define U5500_SDI3_BASE (U5500_PER5_BASE + 0x8000) +#define U5500_SDI4_BASE (U5500_PER5_BASE + 0x9000) +#define U5500_I2C2_BASE (U5500_PER5_BASE + 0xA000) +#define U5500_I2C3_BASE (U5500_PER5_BASE + 0xB000) +#define U5500_MSP2_BASE (U5500_PER5_BASE + 0xC000) +#define U5500_IRDA_BASE (U5500_PER5_BASE + 0xD000) +#define U5500_IRRC_BASE (U5500_PER5_BASE + 0x10000) +#define U5500_GPIO4_BASE (U5500_PER5_BASE + 0x1E000) +#define U5500_CLKRST5_BASE (U5500_PER5_BASE + 0x1F000) + +#define U5500_RNG_BASE (U5500_PER6_BASE + 0x0000) +#define U5500_HASH0_BASE (U5500_PER6_BASE + 0x1000) +#define U5500_HASH1_BASE (U5500_PER6_BASE + 0x2000) +#define U5500_PKA_BASE (U5500_PER6_BASE + 0x4000) +#define U5500_PKAM_BASE (U5500_PER6_BASE + 0x5000) +#define U5500_MTU0_BASE (U5500_PER6_BASE + 0x6000) +#define U5500_MTU1_BASE (U5500_PER6_BASE + 0x7000) +#define U5500_CR_BASE (U5500_PER6_BASE + 0x8000) +#define U5500_CRYP0_BASE (U5500_PER6_BASE + 0xA000) +#define U5500_CRYP1_BASE (U5500_PER6_BASE + 0xB000) +#define U5500_CLKRST6_BASE (U5500_PER6_BASE + 0xF000) + +#define U5500_GPIOBANK0_BASE U5500_GPIO0_BASE +#define U5500_GPIOBANK1_BASE (U5500_GPIO0_BASE + 0x80) +#define U5500_GPIOBANK2_BASE U5500_GPIO1_BASE +#define U5500_GPIOBANK3_BASE U5500_GPIO2_BASE +#define U5500_GPIOBANK4_BASE U5500_GPIO3_BASE +#define U5500_GPIOBANK5_BASE U5500_GPIO4_BASE +#define U5500_GPIOBANK6_BASE (U5500_GPIO4_BASE + 0x80) +#define U5500_GPIOBANK7_BASE (U5500_GPIO4_BASE + 0x100) + +#endif diff --git a/arch/arm/mach-ux500/include/mach/db8500-regs.h b/arch/arm/mach-ux500/include/mach/db8500-regs.h new file mode 100644 index 00000000000..9169e1e382a --- /dev/null +++ b/arch/arm/mach-ux500/include/mach/db8500-regs.h @@ -0,0 +1,135 @@ +/* + * Copyright (C) ST-Ericsson SA 2010 + * + * License terms: GNU General Public License (GPL) version 2 + */ + +#ifndef __MACH_DB8500_REGS_H +#define __MACH_DB8500_REGS_H + +#define U8500_PER3_BASE 0x80000000 +#define U8500_STM_BASE 0x80100000 +#define U8500_STM_REG_BASE (U8500_STM_BASE + 0xF000) +#define U8500_PER2_BASE 0x80110000 +#define U8500_PER1_BASE 0x80120000 +#define U8500_B2R2_BASE 0x80130000 +#define U8500_HSEM_BASE 0x80140000 +#define U8500_PER4_BASE 0x80150000 +#define U8500_ICN_BASE 0x81000000 + +#define U8500_BOOT_ROM_BASE 0x90000000 +/* ASIC ID is at 0xff4 offset within this region */ +#define U8500_ASIC_ID_BASE 0x9001F000 + +#define U8500_PER6_BASE 0xa03c0000 +#define U8500_PER5_BASE 0xa03e0000 +#define U8500_PER7_BASE_ED 0xa03d0000 + +#define U8500_SVA_BASE 0xa0100000 +#define U8500_SIA_BASE 0xa0200000 + +#define U8500_SGA_BASE 0xa0300000 +#define U8500_MCDE_BASE 0xa0350000 +#define U8500_DMA_BASE_ED 0xa0362000 +#define U8500_DMA_BASE 0x801C0000 /* v1 */ + +#define U8500_SBAG_BASE 0xa0390000 + +#define U8500_SCU_BASE 0xa0410000 +#define U8500_GIC_CPU_BASE 0xa0410100 +#define U8500_TWD_BASE 0xa0410600 +#define U8500_GIC_DIST_BASE 0xa0411000 +#define U8500_L2CC_BASE 0xa0412000 + +#define U8500_MODEM_I2C 0xb7e02000 + +#define U8500_GPIO0_BASE (U8500_PER1_BASE + 0xE000) +#define U8500_GPIO1_BASE (U8500_PER3_BASE + 0xE000) +#define U8500_GPIO2_BASE (U8500_PER2_BASE + 0xE000) +#define U8500_GPIO3_BASE (U8500_PER5_BASE + 0x1E000) + +/* per7 base addressess */ +#define U8500_CR_BASE_ED (U8500_PER7_BASE_ED + 0x8000) +#define U8500_MTU0_BASE_ED (U8500_PER7_BASE_ED + 0xa000) +#define U8500_MTU1_BASE_ED (U8500_PER7_BASE_ED + 0xb000) +#define U8500_TZPC0_BASE_ED (U8500_PER7_BASE_ED + 0xc000) +#define U8500_CLKRST7_BASE_ED (U8500_PER7_BASE_ED + 0xf000) + +#define U8500_UART0_BASE (U8500_PER1_BASE + 0x0000) +#define U8500_UART1_BASE (U8500_PER1_BASE + 0x1000) + +/* per6 base addressess */ +#define U8500_RNG_BASE (U8500_PER6_BASE + 0x0000) +#define U8500_PKA_BASE (U8500_PER6_BASE + 0x1000) +#define U8500_PKAM_BASE (U8500_PER6_BASE + 0x2000) +#define U8500_MTU0_BASE (U8500_PER6_BASE + 0x6000) /* v1 */ +#define U8500_MTU1_BASE (U8500_PER6_BASE + 0x7000) /* v1 */ +#define U8500_CR_BASE (U8500_PER6_BASE + 0x8000) /* v1 */ +#define U8500_CRYPTO0_BASE (U8500_PER6_BASE + 0xa000) +#define U8500_CRYPTO1_BASE (U8500_PER6_BASE + 0xb000) +#define U8500_CLKRST6_BASE (U8500_PER6_BASE + 0xf000) + +/* per5 base addressess */ +#define U8500_USBOTG_BASE (U8500_PER5_BASE + 0x00000) +#define U8500_CLKRST5_BASE (U8500_PER5_BASE + 0x1f000) + +/* per4 base addressess */ +#define U8500_BACKUPRAM0_BASE (U8500_PER4_BASE + 0x00000) +#define U8500_BACKUPRAM1_BASE (U8500_PER4_BASE + 0x01000) +#define U8500_RTT0_BASE (U8500_PER4_BASE + 0x02000) +#define U8500_RTT1_BASE (U8500_PER4_BASE + 0x03000) +#define U8500_RTC_BASE (U8500_PER4_BASE + 0x04000) +#define U8500_SCR_BASE (U8500_PER4_BASE + 0x05000) +#define U8500_DMC_BASE (U8500_PER4_BASE + 0x06000) +#define U8500_PRCMU_BASE (U8500_PER4_BASE + 0x07000) +#define U8500_PRCMU_TCDM_BASE (U8500_PER4_BASE + 0x0f000) + +/* per3 base addresses */ +#define U8500_FSMC_BASE (U8500_PER3_BASE + 0x0000) +#define U8500_SSP0_BASE (U8500_PER3_BASE + 0x2000) +#define U8500_SSP1_BASE (U8500_PER3_BASE + 0x3000) +#define U8500_I2C0_BASE (U8500_PER3_BASE + 0x4000) +#define U8500_SDI2_BASE (U8500_PER3_BASE + 0x5000) +#define U8500_SKE_BASE (U8500_PER3_BASE + 0x6000) +#define U8500_UART2_BASE (U8500_PER3_BASE + 0x7000) +#define U8500_SDI5_BASE (U8500_PER3_BASE + 0x8000) +#define U8500_CLKRST3_BASE (U8500_PER3_BASE + 0xf000) + +/* per2 base addressess */ +#define U8500_I2C3_BASE (U8500_PER2_BASE + 0x0000) +#define U8500_SPI2_BASE (U8500_PER2_BASE + 0x1000) +#define U8500_SPI1_BASE (U8500_PER2_BASE + 0x2000) +#define U8500_PWL_BASE (U8500_PER2_BASE + 0x3000) +#define U8500_SDI4_BASE (U8500_PER2_BASE + 0x4000) +#define U8500_MSP2_BASE (U8500_PER2_BASE + 0x7000) +#define U8500_SDI1_BASE (U8500_PER2_BASE + 0x8000) +#define U8500_SDI3_BASE (U8500_PER2_BASE + 0x9000) +#define U8500_SPI0_BASE (U8500_PER2_BASE + 0xa000) +#define U8500_HSIR_BASE (U8500_PER2_BASE + 0xb000) +#define U8500_HSIT_BASE (U8500_PER2_BASE + 0xc000) +#define U8500_CLKRST2_BASE (U8500_PER2_BASE + 0xf000) + +/* per1 base addresses */ +#define U8500_I2C1_BASE (U8500_PER1_BASE + 0x2000) +#define U8500_MSP0_BASE (U8500_PER1_BASE + 0x3000) +#define U8500_MSP1_BASE (U8500_PER1_BASE + 0x4000) +#define U8500_SDI0_BASE (U8500_PER1_BASE + 0x6000) +#define U8500_I2C2_BASE (U8500_PER1_BASE + 0x8000) +#define U8500_SPI3_BASE (U8500_PER1_BASE + 0x9000) +#define U8500_I2C4_BASE (U8500_PER1_BASE + 0xa000) +#define U8500_SLIM0_BASE (U8500_PER1_BASE + 0xb000) +#define U8500_CLKRST1_BASE (U8500_PER1_BASE + 0xf000) + +#define U8500_SHRM_GOP_INTERRUPT_BASE 0xB7C00040 + +#define U8500_GPIOBANK0_BASE U8500_GPIO0_BASE +#define U8500_GPIOBANK1_BASE (U8500_GPIO0_BASE + 0x80) +#define U8500_GPIOBANK2_BASE U8500_GPIO1_BASE +#define U8500_GPIOBANK3_BASE (U8500_GPIO1_BASE + 0x80) +#define U8500_GPIOBANK4_BASE (U8500_GPIO1_BASE + 0x100) +#define U8500_GPIOBANK5_BASE (U8500_GPIO1_BASE + 0x180) +#define U8500_GPIOBANK6_BASE U8500_GPIO2_BASE +#define U8500_GPIOBANK7_BASE (U8500_GPIO2_BASE + 0x80) +#define U8500_GPIOBANK8_BASE U8500_GPIO3_BASE + +#endif diff --git a/arch/arm/mach-ux500/include/mach/debug-macro.S b/arch/arm/mach-ux500/include/mach/debug-macro.S index 09cbfda8aee..c5203b7ea55 100644 --- a/arch/arm/mach-ux500/include/mach/debug-macro.S +++ b/arch/arm/mach-ux500/include/mach/debug-macro.S @@ -10,11 +10,19 @@ */ #include <mach/hardware.h> +#if CONFIG_UX500_DEBUG_UART > 2 +#error Invalid Ux500 debug UART +#endif + +#define __UX500_UART(n) UX500_UART##n##_BASE +#define UX500_UART(n) __UX500_UART(n) +#define UART_BASE UX500_UART(CONFIG_UX500_DEBUG_UART) + .macro addruart, rx, tmp mrc p15, 0, \rx, c1, c0 tst \rx, #1 @ MMU enabled? - ldreq \rx, =U8500_UART2_BASE @ no, physical address - ldrne \rx, =IO_ADDRESS(U8500_UART2_BASE) @ yes, virtual address + ldreq \rx, =UART_BASE @ no, physical address + ldrne \rx, =IO_ADDRESS(UART_BASE) @ yes, virtual address .endm #include <asm/hardware/debug-pl01x.S> diff --git a/arch/arm/mach-ux500/include/mach/devices.h b/arch/arm/mach-ux500/include/mach/devices.h new file mode 100644 index 00000000000..0422af00a56 --- /dev/null +++ b/arch/arm/mach-ux500/include/mach/devices.h @@ -0,0 +1,29 @@ +/* + * Copyright (C) ST-Ericsson SA 2010 + * + * License terms: GNU General Public License (GPL) version 2 + */ + +#ifndef __ASM_ARCH_DEVICES_H__ +#define __ASM_ARCH_DEVICES_H__ + +struct platform_device; +struct amba_device; + +extern struct platform_device u5500_gpio_devs[]; +extern struct platform_device u8500_gpio_devs[]; + +extern struct amba_device ux500_pl031_device; +extern struct amba_device u8500_ssp0_device; +extern struct amba_device ux500_uart0_device; +extern struct amba_device ux500_uart1_device; +extern struct amba_device ux500_uart2_device; + +extern struct platform_device ux500_i2c1_device; +extern struct platform_device ux500_i2c2_device; +extern struct platform_device ux500_i2c3_device; + +extern struct platform_device u8500_i2c0_device; +extern struct platform_device u8500_i2c4_device; + +#endif diff --git a/arch/arm/mach-ux500/include/mach/entry-macro.S b/arch/arm/mach-ux500/include/mach/entry-macro.S index eece3301fef..60ea88db828 100644 --- a/arch/arm/mach-ux500/include/mach/entry-macro.S +++ b/arch/arm/mach-ux500/include/mach/entry-macro.S @@ -17,7 +17,7 @@ .endm .macro get_irqnr_preamble, base, tmp - ldr \base, =IO_ADDRESS(U8500_GIC_CPU_BASE) + ldr \base, =IO_ADDRESS(UX500_GIC_CPU_BASE) .endm .macro arch_ret_to_user, tmp1, tmp2 diff --git a/arch/arm/mach-ux500/include/mach/gpio.h b/arch/arm/mach-ux500/include/mach/gpio.h new file mode 100644 index 00000000000..d548a622e7d --- /dev/null +++ b/arch/arm/mach-ux500/include/mach/gpio.h @@ -0,0 +1,50 @@ +#ifndef __ASM_ARCH_GPIO_H +#define __ASM_ARCH_GPIO_H + +/* + * 288 (#267 is the highest one actually hooked up) onchip GPIOs, plus enough + * room for a couple of GPIO expanders. + */ +#define ARCH_NR_GPIOS 350 + +#include <plat/gpio.h> + +#define __GPIO_RESOURCE(soc, block) \ + { \ + .start = soc##_GPIOBANK##block##_BASE, \ + .end = soc##_GPIOBANK##block##_BASE + 127, \ + .flags = IORESOURCE_MEM, \ + }, \ + { \ + .start = IRQ_GPIO##block, \ + .end = IRQ_GPIO##block, \ + .flags = IORESOURCE_IRQ, \ + } + +#define __GPIO_DEVICE(soc, block) \ + { \ + .name = "gpio", \ + .id = block, \ + .num_resources = 2, \ + .resource = &soc##_gpio_resources[block * 2], \ + .dev = { \ + .platform_data = &soc##_gpio_data[block], \ + }, \ + } + +#define GPIO_DATA(_name, first) \ + { \ + .name = _name, \ + .first_gpio = first, \ + .first_irq = NOMADIK_GPIO_TO_IRQ(first), \ + } + +#ifdef CONFIG_UX500_SOC_DB8500 +#define GPIO_RESOURCE(block) __GPIO_RESOURCE(U8500, block) +#define GPIO_DEVICE(block) __GPIO_DEVICE(u8500, block) +#elif defined(CONFIG_UX500_SOC_DB5500) +#define GPIO_RESOURCE(block) __GPIO_RESOURCE(U5500, block) +#define GPIO_DEVICE(block) __GPIO_DEVICE(u5500, block) +#endif + +#endif /* __ASM_ARCH_GPIO_H */ diff --git a/arch/arm/mach-ux500/include/mach/hardware.h b/arch/arm/mach-ux500/include/mach/hardware.h index 04ea836969b..8656379a830 100644 --- a/arch/arm/mach-ux500/include/mach/hardware.h +++ b/arch/arm/mach-ux500/include/mach/hardware.h @@ -23,109 +23,106 @@ /* typesafe io address */ #define __io_address(n) __io(IO_ADDRESS(n)) +/* used by some plat-nomadik code */ +#define io_p2v(n) __io_address(n) -/* - * Base address definitions for U8500 Onchip IPs. All the - * peripherals are contained in a single 1 Mbyte region, with - * AHB peripherals at the bottom and APB peripherals at the - * top of the region. PER stands for PERIPHERAL region which - * itself divided into sub regions. - */ -#define U8500_PER3_BASE 0x80000000 -#define U8500_PER2_BASE 0x80110000 -#define U8500_PER1_BASE 0x80120000 -#define U8500_PER4_BASE 0x80150000 - -#define U8500_PER6_BASE 0xa03c0000 -#define U8500_PER5_BASE 0xa03e0000 -#define U8500_PER7_BASE 0xa03d0000 - -#define U8500_SVA_BASE 0xa0100000 -#define U8500_SIA_BASE 0xa0200000 - -#define U8500_SGA_BASE 0xa0300000 -#define U8500_MCDE_BASE 0xa0350000 -#define U8500_DMA_BASE 0xa0362000 - -#define U8500_SCU_BASE 0xa0410000 -#define U8500_GIC_CPU_BASE 0xa0410100 -#define U8500_TWD_BASE 0xa0410600 -#define U8500_GIC_DIST_BASE 0xa0411000 -#define U8500_L2CC_BASE 0xa0412000 - -#define U8500_TWD_SIZE 0x100 - -/* per7 base addressess */ -#define U8500_CR_BASE (U8500_PER7_BASE + 0x8000) -#define U8500_MTU0_BASE (U8500_PER7_BASE + 0xa000) -#define U8500_MTU1_BASE (U8500_PER7_BASE + 0xb000) -#define U8500_TZPC0_BASE (U8500_PER7_BASE + 0xc000) -#define U8500_CLKRST7_BASE (U8500_PER7_BASE + 0xf000) - -/* per6 base addressess */ -#define U8500_RNG_BASE (U8500_PER6_BASE + 0x0000) -#define U8500_PKA_BASE (U8500_PER6_BASE + 0x1000) -#define U8500_PKAM_BASE (U8500_PER6_BASE + 0x2000) -#define U8500_CRYPTO0_BASE (U8500_PER6_BASE + 0xa000) -#define U8500_CRYPTO1_BASE (U8500_PER6_BASE + 0xb000) -#define U8500_CLKRST6_BASE (U8500_PER6_BASE + 0xf000) - -/* per5 base addressess */ -#define U8500_USBOTG_BASE (U8500_PER5_BASE + 0x00000) -#define U8500_GPIO5_BASE (U8500_PER5_BASE + 0x1e000) -#define U8500_CLKRST5_BASE (U8500_PER5_BASE + 0x1f000) - -/* per4 base addressess */ -#define U8500_BACKUPRAM0_BASE (U8500_PER4_BASE + 0x0000) -#define U8500_BACKUPRAM1_BASE (U8500_PER4_BASE + 0x1000) -#define U8500_RTT0_BASE (U8500_PER4_BASE + 0x2000) -#define U8500_RTT1_BASE (U8500_PER4_BASE + 0x3000) -#define U8500_RTC_BASE (U8500_PER4_BASE + 0x4000) -#define U8500_SCR_BASE (U8500_PER4_BASE + 0x5000) -#define U8500_DMC_BASE (U8500_PER4_BASE + 0x6000) -#define U8500_PRCMU_BASE (U8500_PER4_BASE + 0x7000) - -/* per3 base addressess */ -#define U8500_FSMC_BASE (U8500_PER3_BASE + 0x0000) -#define U8500_SSP0_BASE (U8500_PER3_BASE + 0x2000) -#define U8500_SSP1_BASE (U8500_PER3_BASE + 0x3000) -#define U8500_I2C0_BASE (U8500_PER3_BASE + 0x4000) -#define U8500_SDI2_BASE (U8500_PER3_BASE + 0x5000) -#define U8500_SKE_BASE (U8500_PER3_BASE + 0x6000) -#define U8500_UART2_BASE (U8500_PER3_BASE + 0x7000) -#define U8500_SDI5_BASE (U8500_PER3_BASE + 0x8000) -#define U8500_GPIO3_BASE (U8500_PER3_BASE + 0xe000) -#define U8500_CLKRST3_BASE (U8500_PER3_BASE + 0xf000) - -/* per2 base addressess */ -#define U8500_I2C3_BASE (U8500_PER2_BASE + 0x0000) -#define U8500_SPI2_BASE (U8500_PER2_BASE + 0x1000) -#define U8500_SPI1_BASE (U8500_PER2_BASE + 0x2000) -#define U8500_PWL_BASE (U8500_PER2_BASE + 0x3000) -#define U8500_SDI4_BASE (U8500_PER2_BASE + 0x4000) -#define U8500_MSP2_BASE (U8500_PER2_BASE + 0x7000) -#define U8500_SDI1_BASE (U8500_PER2_BASE + 0x8000) -#define U8500_SDI3_BASE (U8500_PER2_BASE + 0x9000) -#define U8500_SPI0_BASE (U8500_PER2_BASE + 0xa000) -#define U8500_HSIR_BASE (U8500_PER2_BASE + 0xb000) -#define U8500_HSIT_BASE (U8500_PER2_BASE + 0xc000) -#define U8500_GPIO2_BASE (U8500_PER2_BASE + 0xe000) -#define U8500_CLKRST2_BASE (U8500_PER2_BASE + 0xf000) - -/* per1 base addresses */ -#define U8500_UART0_BASE (U8500_PER1_BASE + 0x0000) -#define U8500_UART1_BASE (U8500_PER1_BASE + 0x1000) -#define U8500_I2C1_BASE (U8500_PER1_BASE + 0x2000) -#define U8500_MSP0_BASE (U8500_PER1_BASE + 0x3000) -#define U8500_MSP1_BASE (U8500_PER1_BASE + 0x4000) -#define U8500_SDI0_BASE (U8500_PER1_BASE + 0x6000) -#define U8500_I2C2_BASE (U8500_PER1_BASE + 0x8000) -#define U8500_SPI3_BASE (U8500_PER1_BASE + 0x9000) -#define U8500_SLIM0_BASE (U8500_PER1_BASE + 0xa000) -#define U8500_GPIO1_BASE (U8500_PER1_BASE + 0xe000) -#define U8500_CLKRST1_BASE (U8500_PER1_BASE + 0xf000) +#include <mach/db8500-regs.h> +#include <mach/db5500-regs.h> + +#ifdef CONFIG_UX500_SOC_DB8500 +#define UX500(periph) U8500_##periph##_BASE +#elif defined(CONFIG_UX500_SOC_DB5500) +#define UX500(periph) U5500_##periph##_BASE +#endif + +#define UX500_BACKUPRAM0_BASE UX500(BACKUPRAM0) +#define UX500_BACKUPRAM1_BASE UX500(BACKUPRAM1) +#define UX500_B2R2_BASE UX500(B2R2) + +#define UX500_CLKRST1_BASE UX500(CLKRST1) +#define UX500_CLKRST2_BASE UX500(CLKRST2) +#define UX500_CLKRST3_BASE UX500(CLKRST3) +#define UX500_CLKRST5_BASE UX500(CLKRST5) +#define UX500_CLKRST6_BASE UX500(CLKRST6) + +#define UX500_DMA_BASE UX500(DMA) +#define UX500_FSMC_BASE UX500(FSMC) + +#define UX500_GIC_CPU_BASE UX500(GIC_CPU) +#define UX500_GIC_DIST_BASE UX500(GIC_DIST) + +#define UX500_I2C1_BASE UX500(I2C1) +#define UX500_I2C2_BASE UX500(I2C2) +#define UX500_I2C3_BASE UX500(I2C3) + +#define UX500_L2CC_BASE UX500(L2CC) +#define UX500_MCDE_BASE UX500(MCDE) +#define UX500_MTU0_BASE UX500(MTU0) +#define UX500_MTU1_BASE UX500(MTU1) +#define UX500_PRCMU_BASE UX500(PRCMU) + +#define UX500_RNG_BASE UX500(RNG) +#define UX500_RTC_BASE UX500(RTC) + +#define UX500_SCU_BASE UX500(SCU) + +#define UX500_SDI0_BASE UX500(SDI0) +#define UX500_SDI1_BASE UX500(SDI1) +#define UX500_SDI2_BASE UX500(SDI2) +#define UX500_SDI3_BASE UX500(SDI3) +#define UX500_SDI4_BASE UX500(SDI4) + +#define UX500_SPI0_BASE UX500(SPI0) +#define UX500_SPI1_BASE UX500(SPI1) +#define UX500_SPI2_BASE UX500(SPI2) +#define UX500_SPI3_BASE UX500(SPI3) + +#define UX500_SIA_BASE UX500(SIA) +#define UX500_SVA_BASE UX500(SVA) + +#define UX500_TWD_BASE UX500(TWD) + +#define UX500_UART0_BASE UX500(UART0) +#define UX500_UART1_BASE UX500(UART1) +#define UX500_UART2_BASE UX500(UART2) + +#define UX500_USBOTG_BASE UX500(USBOTG) /* ST-Ericsson modified pl022 id */ #define SSP_PER_ID 0x01080022 +#ifndef __ASSEMBLY__ + +#include <asm/cputype.h> + +static inline bool cpu_is_u8500(void) +{ +#ifdef CONFIG_UX500_SOC_DB8500 + return 1; +#else + return 0; +#endif +} + +static inline bool cpu_is_u8500ed(void) +{ + return cpu_is_u8500() && (read_cpuid_id() & 15) == 0; +} + +static inline bool cpu_is_u8500v1(void) +{ + return cpu_is_u8500() && (read_cpuid_id() & 15) == 1; +} + +static inline bool cpu_is_u5500(void) +{ +#ifdef CONFIG_UX500_SOC_DB5500 + return 1; +#else + return 0; +#endif +} + +#endif + #endif /* __MACH_HARDWARE_H */ diff --git a/arch/arm/mach-ux500/include/mach/irqs.h b/arch/arm/mach-ux500/include/mach/irqs.h index 394b5dd2200..7970684b1d0 100644 --- a/arch/arm/mach-ux500/include/mach/irqs.h +++ b/arch/arm/mach-ux500/include/mach/irqs.h @@ -42,6 +42,7 @@ #define IRQ_AB4500 (IRQ_SHPI_START + 40) #define IRQ_DISP (IRQ_SHPI_START + 48) #define IRQ_SiPI3 (IRQ_SHPI_START + 49) +#define IRQ_I2C4 (IRQ_SHPI_START + 51) #define IRQ_SSP1 (IRQ_SHPI_START + 52) #define IRQ_I2C2 (IRQ_SHPI_START + 55) #define IRQ_SDMMC0 (IRQ_SHPI_START + 60) @@ -66,6 +67,12 @@ /* There are 128 shared peripheral interrupts assigned to * INTID[160:32]. The first 32 interrupts are reserved. */ -#define NR_IRQS 161 +#define U8500_SOC_NR_IRQS 161 + +/* After chip-specific IRQ numbers we have the GPIO ones */ +#define NOMADIK_NR_GPIO 288 +#define NOMADIK_GPIO_TO_IRQ(gpio) ((gpio) + U8500_SOC_NR_IRQS) +#define NOMADIK_IRQ_TO_GPIO(irq) ((irq) - U8500_SOC_NR_IRQS) +#define NR_IRQS NOMADIK_GPIO_TO_IRQ(NOMADIK_NR_GPIO) #endif /*ASM_ARCH_IRQS_H*/ diff --git a/arch/arm/mach-ux500/include/mach/setup.h b/arch/arm/mach-ux500/include/mach/setup.h index cf0ce1687f2..e978dbd9e21 100644 --- a/arch/arm/mach-ux500/include/mach/setup.h +++ b/arch/arm/mach-ux500/include/mach/setup.h @@ -14,10 +14,28 @@ #include <asm/mach/time.h> #include <linux/init.h> -extern void u8500_map_io(void); -extern void u8500_init_devices(void); -extern void u8500_init_irq(void); +extern void __init ux500_map_io(void); +extern void __init u5500_map_io(void); +extern void __init u8500_map_io(void); + +extern void __init ux500_init_devices(void); +extern void __init u5500_init_devices(void); +extern void __init u8500_init_devices(void); + +extern void __init ux500_init_irq(void); /* We re-use nomadik_timer for this platform */ extern void nmdk_timer_init(void); +extern void __init amba_add_devices(struct amba_device *devs[], int num); + +struct sys_timer; +extern struct sys_timer ux500_timer; + +#define __IO_DEV_DESC(x, sz) { \ + .virtual = IO_ADDRESS(x), \ + .pfn = __phys_to_pfn(x), \ + .length = sz, \ + .type = MT_DEVICE, \ +} + #endif /* __ASM_ARCH_SETUP_H */ |