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-rw-r--r--drivers/media/dvb/frontends/Kconfig15
-rw-r--r--drivers/media/dvb/frontends/Makefile2
-rw-r--r--drivers/media/dvb/frontends/af9013.c55
-rw-r--r--drivers/media/dvb/frontends/atbm8830.h2
-rw-r--r--drivers/media/dvb/frontends/au8522_dig.c6
-rw-r--r--drivers/media/dvb/frontends/bcm3510.c6
-rw-r--r--drivers/media/dvb/frontends/cx22700.c2
-rw-r--r--drivers/media/dvb/frontends/cx22702.c6
-rw-r--r--drivers/media/dvb/frontends/cx24110.c2
-rw-r--r--drivers/media/dvb/frontends/cx24113.h2
-rw-r--r--drivers/media/dvb/frontends/cx24123.c2
-rw-r--r--drivers/media/dvb/frontends/dib0090.c1583
-rw-r--r--drivers/media/dvb/frontends/dib0090.h31
-rw-r--r--drivers/media/dvb/frontends/dib7000p.c1945
-rw-r--r--drivers/media/dvb/frontends/dib7000p.h96
-rw-r--r--drivers/media/dvb/frontends/dib8000.c821
-rw-r--r--drivers/media/dvb/frontends/dib8000.h20
-rw-r--r--drivers/media/dvb/frontends/dib9000.c2351
-rw-r--r--drivers/media/dvb/frontends/dib9000.h131
-rw-r--r--drivers/media/dvb/frontends/dibx000_common.c279
-rw-r--r--drivers/media/dvb/frontends/dibx000_common.h152
-rw-r--r--drivers/media/dvb/frontends/drx397xD.c2
-rw-r--r--drivers/media/dvb/frontends/ds3000.c645
-rw-r--r--drivers/media/dvb/frontends/ds3000.h3
-rw-r--r--drivers/media/dvb/frontends/dvb-pll.c79
-rw-r--r--drivers/media/dvb/frontends/mb86a16.c2
-rw-r--r--drivers/media/dvb/frontends/mb86a20s.c2
-rw-r--r--drivers/media/dvb/frontends/mt312.c2
-rw-r--r--drivers/media/dvb/frontends/s5h1420.c2
-rw-r--r--drivers/media/dvb/frontends/stb6100.c2
-rw-r--r--drivers/media/dvb/frontends/stv0288.c7
-rw-r--r--drivers/media/dvb/frontends/stv0297.c2
-rw-r--r--drivers/media/dvb/frontends/stv0367.c3459
-rw-r--r--drivers/media/dvb/frontends/stv0367.h66
-rw-r--r--drivers/media/dvb/frontends/stv0367_priv.h212
-rw-r--r--drivers/media/dvb/frontends/stv0367_regs.h3614
-rw-r--r--drivers/media/dvb/frontends/stv0900.h2
-rw-r--r--drivers/media/dvb/frontends/stv0900_core.c27
-rw-r--r--drivers/media/dvb/frontends/stv0900_priv.h2
-rw-r--r--drivers/media/dvb/frontends/stv090x.c307
-rw-r--r--drivers/media/dvb/frontends/stv090x.h16
-rw-r--r--drivers/media/dvb/frontends/stv090x_reg.h16
-rw-r--r--drivers/media/dvb/frontends/zl10036.c10
43 files changed, 14272 insertions, 1716 deletions
diff --git a/drivers/media/dvb/frontends/Kconfig b/drivers/media/dvb/frontends/Kconfig
index b8519ba511e..83093d1f4f7 100644
--- a/drivers/media/dvb/frontends/Kconfig
+++ b/drivers/media/dvb/frontends/Kconfig
@@ -349,6 +349,14 @@ config DVB_DIB7000P
A DVB-T tuner module. Designed for mobile usage. Say Y when you want
to support this frontend.
+config DVB_DIB9000
+ tristate "DiBcom 9000"
+ depends on DVB_CORE && I2C
+ default m if DVB_FE_CUSTOMISE
+ help
+ A DVB-T tuner module. Designed for mobile usage. Say Y when you want
+ to support this frontend.
+
config DVB_TDA10048
tristate "Philips TDA10048HN based"
depends on DVB_CORE && I2C
@@ -370,6 +378,13 @@ config DVB_EC100
help
Say Y when you want to support this frontend.
+config DVB_STV0367
+ tristate "ST STV0367 based"
+ depends on DVB_CORE && I2C
+ default m if DVB_FE_CUSTOMISE
+ help
+ A DVB-T/C tuner module. Say Y when you want to support this frontend.
+
comment "DVB-C (cable) frontends"
depends on DVB_CORE
diff --git a/drivers/media/dvb/frontends/Makefile b/drivers/media/dvb/frontends/Makefile
index b1d9525aa7e..3b0c4bdc4b2 100644
--- a/drivers/media/dvb/frontends/Makefile
+++ b/drivers/media/dvb/frontends/Makefile
@@ -24,6 +24,7 @@ obj-$(CONFIG_DVB_DIB3000MC) += dib3000mc.o dibx000_common.o
obj-$(CONFIG_DVB_DIB7000M) += dib7000m.o dibx000_common.o
obj-$(CONFIG_DVB_DIB7000P) += dib7000p.o dibx000_common.o
obj-$(CONFIG_DVB_DIB8000) += dib8000.o dibx000_common.o
+obj-$(CONFIG_DVB_DIB9000) += dib9000.o dibx000_common.o
obj-$(CONFIG_DVB_MT312) += mt312.o
obj-$(CONFIG_DVB_VES1820) += ves1820.o
obj-$(CONFIG_DVB_VES1X93) += ves1x93.o
@@ -83,3 +84,4 @@ obj-$(CONFIG_DVB_DS3000) += ds3000.o
obj-$(CONFIG_DVB_MB86A16) += mb86a16.o
obj-$(CONFIG_DVB_MB86A20S) += mb86a20s.o
obj-$(CONFIG_DVB_IX2505V) += ix2505v.o
+obj-$(CONFIG_DVB_STV0367) += stv0367.o
diff --git a/drivers/media/dvb/frontends/af9013.c b/drivers/media/dvb/frontends/af9013.c
index ba25fa0b0fc..345311c3338 100644
--- a/drivers/media/dvb/frontends/af9013.c
+++ b/drivers/media/dvb/frontends/af9013.c
@@ -1323,13 +1323,11 @@ static struct dvb_frontend_ops af9013_ops;
static int af9013_download_firmware(struct af9013_state *state)
{
- int i, len, packets, remainder, ret;
+ int i, len, remaining, ret;
const struct firmware *fw;
- u16 addr = 0x5100; /* firmware start address */
u16 checksum = 0;
u8 val;
u8 fw_params[4];
- u8 *data;
u8 *fw_file = AF9013_DEFAULT_FIRMWARE;
msleep(100);
@@ -1373,21 +1371,18 @@ static int af9013_download_firmware(struct af9013_state *state)
if (ret)
goto error_release;
- #define FW_PACKET_MAX_DATA 16
-
- packets = fw->size / FW_PACKET_MAX_DATA;
- remainder = fw->size % FW_PACKET_MAX_DATA;
- len = FW_PACKET_MAX_DATA;
- for (i = 0; i <= packets; i++) {
- if (i == packets) /* set size of the last packet */
- len = remainder;
-
- data = (u8 *)(fw->data + i * FW_PACKET_MAX_DATA);
- ret = af9013_write_ofsm_regs(state, addr, data, len);
- addr += FW_PACKET_MAX_DATA;
+ #define FW_ADDR 0x5100 /* firmware start address */
+ #define LEN_MAX 16 /* max packet size */
+ for (remaining = fw->size; remaining > 0; remaining -= LEN_MAX) {
+ len = remaining;
+ if (len > LEN_MAX)
+ len = LEN_MAX;
+ ret = af9013_write_ofsm_regs(state,
+ FW_ADDR + fw->size - remaining,
+ (u8 *) &fw->data[fw->size - remaining], len);
if (ret) {
- err("firmware download failed at %d with %d", i, ret);
+ err("firmware download failed:%d", ret);
goto error_release;
}
}
@@ -1466,20 +1461,6 @@ struct dvb_frontend *af9013_attach(const struct af9013_config *config,
state->i2c = i2c;
memcpy(&state->config, config, sizeof(struct af9013_config));
- /* chip version */
- ret = af9013_read_reg_bits(state, 0xd733, 4, 4, &buf[2]);
- if (ret)
- goto error;
-
- /* ROM version */
- for (i = 0; i < 2; i++) {
- ret = af9013_read_reg(state, 0x116b + i, &buf[i]);
- if (ret)
- goto error;
- }
- deb_info("%s: chip version:%d ROM version:%d.%d\n", __func__,
- buf[2], buf[0], buf[1]);
-
/* download firmware */
if (state->config.output_mode != AF9013_OUTPUT_MODE_USB) {
ret = af9013_download_firmware(state);
@@ -1495,6 +1476,20 @@ struct dvb_frontend *af9013_attach(const struct af9013_config *config,
}
info("firmware version:%d.%d.%d.%d", buf[0], buf[1], buf[2], buf[3]);
+ /* chip version */
+ ret = af9013_read_reg_bits(state, 0xd733, 4, 4, &buf[2]);
+ if (ret)
+ goto error;
+
+ /* ROM version */
+ for (i = 0; i < 2; i++) {
+ ret = af9013_read_reg(state, 0x116b + i, &buf[i]);
+ if (ret)
+ goto error;
+ }
+ deb_info("%s: chip version:%d ROM version:%d.%d\n", __func__,
+ buf[2], buf[0], buf[1]);
+
/* settings for mp2if */
if (state->config.output_mode == AF9013_OUTPUT_MODE_USB) {
/* AF9015 split PSB to 1.5k + 0.5k */
diff --git a/drivers/media/dvb/frontends/atbm8830.h b/drivers/media/dvb/frontends/atbm8830.h
index e8149f39330..024273374bd 100644
--- a/drivers/media/dvb/frontends/atbm8830.h
+++ b/drivers/media/dvb/frontends/atbm8830.h
@@ -39,7 +39,7 @@ struct atbm8830_config {
/* parallel or serial transport stream */
u8 serial_ts;
- /* transport stream clock output only when receving valid stream */
+ /* transport stream clock output only when receiving valid stream */
u8 ts_clk_gated;
/* Decoder sample TS data at rising edge of clock */
diff --git a/drivers/media/dvb/frontends/au8522_dig.c b/drivers/media/dvb/frontends/au8522_dig.c
index 65f6a36dfb2..1d572940e24 100644
--- a/drivers/media/dvb/frontends/au8522_dig.c
+++ b/drivers/media/dvb/frontends/au8522_dig.c
@@ -635,7 +635,7 @@ static int au8522_led_gpio_enable(struct au8522_state *state, int onoff)
struct au8522_led_config *led_config = state->config->led_cfg;
u8 val;
- /* bail out if we cant control an LED */
+ /* bail out if we can't control an LED */
if (!led_config || !led_config->gpio_output ||
!led_config->gpio_output_enable || !led_config->gpio_output_disable)
return 0;
@@ -665,7 +665,7 @@ static int au8522_led_ctrl(struct au8522_state *state, int led)
struct au8522_led_config *led_config = state->config->led_cfg;
int i, ret = 0;
- /* bail out if we cant control an LED */
+ /* bail out if we can't control an LED */
if (!led_config || !led_config->gpio_leds ||
!led_config->num_led_states || !led_config->led_states)
return 0;
@@ -803,7 +803,7 @@ static int au8522_led_status(struct au8522_state *state, const u16 *snr)
int led;
u16 strong;
- /* bail out if we cant control an LED */
+ /* bail out if we can't control an LED */
if (!led_config)
return 0;
diff --git a/drivers/media/dvb/frontends/bcm3510.c b/drivers/media/dvb/frontends/bcm3510.c
index cf5e576dfdc..8aff5868a5e 100644
--- a/drivers/media/dvb/frontends/bcm3510.c
+++ b/drivers/media/dvb/frontends/bcm3510.c
@@ -155,7 +155,7 @@ static int bcm3510_hab_send_request(struct bcm3510_state *st, u8 *buf, int len)
unsigned long t;
/* Check if any previous HAB request still needs to be serviced by the
- * Aquisition Processor before sending new request */
+ * Acquisition Processor before sending new request */
if ((ret = bcm3510_readB(st,0xa8,&v)) < 0)
return ret;
if (v.HABSTAT_a8.HABR) {
@@ -361,7 +361,7 @@ static int bcm3510_tuner_cmd(struct bcm3510_state* st,u8 bc, u16 n, u8 a)
/* Set duration of the initial state of TUNCTL = 3.34 micro Sec */
c.TUNCTL_state = 0x40;
-/* PRESCALER DEVIDE RATIO | BC1_2_3_4; (band switch), 1stosc REFERENCE COUNTER REF_S12 and REF_S11 */
+/* PRESCALER DIVIDE RATIO | BC1_2_3_4; (band switch), 1stosc REFERENCE COUNTER REF_S12 and REF_S11 */
c.ctl_dat[0].ctrl.size = BITS_8;
c.ctl_dat[0].data = 0x80 | bc;
@@ -397,7 +397,7 @@ static int bcm3510_tuner_cmd(struct bcm3510_state* st,u8 bc, u16 n, u8 a)
c.ctl_dat[7].ctrl.cs0 = 1;
c.ctl_dat[7].data = 0x40;
-/* PRESCALER DEVIDE RATIO, 2ndosc REFERENCE COUNTER REF_S12 and REF_S11 */
+/* PRESCALER DIVIDE RATIO, 2ndosc REFERENCE COUNTER REF_S12 and REF_S11 */
c.ctl_dat[8].ctrl.size = BITS_8;
c.ctl_dat[8].data = 0x80;
diff --git a/drivers/media/dvb/frontends/cx22700.c b/drivers/media/dvb/frontends/cx22700.c
index 5fbc0fc37ec..0142214b013 100644
--- a/drivers/media/dvb/frontends/cx22700.c
+++ b/drivers/media/dvb/frontends/cx22700.c
@@ -179,7 +179,7 @@ static int cx22700_set_tps (struct cx22700_state *state, struct dvb_ofdm_paramet
cx22700_writereg (state, 0x06, val);
cx22700_writereg (state, 0x08, 0x04 | 0x02); /* use user tps parameters */
- cx22700_writereg (state, 0x08, 0x04); /* restart aquisition */
+ cx22700_writereg (state, 0x08, 0x04); /* restart acquisition */
return 0;
}
diff --git a/drivers/media/dvb/frontends/cx22702.c b/drivers/media/dvb/frontends/cx22702.c
index ff6c4983051..3139558148b 100644
--- a/drivers/media/dvb/frontends/cx22702.c
+++ b/drivers/media/dvb/frontends/cx22702.c
@@ -55,7 +55,7 @@ MODULE_PARM_DESC(debug, "Enable verbose debug messages");
/* Register values to initialise the demod */
static const u8 init_tab[] = {
- 0x00, 0x00, /* Stop aquisition */
+ 0x00, 0x00, /* Stop acquisition */
0x0B, 0x06,
0x09, 0x01,
0x0D, 0x41,
@@ -310,7 +310,7 @@ static int cx22702_set_tps(struct dvb_frontend *fe,
& 0xfc);
cx22702_writereg(state, 0x0C,
(cx22702_readreg(state, 0x0C) & 0xBF) | 0x40);
- cx22702_writereg(state, 0x00, 0x01); /* Begin aquisition */
+ cx22702_writereg(state, 0x00, 0x01); /* Begin acquisition */
dprintk("%s: Autodetecting\n", __func__);
return 0;
}
@@ -424,7 +424,7 @@ static int cx22702_set_tps(struct dvb_frontend *fe,
cx22702_writereg(state, 0x0C,
(cx22702_readreg(state, 0x0C) & 0xBF) | 0x40);
- /* Begin channel aquisition */
+ /* Begin channel acquisition */
cx22702_writereg(state, 0x00, 0x01);
return 0;
diff --git a/drivers/media/dvb/frontends/cx24110.c b/drivers/media/dvb/frontends/cx24110.c
index 7a1a5bc337d..bf9c999aa47 100644
--- a/drivers/media/dvb/frontends/cx24110.c
+++ b/drivers/media/dvb/frontends/cx24110.c
@@ -544,7 +544,7 @@ static int cx24110_set_frontend(struct dvb_frontend* fe, struct dvb_frontend_par
cx24110_set_inversion (state, p->inversion);
cx24110_set_fec (state, p->u.qpsk.fec_inner);
cx24110_set_symbolrate (state, p->u.qpsk.symbol_rate);
- cx24110_writereg(state,0x04,0x05); /* start aquisition */
+ cx24110_writereg(state,0x04,0x05); /* start acquisition */
return 0;
}
diff --git a/drivers/media/dvb/frontends/cx24113.h b/drivers/media/dvb/frontends/cx24113.h
index 5de0f7ffd8d..01eb7b9c28f 100644
--- a/drivers/media/dvb/frontends/cx24113.h
+++ b/drivers/media/dvb/frontends/cx24113.h
@@ -1,5 +1,5 @@
/*
- * Driver for Conexant CX24113/CX24128 Tuner (Satelite)
+ * Driver for Conexant CX24113/CX24128 Tuner (Satellite)
*
* Copyright (C) 2007-8 Patrick Boettcher <pb@linuxtv.org>
*
diff --git a/drivers/media/dvb/frontends/cx24123.c b/drivers/media/dvb/frontends/cx24123.c
index fad6a990a39..b1dd8acc607 100644
--- a/drivers/media/dvb/frontends/cx24123.c
+++ b/drivers/media/dvb/frontends/cx24123.c
@@ -949,7 +949,7 @@ static int cx24123_set_frontend(struct dvb_frontend *fe,
else
err("it seems I don't have a tuner...");
- /* Enable automatic aquisition and reset cycle */
+ /* Enable automatic acquisition and reset cycle */
cx24123_writereg(state, 0x03, (cx24123_readreg(state, 0x03) | 0x07));
cx24123_writereg(state, 0x00, 0x10);
cx24123_writereg(state, 0x00, 0);
diff --git a/drivers/media/dvb/frontends/dib0090.c b/drivers/media/dvb/frontends/dib0090.c
index 65240b7801e..52ff1a252a9 100644
--- a/drivers/media/dvb/frontends/dib0090.c
+++ b/drivers/media/dvb/frontends/dib0090.c
@@ -45,6 +45,7 @@ MODULE_PARM_DESC(debug, "turn on debugging (default: 0)");
} \
} while (0)
+#define CONFIG_SYS_DVBT
#define CONFIG_SYS_ISDBT
#define CONFIG_BAND_CBAND
#define CONFIG_BAND_VHF
@@ -76,6 +77,34 @@ MODULE_PARM_DESC(debug, "turn on debugging (default: 0)");
#define EN_SBD 0x44E9
#define EN_CAB 0x88E9
+/* Calibration defines */
+#define DC_CAL 0x1
+#define WBD_CAL 0x2
+#define TEMP_CAL 0x4
+#define CAPTRIM_CAL 0x8
+
+#define KROSUS_PLL_LOCKED 0x800
+#define KROSUS 0x2
+
+/* Use those defines to identify SOC version */
+#define SOC 0x02
+#define SOC_7090_P1G_11R1 0x82
+#define SOC_7090_P1G_21R1 0x8a
+#define SOC_8090_P1G_11R1 0x86
+#define SOC_8090_P1G_21R1 0x8e
+
+/* else use thos ones to check */
+#define P1A_B 0x0
+#define P1C 0x1
+#define P1D_E_F 0x3
+#define P1G 0x7
+#define P1G_21R2 0xf
+
+#define MP001 0x1 /* Single 9090/8096 */
+#define MP005 0x4 /* Single Sband */
+#define MP008 0x6 /* Dual diversity VHF-UHF-LBAND */
+#define MP009 0x7 /* Dual diversity 29098 CBAND-UHF-LBAND-SBAND */
+
#define pgm_read_word(w) (*w)
struct dc_calibration;
@@ -84,7 +113,7 @@ struct dib0090_tuning {
u32 max_freq; /* for every frequency less than or equal to that field: this information is correct */
u8 switch_trim;
u8 lna_tune;
- u8 lna_bias;
+ u16 lna_bias;
u16 v2i;
u16 mix;
u16 load;
@@ -99,13 +128,19 @@ struct dib0090_pll {
u8 topresc;
};
+struct dib0090_identity {
+ u8 version;
+ u8 product;
+ u8 p1g;
+ u8 in_soc;
+};
+
struct dib0090_state {
struct i2c_adapter *i2c;
struct dvb_frontend *fe;
const struct dib0090_config *config;
u8 current_band;
- u16 revision;
enum frontend_tune_state tune_state;
u32 current_rf;
@@ -143,7 +178,26 @@ struct dib0090_state {
u8 tuner_is_tuned;
u8 agc_freeze;
- u8 reset;
+ struct dib0090_identity identity;
+
+ u32 rf_request;
+ u8 current_standard;
+
+ u8 calibrate;
+ u32 rest;
+ u16 bias;
+ s16 temperature;
+
+ u8 wbd_calibration_gain;
+ const struct dib0090_wbd_slope *current_wbd_table;
+ u16 wbdmux;
+};
+
+struct dib0090_fw_state {
+ struct i2c_adapter *i2c;
+ struct dvb_frontend *fe;
+ struct dib0090_identity identity;
+ const struct dib0090_config *config;
};
static u16 dib0090_read_reg(struct dib0090_state *state, u8 reg)
@@ -171,6 +225,28 @@ static int dib0090_write_reg(struct dib0090_state *state, u32 reg, u16 val)
return 0;
}
+static u16 dib0090_fw_read_reg(struct dib0090_fw_state *state, u8 reg)
+{
+ u8 b[2];
+ struct i2c_msg msg = {.addr = reg, .flags = I2C_M_RD, .buf = b, .len = 2 };
+ if (i2c_transfer(state->i2c, &msg, 1) != 1) {
+ printk(KERN_WARNING "DiB0090 I2C read failed\n");
+ return 0;
+ }
+ return (b[0] << 8) | b[1];
+}
+
+static int dib0090_fw_write_reg(struct dib0090_fw_state *state, u8 reg, u16 val)
+{
+ u8 b[2] = { val >> 8, val & 0xff };
+ struct i2c_msg msg = {.addr = reg, .flags = 0, .buf = b, .len = 2 };
+ if (i2c_transfer(state->i2c, &msg, 1) != 1) {
+ printk(KERN_WARNING "DiB0090 I2C write failed\n");
+ return -EREMOTEIO;
+ }
+ return 0;
+}
+
#define HARD_RESET(state) do { if (cfg->reset) { if (cfg->sleep) cfg->sleep(fe, 0); msleep(10); cfg->reset(fe, 1); msleep(10); cfg->reset(fe, 0); msleep(10); } } while (0)
#define ADC_TARGET -220
#define GAIN_ALPHA 5
@@ -183,89 +259,327 @@ static void dib0090_write_regs(struct dib0090_state *state, u8 r, const u16 * b,
} while (--c);
}
-static u16 dib0090_identify(struct dvb_frontend *fe)
+static int dib0090_identify(struct dvb_frontend *fe)
{
struct dib0090_state *state = fe->tuner_priv;
u16 v;
+ struct dib0090_identity *identity = &state->identity;
v = dib0090_read_reg(state, 0x1a);
-#ifdef FIRMWARE_FIREFLY
- /* pll is not locked locked */
- if (!(v & 0x800))
- dprintk("FE%d : Identification : pll is not yet locked", fe->id);
-#endif
+ identity->p1g = 0;
+ identity->in_soc = 0;
+
+ dprintk("Tuner identification (Version = 0x%04x)", v);
/* without PLL lock info */
- v &= 0x3ff;
- dprintk("P/V: %04x:", v);
+ v &= ~KROSUS_PLL_LOCKED;
- if ((v >> 8) & 0xf)
- dprintk("FE%d : Product ID = 0x%x : KROSUS", fe->id, (v >> 8) & 0xf);
- else
- return 0xff;
-
- v &= 0xff;
- if (((v >> 5) & 0x7) == 0x1)
- dprintk("FE%d : MP001 : 9090/8096", fe->id);
- else if (((v >> 5) & 0x7) == 0x4)
- dprintk("FE%d : MP005 : Single Sband", fe->id);
- else if (((v >> 5) & 0x7) == 0x6)
- dprintk("FE%d : MP008 : diversity VHF-UHF-LBAND", fe->id);
- else if (((v >> 5) & 0x7) == 0x7)
- dprintk("FE%d : MP009 : diversity 29098 CBAND-UHF-LBAND-SBAND", fe->id);
- else
- return 0xff;
-
- /* revision only */
- if ((v & 0x1f) == 0x3)
- dprintk("FE%d : P1-D/E/F detected", fe->id);
- else if ((v & 0x1f) == 0x1)
- dprintk("FE%d : P1C detected", fe->id);
- else if ((v & 0x1f) == 0x0) {
-#ifdef CONFIG_TUNER_DIB0090_P1B_SUPPORT
- dprintk("FE%d : P1-A/B detected: using previous driver - support will be removed soon", fe->id);
- dib0090_p1b_register(fe);
-#else
- dprintk("FE%d : P1-A/B detected: driver is deactivated - not available", fe->id);
- return 0xff;
-#endif
+ identity->version = v & 0xff;
+ identity->product = (v >> 8) & 0xf;
+
+ if (identity->product != KROSUS)
+ goto identification_error;
+
+ if ((identity->version & 0x3) == SOC) {
+ identity->in_soc = 1;
+ switch (identity->version) {
+ case SOC_8090_P1G_11R1:
+ dprintk("SOC 8090 P1-G11R1 Has been detected");
+ identity->p1g = 1;
+ break;
+ case SOC_8090_P1G_21R1:
+ dprintk("SOC 8090 P1-G21R1 Has been detected");
+ identity->p1g = 1;
+ break;
+ case SOC_7090_P1G_11R1:
+ dprintk("SOC 7090 P1-G11R1 Has been detected");
+ identity->p1g = 1;
+ break;
+ case SOC_7090_P1G_21R1:
+ dprintk("SOC 7090 P1-G21R1 Has been detected");
+ identity->p1g = 1;
+ break;
+ default:
+ goto identification_error;
+ }
+ } else {
+ switch ((identity->version >> 5) & 0x7) {
+ case MP001:
+ dprintk("MP001 : 9090/8096");
+ break;
+ case MP005:
+ dprintk("MP005 : Single Sband");
+ break;
+ case MP008:
+ dprintk("MP008 : diversity VHF-UHF-LBAND");
+ break;
+ case MP009:
+ dprintk("MP009 : diversity 29098 CBAND-UHF-LBAND-SBAND");
+ break;
+ default:
+ goto identification_error;
+ }
+
+ switch (identity->version & 0x1f) {
+ case P1G_21R2:
+ dprintk("P1G_21R2 detected");
+ identity->p1g = 1;
+ break;
+ case P1G:
+ dprintk("P1G detected");
+ identity->p1g = 1;
+ break;
+ case P1D_E_F:
+ dprintk("P1D/E/F detected");
+ break;
+ case P1C:
+ dprintk("P1C detected");
+ break;
+ case P1A_B:
+ dprintk("P1-A/B detected: driver is deactivated - not available");
+ goto identification_error;
+ break;
+ default:
+ goto identification_error;
+ }
}
- return v;
+ return 0;
+
+identification_error:
+ return -EIO;
+}
+
+static int dib0090_fw_identify(struct dvb_frontend *fe)
+{
+ struct dib0090_fw_state *state = fe->tuner_priv;
+ struct dib0090_identity *identity = &state->identity;
+
+ u16 v = dib0090_fw_read_reg(state, 0x1a);
+ identity->p1g = 0;
+ identity->in_soc = 0;
+
+ dprintk("FE: Tuner identification (Version = 0x%04x)", v);
+
+ /* without PLL lock info */
+ v &= ~KROSUS_PLL_LOCKED;
+
+ identity->version = v & 0xff;
+ identity->product = (v >> 8) & 0xf;
+
+ if (identity->product != KROSUS)
+ goto identification_error;
+
+ if ((identity->version & 0x3) == SOC) {
+ identity->in_soc = 1;
+ switch (identity->version) {
+ case SOC_8090_P1G_11R1:
+ dprintk("SOC 8090 P1-G11R1 Has been detected");
+ identity->p1g = 1;
+ break;
+ case SOC_8090_P1G_21R1:
+ dprintk("SOC 8090 P1-G21R1 Has been detected");
+ identity->p1g = 1;
+ break;
+ case SOC_7090_P1G_11R1:
+ dprintk("SOC 7090 P1-G11R1 Has been detected");
+ identity->p1g = 1;
+ break;
+ case SOC_7090_P1G_21R1:
+ dprintk("SOC 7090 P1-G21R1 Has been detected");
+ identity->p1g = 1;
+ break;
+ default:
+ goto identification_error;
+ }
+ } else {
+ switch ((identity->version >> 5) & 0x7) {
+ case MP001:
+ dprintk("MP001 : 9090/8096");
+ break;
+ case MP005:
+ dprintk("MP005 : Single Sband");
+ break;
+ case MP008:
+ dprintk("MP008 : diversity VHF-UHF-LBAND");
+ break;
+ case MP009:
+ dprintk("MP009 : diversity 29098 CBAND-UHF-LBAND-SBAND");
+ break;
+ default:
+ goto identification_error;
+ }
+
+ switch (identity->version & 0x1f) {
+ case P1G_21R2:
+ dprintk("P1G_21R2 detected");
+ identity->p1g = 1;
+ break;
+ case P1G:
+ dprintk("P1G detected");
+ identity->p1g = 1;
+ break;
+ case P1D_E_F:
+ dprintk("P1D/E/F detected");
+ break;
+ case P1C:
+ dprintk("P1C detected");
+ break;
+ case P1A_B:
+ dprintk("P1-A/B detected: driver is deactivated - not available");
+ goto identification_error;
+ break;
+ default:
+ goto identification_error;
+ }
+ }
+
+ return 0;
+
+identification_error:
+ return -EIO;;
}
static void dib0090_reset_digital(struct dvb_frontend *fe, const struct dib0090_config *cfg)
{
struct dib0090_state *state = fe->tuner_priv;
+ u16 PllCfg, i, v;
HARD_RESET(state);
- dib0090_write_reg(state, 0x24, EN_PLL);
+ dib0090_write_reg(state, 0x24, EN_PLL | EN_CRYSTAL);
dib0090_write_reg(state, 0x1b, EN_DIGCLK | EN_PLL | EN_CRYSTAL); /* PLL, DIG_CLK and CRYSTAL remain */
- /* adcClkOutRatio=8->7, release reset */
- dib0090_write_reg(state, 0x20, ((cfg->io.adc_clock_ratio - 1) << 11) | (0 << 10) | (1 << 9) | (1 << 8) | (0 << 4) | 0);
+ if (!cfg->in_soc) {
+ /* adcClkOutRatio=8->7, release reset */
+ dib0090_write_reg(state, 0x20, ((cfg->io.adc_clock_ratio - 1) << 11) | (0 << 10) | (1 << 9) | (1 << 8) | (0 << 4) | 0);
+ if (cfg->clkoutdrive != 0)
+ dib0090_write_reg(state, 0x23, (0 << 15) | ((!cfg->analog_output) << 14) | (2 << 10) | (1 << 9) | (0 << 8)
+ | (cfg->clkoutdrive << 5) | (cfg->clkouttobamse << 4) | (0 << 2) | (0));
+ else
+ dib0090_write_reg(state, 0x23, (0 << 15) | ((!cfg->analog_output) << 14) | (2 << 10) | (1 << 9) | (0 << 8)
+ | (7 << 5) | (cfg->clkouttobamse << 4) | (0 << 2) | (0));
+ }
+
+ /* Read Pll current config * */
+ PllCfg = dib0090_read_reg(state, 0x21);
+
+ /** Reconfigure PLL if current setting is different from default setting **/
+ if ((PllCfg & 0x1FFF) != ((cfg->io.pll_range << 12) | (cfg->io.pll_loopdiv << 6) | (cfg->io.pll_prediv)) && (!cfg->in_soc)
+ && !cfg->io.pll_bypass) {
+
+ /* Set Bypass mode */
+ PllCfg |= (1 << 15);
+ dib0090_write_reg(state, 0x21, PllCfg);
+
+ /* Set Reset Pll */
+ PllCfg &= ~(1 << 13);
+ dib0090_write_reg(state, 0x21, PllCfg);
+
+ /*** Set new Pll configuration in bypass and reset state ***/
+ PllCfg = (1 << 15) | (0 << 13) | (cfg->io.pll_range << 12) | (cfg->io.pll_loopdiv << 6) | (cfg->io.pll_prediv);
+ dib0090_write_reg(state, 0x21, PllCfg);
+
+ /* Remove Reset Pll */
+ PllCfg |= (1 << 13);
+ dib0090_write_reg(state, 0x21, PllCfg);
+
+ /*** Wait for PLL lock ***/
+ i = 100;
+ do {
+ v = !!(dib0090_read_reg(state, 0x1a) & 0x800);
+ if (v)
+ break;
+ } while (--i);
+
+ if (i == 0) {
+ dprintk("Pll: Unable to lock Pll");
+ return;
+ }
+
+ /* Finally Remove Bypass mode */
+ PllCfg &= ~(1 << 15);
+ dib0090_write_reg(state, 0x21, PllCfg);
+ }
+
+ if (cfg->io.pll_bypass) {
+ PllCfg |= (cfg->io.pll_bypass << 15);
+ dib0090_write_reg(state, 0x21, PllCfg);
+ }
+}
+
+static int dib0090_fw_reset_digital(struct dvb_frontend *fe, const struct dib0090_config *cfg)
+{
+ struct dib0090_fw_state *state = fe->tuner_priv;
+ u16 PllCfg;
+ u16 v;
+ int i;
+
+ dprintk("fw reset digital");
+ HARD_RESET(state);
+
+ dib0090_fw_write_reg(state, 0x24, EN_PLL | EN_CRYSTAL);
+ dib0090_fw_write_reg(state, 0x1b, EN_DIGCLK | EN_PLL | EN_CRYSTAL); /* PLL, DIG_CLK and CRYSTAL remain */
+
+ dib0090_fw_write_reg(state, 0x20,
+ ((cfg->io.adc_clock_ratio - 1) << 11) | (0 << 10) | (1 << 9) | (1 << 8) | (cfg->data_tx_drv << 4) | cfg->ls_cfg_pad_drv);
+
+ v = (0 << 15) | ((!cfg->analog_output) << 14) | (1 << 9) | (0 << 8) | (cfg->clkouttobamse << 4) | (0 << 2) | (0);
if (cfg->clkoutdrive != 0)
- dib0090_write_reg(state, 0x23,
- (0 << 15) | ((!cfg->analog_output) << 14) | (1 << 10) | (1 << 9) | (0 << 8) | (cfg->clkoutdrive << 5) | (cfg->
- clkouttobamse
- << 4) | (0
- <<
- 2)
- | (0));
+ v |= cfg->clkoutdrive << 5;
else
- dib0090_write_reg(state, 0x23,
- (0 << 15) | ((!cfg->analog_output) << 14) | (1 << 10) | (1 << 9) | (0 << 8) | (7 << 5) | (cfg->
- clkouttobamse << 4) | (0
- <<
- 2)
- | (0));
+ v |= 7 << 5;
+
+ v |= 2 << 10;
+ dib0090_fw_write_reg(state, 0x23, v);
+
+ /* Read Pll current config * */
+ PllCfg = dib0090_fw_read_reg(state, 0x21);
+
+ /** Reconfigure PLL if current setting is different from default setting **/
+ if ((PllCfg & 0x1FFF) != ((cfg->io.pll_range << 12) | (cfg->io.pll_loopdiv << 6) | (cfg->io.pll_prediv)) && !cfg->io.pll_bypass) {
- /* enable pll, de-activate reset, ratio: 2/1 = 60MHz */
- dib0090_write_reg(state, 0x21,
- (cfg->io.pll_bypass << 15) | (1 << 13) | (cfg->io.pll_range << 12) | (cfg->io.pll_loopdiv << 6) | (cfg->io.pll_prediv));
+ /* Set Bypass mode */
+ PllCfg |= (1 << 15);
+ dib0090_fw_write_reg(state, 0x21, PllCfg);
+ /* Set Reset Pll */
+ PllCfg &= ~(1 << 13);
+ dib0090_fw_write_reg(state, 0x21, PllCfg);
+
+ /*** Set new Pll configuration in bypass and reset state ***/
+ PllCfg = (1 << 15) | (0 << 13) | (cfg->io.pll_range << 12) | (cfg->io.pll_loopdiv << 6) | (cfg->io.pll_prediv);
+ dib0090_fw_write_reg(state, 0x21, PllCfg);
+
+ /* Remove Reset Pll */
+ PllCfg |= (1 << 13);
+ dib0090_fw_write_reg(state, 0x21, PllCfg);
+
+ /*** Wait for PLL lock ***/
+ i = 100;
+ do {
+ v = !!(dib0090_fw_read_reg(state, 0x1a) & 0x800);
+ if (v)
+ break;
+ } while (--i);
+
+ if (i == 0) {
+ dprintk("Pll: Unable to lock Pll");
+ return -EIO;
+ }
+
+ /* Finally Remove Bypass mode */
+ PllCfg &= ~(1 << 15);
+ dib0090_fw_write_reg(state, 0x21, PllCfg);
+ }
+
+ if (cfg->io.pll_bypass) {
+ PllCfg |= (cfg->io.pll_bypass << 15);
+ dib0090_fw_write_reg(state, 0x21, PllCfg);
+ }
+
+ return dib0090_fw_identify(fe);
}
static int dib0090_wakeup(struct dvb_frontend *fe)
@@ -273,6 +587,9 @@ static int dib0090_wakeup(struct dvb_frontend *fe)
struct dib0090_state *state = fe->tuner_priv;
if (state->config->sleep)
state->config->sleep(fe, 0);
+
+ /* enable dataTX in case we have been restarted in the wrong moment */
+ dib0090_write_reg(state, 0x23, dib0090_read_reg(state, 0x23) | (1 << 14));
return 0;
}
@@ -292,8 +609,75 @@ void dib0090_dcc_freq(struct dvb_frontend *fe, u8 fast)
else
dib0090_write_reg(state, 0x04, 1);
}
+
EXPORT_SYMBOL(dib0090_dcc_freq);
+static const u16 bb_ramp_pwm_normal_socs[] = {
+ 550, /* max BB gain in 10th of dB */
+ (1 << 9) | 8, /* ramp_slope = 1dB of gain -> clock_ticks_per_db = clk_khz / ramp_slope -> BB_RAMP2 */
+ 440,
+ (4 << 9) | 0, /* BB_RAMP3 = 26dB */
+ (0 << 9) | 208, /* BB_RAMP4 */
+ (4 << 9) | 208, /* BB_RAMP5 = 29dB */
+ (0 << 9) | 440, /* BB_RAMP6 */
+};
+
+static const u16 rf_ramp_pwm_cband_7090[] = {
+ 280, /* max RF gain in 10th of dB */
+ 18, /* ramp_slope = 1dB of gain -> clock_ticks_per_db = clk_khz / ramp_slope -> RF_RAMP2 */
+ 504, /* ramp_max = maximum X used on the ramp */
+ (29 << 10) | 364, /* RF_RAMP5, LNA 1 = 8dB */
+ (0 << 10) | 504, /* RF_RAMP6, LNA 1 */
+ (60 << 10) | 228, /* RF_RAMP7, LNA 2 = 7.7dB */
+ (0 << 10) | 364, /* RF_RAMP8, LNA 2 */
+ (34 << 10) | 109, /* GAIN_4_1, LNA 3 = 6.8dB */
+ (0 << 10) | 228, /* GAIN_4_2, LNA 3 */
+ (37 << 10) | 0, /* RF_RAMP3, LNA 4 = 6.2dB */
+ (0 << 10) | 109, /* RF_RAMP4, LNA 4 */
+};
+
+static const u16 rf_ramp_pwm_cband_8090[] = {
+ 345, /* max RF gain in 10th of dB */
+ 29, /* ramp_slope = 1dB of gain -> clock_ticks_per_db = clk_khz / ramp_slope -> RF_RAMP2 */
+ 1000, /* ramp_max = maximum X used on the ramp */
+ (35 << 10) | 772, /* RF_RAMP3, LNA 1 = 8dB */
+ (0 << 10) | 1000, /* RF_RAMP4, LNA 1 */
+ (58 << 10) | 496, /* RF_RAMP5, LNA 2 = 9.5dB */
+ (0 << 10) | 772, /* RF_RAMP6, LNA 2 */
+ (27 << 10) | 200, /* RF_RAMP7, LNA 3 = 10.5dB */
+ (0 << 10) | 496, /* RF_RAMP8, LNA 3 */
+ (40 << 10) | 0, /* GAIN_4_1, LNA 4 = 7dB */
+ (0 << 10) | 200, /* GAIN_4_2, LNA 4 */
+};
+
+static const u16 rf_ramp_pwm_uhf_7090[] = {
+ 407, /* max RF gain in 10th of dB */
+ 13, /* ramp_slope = 1dB of gain -> clock_ticks_per_db = clk_khz / ramp_slope -> RF_RAMP2 */
+ 529, /* ramp_max = maximum X used on the ramp */
+ (23 << 10) | 0, /* RF_RAMP3, LNA 1 = 14.7dB */
+ (0 << 10) | 176, /* RF_RAMP4, LNA 1 */
+ (63 << 10) | 400, /* RF_RAMP5, LNA 2 = 8dB */
+ (0 << 10) | 529, /* RF_RAMP6, LNA 2 */
+ (48 << 10) | 316, /* RF_RAMP7, LNA 3 = 6.8dB */
+ (0 << 10) | 400, /* RF_RAMP8, LNA 3 */
+ (29 << 10) | 176, /* GAIN_4_1, LNA 4 = 11.5dB */
+ (0 << 10) | 316, /* GAIN_4_2, LNA 4 */
+};
+
+static const u16 rf_ramp_pwm_uhf_8090[] = {
+ 388, /* max RF gain in 10th of dB */
+ 26, /* ramp_slope = 1dB of gain -> clock_ticks_per_db = clk_khz / ramp_slope -> RF_RAMP2 */
+ 1008, /* ramp_max = maximum X used on the ramp */
+ (11 << 10) | 0, /* RF_RAMP3, LNA 1 = 14.7dB */
+ (0 << 10) | 369, /* RF_RAMP4, LNA 1 */
+ (41 << 10) | 809, /* RF_RAMP5, LNA 2 = 8dB */
+ (0 << 10) | 1008, /* RF_RAMP6, LNA 2 */
+ (27 << 10) | 659, /* RF_RAMP7, LNA 3 = 6dB */
+ (0 << 10) | 809, /* RF_RAMP8, LNA 3 */
+ (14 << 10) | 369, /* GAIN_4_1, LNA 4 = 11.5dB */
+ (0 << 10) | 659, /* GAIN_4_2, LNA 4 */
+};
+
static const u16 rf_ramp_pwm_cband[] = {
0, /* max RF gain in 10th of dB */
0, /* ramp_slope = 1dB of gain -> clock_ticks_per_db = clk_khz / ramp_slope -> 0x2b */
@@ -326,6 +710,16 @@ static const u16 rf_ramp_uhf[] = {
0, 0, 127, /* CBAND : 0.0 dB */
};
+static const u16 rf_ramp_cband_broadmatching[] = /* for p1G only */
+{
+ 314, /* Calibrated at 200MHz order has been changed g4-g3-g2-g1 */
+ 84, 314, 127, /* LNA1 */
+ 80, 230, 255, /* LNA2 */
+ 80, 150, 127, /* LNA3 It was measured 12dB, do not lock if 120 */
+ 70, 70, 127, /* LNA4 */
+ 0, 0, 127, /* CBAND */
+};
+
static const u16 rf_ramp_cband[] = {
332, /* max RF gain in 10th of dB */
132, 252, 127, /* LNA1, dB */
@@ -380,8 +774,8 @@ static const u16 bb_ramp_pwm_normal[] = {
};
struct slope {
- int16_t range;
- int16_t slope;
+ s16 range;
+ s16 slope;
};
static u16 slopes_to_scale(const struct slope *slopes, u8 num, s16 val)
{
@@ -597,19 +991,39 @@ void dib0090_pwm_gain_reset(struct dvb_frontend *fe)
#endif
#ifdef CONFIG_BAND_CBAND
if (state->current_band == BAND_CBAND) {
- dib0090_set_rframp_pwm(state, rf_ramp_pwm_cband);
- dib0090_set_bbramp_pwm(state, bb_ramp_pwm_normal);
+ if (state->identity.in_soc) {
+ dib0090_set_bbramp_pwm(state, bb_ramp_pwm_normal_socs);
+ if (state->identity.version == SOC_8090_P1G_11R1 || state->identity.version == SOC_8090_P1G_21R1)
+ dib0090_set_rframp_pwm(state, rf_ramp_pwm_cband_8090);
+ else if (state->identity.version == SOC_7090_P1G_11R1 || state->identity.version == SOC_7090_P1G_21R1)
+ dib0090_set_rframp_pwm(state, rf_ramp_pwm_cband_7090);
+ } else {
+ dib0090_set_rframp_pwm(state, rf_ramp_pwm_cband);
+ dib0090_set_bbramp_pwm(state, bb_ramp_pwm_normal);
+ }
} else
#endif
#ifdef CONFIG_BAND_VHF
if (state->current_band == BAND_VHF) {
- dib0090_set_rframp_pwm(state, rf_ramp_pwm_vhf);
- dib0090_set_bbramp_pwm(state, bb_ramp_pwm_normal);
+ if (state->identity.in_soc) {
+ dib0090_set_bbramp_pwm(state, bb_ramp_pwm_normal_socs);
+ } else {
+ dib0090_set_rframp_pwm(state, rf_ramp_pwm_vhf);
+ dib0090_set_bbramp_pwm(state, bb_ramp_pwm_normal);
+ }
} else
#endif
{
- dib0090_set_rframp_pwm(state, rf_ramp_pwm_uhf);
- dib0090_set_bbramp_pwm(state, bb_ramp_pwm_normal);
+ if (state->identity.in_soc) {
+ if (state->identity.version == SOC_8090_P1G_11R1 || state->identity.version == SOC_8090_P1G_21R1)
+ dib0090_set_rframp_pwm(state, rf_ramp_pwm_uhf_8090);
+ else if (state->identity.version == SOC_7090_P1G_11R1 || state->identity.version == SOC_7090_P1G_21R1)
+ dib0090_set_rframp_pwm(state, rf_ramp_pwm_uhf_7090);
+ dib0090_set_bbramp_pwm(state, bb_ramp_pwm_normal_socs);
+ } else {
+ dib0090_set_rframp_pwm(state, rf_ramp_pwm_uhf);
+ dib0090_set_bbramp_pwm(state, bb_ramp_pwm_normal);
+ }
}
if (state->rf_ramp[0] != 0)
@@ -617,11 +1031,21 @@ void dib0090_pwm_gain_reset(struct dvb_frontend *fe)
else
dib0090_write_reg(state, 0x32, (0 << 11));
+ dib0090_write_reg(state, 0x04, 0x01);
dib0090_write_reg(state, 0x39, (1 << 10));
}
}
+
EXPORT_SYMBOL(dib0090_pwm_gain_reset);
+static u32 dib0090_get_slow_adc_val(struct dib0090_state *state)
+{
+ u16 adc_val = dib0090_read_reg(state, 0x1d);
+ if (state->identity.in_soc)
+ adc_val >>= 2;
+ return adc_val;
+}
+
int dib0090_gain_control(struct dvb_frontend *fe)
{
struct dib0090_state *state = fe->tuner_priv;
@@ -643,18 +1067,21 @@ int dib0090_gain_control(struct dvb_frontend *fe)
} else
#endif
#ifdef CONFIG_BAND_VHF
- if (state->current_band == BAND_VHF) {
+ if (state->current_band == BAND_VHF && !state->identity.p1g) {
dib0090_set_rframp(state, rf_ramp_vhf);
dib0090_set_bbramp(state, bb_ramp_boost);
} else
#endif
#ifdef CONFIG_BAND_CBAND
- if (state->current_band == BAND_CBAND) {
+ if (state->current_band == BAND_CBAND && !state->identity.p1g) {
dib0090_set_rframp(state, rf_ramp_cband);
dib0090_set_bbramp(state, bb_ramp_boost);
} else
#endif
- {
+ if ((state->current_band == BAND_CBAND || state->current_band == BAND_VHF) && state->identity.p1g) {
+ dib0090_set_rframp(state, rf_ramp_cband_broadmatching);
+ dib0090_set_bbramp(state, bb_ramp_boost);
+ } else {
dib0090_set_rframp(state, rf_ramp_uhf);
dib0090_set_bbramp(state, bb_ramp_boost);
}
@@ -669,17 +1096,25 @@ int dib0090_gain_control(struct dvb_frontend *fe)
*tune_state = CT_AGC_STEP_0;
} else if (!state->agc_freeze) {
- s16 wbd;
+ s16 wbd = 0, i, cnt;
int adc;
- wbd_val = dib0090_read_reg(state, 0x1d);
+ wbd_val = dib0090_get_slow_adc_val(state);
- /* read and calc the wbd power */
- wbd = dib0090_wbd_to_db(state, wbd_val);
+ if (*tune_state == CT_AGC_STEP_0)
+ cnt = 5;
+ else
+ cnt = 1;
+
+ for (i = 0; i < cnt; i++) {
+ wbd_val = dib0090_get_slow_adc_val(state);
+ wbd += dib0090_wbd_to_db(state, wbd_val);
+ }
+ wbd /= cnt;
wbd_error = state->wbd_target - wbd;
if (*tune_state == CT_AGC_STEP_0) {
- if (wbd_error < 0 && state->rf_gain_limit > 0) {
+ if (wbd_error < 0 && state->rf_gain_limit > 0 && !state->identity.p1g) {
#ifdef CONFIG_BAND_CBAND
/* in case of CBAND tune reduce first the lt_gain2 before adjusting the RF gain */
u8 ltg2 = (state->rf_lt_def >> 10) & 0x7;
@@ -700,39 +1135,39 @@ int dib0090_gain_control(struct dvb_frontend *fe)
adc_error = (s16) (((s32) ADC_TARGET) - adc);
#ifdef CONFIG_STANDARD_DAB
if (state->fe->dtv_property_cache.delivery_system == STANDARD_DAB)
- adc_error += 130;
+ adc_error -= 10;
#endif
#ifdef CONFIG_STANDARD_DVBT
if (state->fe->dtv_property_cache.delivery_system == STANDARD_DVBT &&
- (state->fe->dtv_property_cache.modulation == QAM_64 || state->fe->dtv_property_cache.modulation == QAM_16))
+ (state->fe->dtv_property_cache.modulation == QAM_64 || state->fe->dtv_property_cache.modulation == QAM_16))
adc_error += 60;
#endif
#ifdef CONFIG_SYS_ISDBT
if ((state->fe->dtv_property_cache.delivery_system == SYS_ISDBT) && (((state->fe->dtv_property_cache.layer[0].segment_count >
- 0)
- &&
- ((state->fe->dtv_property_cache.layer[0].modulation ==
- QAM_64)
- || (state->fe->dtv_property_cache.layer[0].
- modulation == QAM_16)))
- ||
- ((state->fe->dtv_property_cache.layer[1].segment_count >
- 0)
- &&
- ((state->fe->dtv_property_cache.layer[1].modulation ==
- QAM_64)
- || (state->fe->dtv_property_cache.layer[1].
- modulation == QAM_16)))
- ||
- ((state->fe->dtv_property_cache.layer[2].segment_count >
- 0)
- &&
- ((state->fe->dtv_property_cache.layer[2].modulation ==
- QAM_64)
- || (state->fe->dtv_property_cache.layer[2].
- modulation == QAM_16)))
- )
- )
+ 0)
+ &&
+ ((state->fe->dtv_property_cache.layer[0].modulation ==
+ QAM_64)
+ || (state->fe->dtv_property_cache.
+ layer[0].modulation == QAM_16)))
+ ||
+ ((state->fe->dtv_property_cache.layer[1].segment_count >
+ 0)
+ &&
+ ((state->fe->dtv_property_cache.layer[1].modulation ==
+ QAM_64)
+ || (state->fe->dtv_property_cache.
+ layer[1].modulation == QAM_16)))
+ ||
+ ((state->fe->dtv_property_cache.layer[2].segment_count >
+ 0)
+ &&
+ ((state->fe->dtv_property_cache.layer[2].modulation ==
+ QAM_64)
+ || (state->fe->dtv_property_cache.
+ layer[2].modulation == QAM_16)))
+ )
+ )
adc_error += 60;
#endif
@@ -760,9 +1195,9 @@ int dib0090_gain_control(struct dvb_frontend *fe)
}
#ifdef DEBUG_AGC
dprintk
- ("FE: %d, tune state %d, ADC = %3ddB (ADC err %3d) WBD %3ddB (WBD err %3d, WBD val SADC: %4d), RFGainLimit (TOP): %3d, signal: %3ddBm",
- (u32) fe->id, (u32) *tune_state, (u32) adc, (u32) adc_error, (u32) wbd, (u32) wbd_error, (u32) wbd_val,
- (u32) state->rf_gain_limit >> WBD_ALPHA, (s32) 200 + adc - (state->current_gain >> GAIN_ALPHA));
+ ("tune state %d, ADC = %3ddB (ADC err %3d) WBD %3ddB (WBD err %3d, WBD val SADC: %4d), RFGainLimit (TOP): %3d, signal: %3ddBm",
+ (u32) *tune_state, (u32) adc, (u32) adc_error, (u32) wbd, (u32) wbd_error, (u32) wbd_val,
+ (u32) state->rf_gain_limit >> WBD_ALPHA, (s32) 200 + adc - (state->current_gain >> GAIN_ALPHA));
#endif
}
@@ -771,6 +1206,7 @@ int dib0090_gain_control(struct dvb_frontend *fe)
dib0090_gain_apply(state, adc_error, wbd_error, apply_gain_immediatly);
return ret;
}
+
EXPORT_SYMBOL(dib0090_gain_control);
void dib0090_get_current_gain(struct dvb_frontend *fe, u16 * rf, u16 * bb, u16 * rf_gain_limit, u16 * rflt)
@@ -785,13 +1221,47 @@ void dib0090_get_current_gain(struct dvb_frontend *fe, u16 * rf, u16 * bb, u16 *
if (rflt)
*rflt = (state->rf_lt_def >> 10) & 0x7;
}
+
EXPORT_SYMBOL(dib0090_get_current_gain);
-u16 dib0090_get_wbd_offset(struct dvb_frontend *tuner)
+u16 dib0090_get_wbd_offset(struct dvb_frontend *fe)
{
- struct dib0090_state *st = tuner->tuner_priv;
- return st->wbd_offset;
+ struct dib0090_state *state = fe->tuner_priv;
+ u32 f_MHz = state->fe->dtv_property_cache.frequency / 1000000;
+ s32 current_temp = state->temperature;
+ s32 wbd_thot, wbd_tcold;
+ const struct dib0090_wbd_slope *wbd = state->current_wbd_table;
+
+ while (f_MHz > wbd->max_freq)
+ wbd++;
+
+ dprintk("using wbd-table-entry with max freq %d", wbd->max_freq);
+
+ if (current_temp < 0)
+ current_temp = 0;
+ if (current_temp > 128)
+ current_temp = 128;
+
+ state->wbdmux &= ~(7 << 13);
+ if (wbd->wbd_gain != 0)
+ state->wbdmux |= (wbd->wbd_gain << 13);
+ else
+ state->wbdmux |= (4 << 13);
+
+ dib0090_write_reg(state, 0x10, state->wbdmux);
+
+ wbd_thot = wbd->offset_hot - (((u32) wbd->slope_hot * f_MHz) >> 6);
+ wbd_tcold = wbd->offset_cold - (((u32) wbd->slope_cold * f_MHz) >> 6);
+
+ wbd_tcold += ((wbd_thot - wbd_tcold) * current_temp) >> 7;
+
+ state->wbd_target = dib0090_wbd_to_db(state, state->wbd_offset + wbd_tcold);
+ dprintk("wbd-target: %d dB", (u32) state->wbd_target);
+ dprintk("wbd offset applied is %d", wbd_tcold);
+
+ return state->wbd_offset + wbd_tcold;
}
+
EXPORT_SYMBOL(dib0090_get_wbd_offset);
static const u16 dib0090_defaults[] = {
@@ -801,7 +1271,7 @@ static const u16 dib0090_defaults[] = {
0x99a0,
0x6008,
0x0000,
- 0x8acb,
+ 0x8bcb,
0x0000,
0x0405,
0x0000,
@@ -829,8 +1299,6 @@ static const u16 dib0090_defaults[] = {
1, 0x39,
0x0000,
- 1, 0x1b,
- EN_IQADC | EN_BB | EN_BIAS | EN_DIGCLK | EN_PLL | EN_CRYSTAL,
2, 0x1e,
0x07FF,
0x0007,
@@ -844,50 +1312,125 @@ static const u16 dib0090_defaults[] = {
0
};
-static int dib0090_reset(struct dvb_frontend *fe)
-{
- struct dib0090_state *state = fe->tuner_priv;
- u16 l, r, *n;
+static const u16 dib0090_p1g_additionnal_defaults[] = {
+ 1, 0x05,
+ 0xabcd,
- dib0090_reset_digital(fe, state->config);
- state->revision = dib0090_identify(fe);
+ 1, 0x11,
+ 0x00b4,
- /* Revision definition */
- if (state->revision == 0xff)
- return -EINVAL;
-#ifdef EFUSE
- else if ((state->revision & 0x1f) >= 3) /* Update the efuse : Only available for KROSUS > P1C */
- dib0090_set_EFUSE(state);
-#endif
+ 1, 0x1c,
+ 0xfffd,
-#ifdef CONFIG_TUNER_DIB0090_P1B_SUPPORT
- if (!(state->revision & 0x1)) /* it is P1B - reset is already done */
- return 0;
-#endif
+ 1, 0x40,
+ 0x108,
+ 0
+};
+
+static void dib0090_set_default_config(struct dib0090_state *state, const u16 * n)
+{
+ u16 l, r;
- /* Upload the default values */
- n = (u16 *) dib0090_defaults;
l = pgm_read_word(n++);
while (l) {
r = pgm_read_word(n++);
do {
- /* DEBUG_TUNER */
- /* dprintk("%d, %d, %d", l, r, pgm_read_word(n)); */
dib0090_write_reg(state, r, pgm_read_word(n++));
r++;
} while (--l);
l = pgm_read_word(n++);
}
+}
+
+#define CAP_VALUE_MIN (u8) 9
+#define CAP_VALUE_MAX (u8) 40
+#define HR_MIN (u8) 25
+#define HR_MAX (u8) 40
+#define POLY_MIN (u8) 0
+#define POLY_MAX (u8) 8
+
+void dib0090_set_EFUSE(struct dib0090_state *state)
+{
+ u8 c, h, n;
+ u16 e2, e4;
+ u16 cal;
+
+ e2 = dib0090_read_reg(state, 0x26);
+ e4 = dib0090_read_reg(state, 0x28);
+
+ if ((state->identity.version == P1D_E_F) ||
+ (state->identity.version == P1G) || (e2 == 0xffff)) {
+
+ dib0090_write_reg(state, 0x22, 0x10);
+ cal = (dib0090_read_reg(state, 0x22) >> 6) & 0x3ff;
+
+ if ((cal < 670) || (cal == 1023))
+ cal = 850;
+ n = 165 - ((cal * 10)>>6) ;
+ e2 = e4 = (3<<12) | (34<<6) | (n);
+ }
+
+ if (e2 != e4)
+ e2 &= e4; /* Remove the redundancy */
+
+ if (e2 != 0xffff) {
+ c = e2 & 0x3f;
+ n = (e2 >> 12) & 0xf;
+ h = (e2 >> 6) & 0x3f;
+
+ if ((c >= CAP_VALUE_MAX) || (c <= CAP_VALUE_MIN))
+ c = 32;
+ if ((h >= HR_MAX) || (h <= HR_MIN))
+ h = 34;
+ if ((n >= POLY_MAX) || (n <= POLY_MIN))
+ n = 3;
+
+ dib0090_write_reg(state, 0x13, (h << 10)) ;
+ e2 = (n<<11) | ((h>>2)<<6) | (c);
+ dib0090_write_reg(state, 0x2, e2) ; /* Load the BB_2 */
+ }
+}
+
+static int dib0090_reset(struct dvb_frontend *fe)
+{
+ struct dib0090_state *state = fe->tuner_priv;
+
+ dib0090_reset_digital(fe, state->config);
+ if (dib0090_identify(fe) < 0)
+ return -EIO;
+
+#ifdef CONFIG_TUNER_DIB0090_P1B_SUPPORT
+ if (!(state->identity.version & 0x1)) /* it is P1B - reset is already done */
+ return 0;
+#endif
+
+ if (!state->identity.in_soc) {
+ if ((dib0090_read_reg(state, 0x1a) >> 5) & 0x2)
+ dib0090_write_reg(state, 0x1b, (EN_IQADC | EN_BB | EN_BIAS | EN_DIGCLK | EN_PLL | EN_CRYSTAL));
+ else
+ dib0090_write_reg(state, 0x1b, (EN_DIGCLK | EN_PLL | EN_CRYSTAL));
+ }
+
+ dib0090_set_default_config(state, dib0090_defaults);
+
+ if (state->identity.in_soc)
+ dib0090_write_reg(state, 0x18, 0x2910); /* charge pump current = 0 */
+
+ if (state->identity.p1g)
+ dib0090_set_default_config(state, dib0090_p1g_additionnal_defaults);
+
+ /* Update the efuse : Only available for KROSUS > P1C and SOC as well*/
+ if (((state->identity.version & 0x1f) >= P1D_E_F) || (state->identity.in_soc))
+ dib0090_set_EFUSE(state);
/* Congigure in function of the crystal */
if (state->config->io.clock_khz >= 24000)
- l = 1;
+ dib0090_write_reg(state, 0x14, 1);
else
- l = 2;
- dib0090_write_reg(state, 0x14, l);
+ dib0090_write_reg(state, 0x14, 2);
dprintk("Pll lock : %d", (dib0090_read_reg(state, 0x1a) >> 11) & 0x1);
- state->reset = 3; /* enable iq-offset-calibration and wbd-calibration when tuning next time */
+ state->calibrate = DC_CAL | WBD_CAL | TEMP_CAL; /* enable iq-offset-calibration and wbd-calibration when tuning next time */
return 0;
}
@@ -927,11 +1470,11 @@ static int dib0090_get_offset(struct dib0090_state *state, enum frontend_tune_st
}
struct dc_calibration {
- uint8_t addr;
- uint8_t offset;
- uint8_t pga:1;
- uint16_t bb1;
- uint8_t i:1;
+ u8 addr;
+ u8 offset;
+ u8 pga:1;
+ u16 bb1;
+ u8 i:1;
};
static const struct dc_calibration dc_table[] = {
@@ -944,6 +1487,17 @@ static const struct dc_calibration dc_table[] = {
{0},
};
+static const struct dc_calibration dc_p1g_table[] = {
+ /* Step1 BB gain1= 26 with boost 1, gain 2 = 0 */
+ /* addr ; trim reg offset ; pga ; CTRL_BB1 value ; i or q */
+ {0x06, 5, 1, (1 << 13) | (0 << 8) | (15 << 3), 1},
+ {0x07, 11, 1, (1 << 13) | (0 << 8) | (15 << 3), 0},
+ /* Step 2 BB gain 1 = 26 with boost = 1 & gain 2 = 29 */
+ {0x06, 0, 0, (1 << 13) | (29 << 8) | (15 << 3), 1},
+ {0x06, 10, 0, (1 << 13) | (29 << 8) | (15 << 3), 0},
+ {0},
+};
+
static void dib0090_set_trim(struct dib0090_state *state)
{
u16 *val;
@@ -962,41 +1516,45 @@ static void dib0090_set_trim(struct dib0090_state *state)
static int dib0090_dc_offset_calibration(struct dib0090_state *state, enum frontend_tune_state *tune_state)
{
int ret = 0;
+ u16 reg;
switch (*tune_state) {
-
case CT_TUNER_START:
- /* init */
- dprintk("Internal DC calibration");
-
- /* the LNA is off */
- dib0090_write_reg(state, 0x24, 0x02ed);
+ dprintk("Start DC offset calibration");
/* force vcm2 = 0.8V */
state->bb6 = 0;
state->bb7 = 0x040d;
+ /* the LNA AND LO are off */
+ reg = dib0090_read_reg(state, 0x24) & 0x0ffb; /* shutdown lna and lo */
+ dib0090_write_reg(state, 0x24, reg);
+
+ state->wbdmux = dib0090_read_reg(state, 0x10);
+ dib0090_write_reg(state, 0x10, (state->wbdmux & ~(0xff << 3)) | (0x7 << 3) | 0x3);
+ dib0090_write_reg(state, 0x23, dib0090_read_reg(state, 0x23) & ~(1 << 14));
+
state->dc = dc_table;
+ if (state->identity.p1g)
+ state->dc = dc_p1g_table;
*tune_state = CT_TUNER_STEP_0;
/* fall through */
case CT_TUNER_STEP_0:
+ dprintk("Sart/continue DC calibration for %s path", (state->dc->i == 1) ? "I" : "Q");
dib0090_write_reg(state, 0x01, state->dc->bb1);
dib0090_write_reg(state, 0x07, state->bb7 | (state->dc->i << 7));
state->step = 0;
-
state->min_adc_diff = 1023;
-
*tune_state = CT_TUNER_STEP_1;
ret = 50;
break;
case CT_TUNER_STEP_1:
dib0090_set_trim(state);
-
*tune_state = CT_TUNER_STEP_2;
break;
@@ -1007,7 +1565,13 @@ static int dib0090_dc_offset_calibration(struct dib0090_state *state, enum front
break;
case CT_TUNER_STEP_5: /* found an offset */
- dprintk("FE%d: IQC read=%d, current=%x", state->fe->id, (u32) state->adc_diff, state->step);
+ dprintk("adc_diff = %d, current step= %d", (u32) state->adc_diff, state->step);
+ if (state->step == 0 && state->adc_diff < 0) {
+ state->min_adc_diff = -1023;
+ dprintk("Change of sign of the minimum adc diff");
+ }
+
+ dprintk("adc_diff = %d, min_adc_diff = %d current_step = %d", state->adc_diff, state->min_adc_diff, state->step);
/* first turn for this frequency */
if (state->step == 0) {
@@ -1017,20 +1581,21 @@ static int dib0090_dc_offset_calibration(struct dib0090_state *state, enum front
state->step = 0x10;
}
- state->adc_diff = ABS(state->adc_diff);
-
- if (state->adc_diff < state->min_adc_diff && steps(state->step) < 15) { /* stop search when the delta to 0 is increasing */
+ /* Look for a change of Sign in the Adc_diff.min_adc_diff is used to STORE the setp N-1 */
+ if ((state->adc_diff & 0x8000) == (state->min_adc_diff & 0x8000) && steps(state->step) < 15) {
+ /* stop search when the delta the sign is changing and Steps =15 and Step=0 is force for continuance */
state->step++;
state->min_adc_diff = state->adc_diff;
*tune_state = CT_TUNER_STEP_1;
} else {
-
/* the minimum was what we have seen in the step before */
- state->step--;
- dib0090_set_trim(state);
+ if (ABS(state->adc_diff) > ABS(state->min_adc_diff)) {
+ dprintk("Since adc_diff N = %d > adc_diff step N-1 = %d, Come back one step", state->adc_diff, state->min_adc_diff);
+ state->step--;
+ }
- dprintk("FE%d: BB Offset Cal, BBreg=%hd,Offset=%hd,Value Set=%hd", state->fe->id, state->dc->addr, state->adc_diff,
- state->step);
+ dib0090_set_trim(state);
+ dprintk("BB Offset Cal, BBreg=%hd,Offset=%hd,Value Set=%hd", state->dc->addr, state->adc_diff, state->step);
state->dc++;
if (state->dc->addr == 0) /* done */
@@ -1045,7 +1610,7 @@ static int dib0090_dc_offset_calibration(struct dib0090_state *state, enum front
dib0090_write_reg(state, 0x07, state->bb7 & ~0x0008);
dib0090_write_reg(state, 0x1f, 0x7);
*tune_state = CT_TUNER_START; /* reset done -> real tuning can now begin */
- state->reset &= ~0x1;
+ state->calibrate &= ~DC_CAL;
default:
break;
}
@@ -1054,21 +1619,43 @@ static int dib0090_dc_offset_calibration(struct dib0090_state *state, enum front
static int dib0090_wbd_calibration(struct dib0090_state *state, enum frontend_tune_state *tune_state)
{
+ u8 wbd_gain;
+ const struct dib0090_wbd_slope *wbd = state->current_wbd_table;
+
switch (*tune_state) {
case CT_TUNER_START:
- /* WBD-mode=log, Bias=2, Gain=6, Testmode=1, en=1, WBDMUX=1 */
- dib0090_write_reg(state, 0x10, 0xdb09 | (1 << 10));
- dib0090_write_reg(state, 0x24, EN_UHF & 0x0fff);
+ while (state->current_rf / 1000 > wbd->max_freq)
+ wbd++;
+ if (wbd->wbd_gain != 0)
+ wbd_gain = wbd->wbd_gain;
+ else {
+ wbd_gain = 4;
+#if defined(CONFIG_BAND_LBAND) || defined(CONFIG_BAND_SBAND)
+ if ((state->current_band == BAND_LBAND) || (state->current_band == BAND_SBAND))
+ wbd_gain = 2;
+#endif
+ }
+
+ if (wbd_gain == state->wbd_calibration_gain) { /* the WBD calibration has already been done */
+ *tune_state = CT_TUNER_START;
+ state->calibrate &= ~WBD_CAL;
+ return 0;
+ }
+
+ dib0090_write_reg(state, 0x10, 0x1b81 | (1 << 10) | (wbd_gain << 13) | (1 << 3));
+ dib0090_write_reg(state, 0x24, ((EN_UHF & 0x0fff) | (1 << 1)));
*tune_state = CT_TUNER_STEP_0;
+ state->wbd_calibration_gain = wbd_gain;
return 90; /* wait for the WBDMUX to switch and for the ADC to sample */
+
case CT_TUNER_STEP_0:
- state->wbd_offset = dib0090_read_reg(state, 0x1d);
+ state->wbd_offset = dib0090_get_slow_adc_val(state);
dprintk("WBD calibration offset = %d", state->wbd_offset);
-
*tune_state = CT_TUNER_START; /* reset done -> real tuning can now begin */
- state->reset &= ~0x2;
+ state->calibrate &= ~WBD_CAL;
break;
+
default:
break;
}
@@ -1092,6 +1679,15 @@ static void dib0090_set_bandwidth(struct dib0090_state *state)
state->bb_1_def |= tmp;
dib0090_write_reg(state, 0x01, state->bb_1_def); /* be sure that we have the right bb-filter */
+
+ dib0090_write_reg(state, 0x03, 0x6008); /* = 0x6008 : vcm3_trim = 1 ; filter2_gm1_trim = 8 ; filter2_cutoff_freq = 0 */
+ dib0090_write_reg(state, 0x04, 0x1); /* 0 = 1KHz ; 1 = 50Hz ; 2 = 150Hz ; 3 = 50KHz ; 4 = servo fast */
+ if (state->identity.in_soc) {
+ dib0090_write_reg(state, 0x05, 0x9bcf); /* attenuator_ibias_tri = 2 ; input_stage_ibias_tr = 1 ; nc = 11 ; ext_gm_trim = 1 ; obuf_ibias_trim = 4 ; filter13_gm2_ibias_t = 15 */
+ } else {
+ dib0090_write_reg(state, 0x02, (5 << 11) | (8 << 6) | (22 & 0x3f)); /* 22 = cap_value */
+ dib0090_write_reg(state, 0x05, 0xabcd); /* = 0xabcd : attenuator_ibias_tri = 2 ; input_stage_ibias_tr = 2 ; nc = 11 ; ext_gm_trim = 1 ; obuf_ibias_trim = 4 ; filter13_gm2_ibias_t = 13 */
+ }
}
static const struct dib0090_pll dib0090_pll_table[] = {
@@ -1180,6 +1776,255 @@ static const struct dib0090_tuning dib0090_tuning_table[] = {
#endif
};
+static const struct dib0090_tuning dib0090_p1g_tuning_table[] = {
+#ifdef CONFIG_BAND_CBAND
+ {170000, 4, 1, 0x820f, 0x300, 0x2d22, 0x82cb, EN_CAB},
+#endif
+#ifdef CONFIG_BAND_VHF
+ {184000, 1, 1, 15, 0x300, 0x4d12, 0xb94e, EN_VHF},
+ {227000, 1, 3, 15, 0x300, 0x4d12, 0xb94e, EN_VHF},
+ {380000, 1, 7, 15, 0x300, 0x4d12, 0xb94e, EN_VHF},
+#endif
+#ifdef CONFIG_BAND_UHF
+ {510000, 2, 0, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
+ {540000, 2, 1, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
+ {600000, 2, 3, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
+ {630000, 2, 4, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
+ {680000, 2, 5, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
+ {720000, 2, 6, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
+ {900000, 2, 7, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
+#endif
+#ifdef CONFIG_BAND_LBAND
+ {1500000, 4, 0, 20, 0x300, 0x1912, 0x82c9, EN_LBD},
+ {1600000, 4, 1, 20, 0x300, 0x1912, 0x82c9, EN_LBD},
+ {1800000, 4, 3, 20, 0x300, 0x1912, 0x82c9, EN_LBD},
+#endif
+#ifdef CONFIG_BAND_SBAND
+ {2300000, 1, 4, 20, 0x300, 0x2d2A, 0x82c7, EN_SBD},
+ {2900000, 1, 7, 20, 0x280, 0x2deb, 0x8347, EN_SBD},
+#endif
+};
+
+static const struct dib0090_pll dib0090_p1g_pll_table[] = {
+#ifdef CONFIG_BAND_CBAND
+ {57000, 0, 11, 48, 6},
+ {70000, 1, 11, 48, 6},
+ {86000, 0, 10, 32, 4},
+ {105000, 1, 10, 32, 4},
+ {115000, 0, 9, 24, 6},
+ {140000, 1, 9, 24, 6},
+ {170000, 0, 8, 16, 4},
+#endif
+#ifdef CONFIG_BAND_VHF
+ {200000, 1, 8, 16, 4},
+ {230000, 0, 7, 12, 6},
+ {280000, 1, 7, 12, 6},
+ {340000, 0, 6, 8, 4},
+ {380000, 1, 6, 8, 4},
+ {455000, 0, 5, 6, 6},
+#endif
+#ifdef CONFIG_BAND_UHF
+ {580000, 1, 5, 6, 6},
+ {680000, 0, 4, 4, 4},
+ {860000, 1, 4, 4, 4},
+#endif
+#ifdef CONFIG_BAND_LBAND
+ {1800000, 1, 2, 2, 4},
+#endif
+#ifdef CONFIG_BAND_SBAND
+ {2900000, 0, 1, 1, 6},
+#endif
+};
+
+static const struct dib0090_tuning dib0090_p1g_tuning_table_fm_vhf_on_cband[] = {
+#ifdef CONFIG_BAND_CBAND
+ {184000, 4, 3, 0x4187, 0x2c0, 0x2d22, 0x81cb, EN_CAB},
+ {227000, 4, 3, 0x4187, 0x2c0, 0x2d22, 0x81cb, EN_CAB},
+ {380000, 4, 3, 0x4187, 0x2c0, 0x2d22, 0x81cb, EN_CAB},
+#endif
+#ifdef CONFIG_BAND_UHF
+ {520000, 2, 0, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
+ {550000, 2, 2, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
+ {650000, 2, 3, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
+ {750000, 2, 5, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
+ {850000, 2, 6, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
+ {900000, 2, 7, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
+#endif
+#ifdef CONFIG_BAND_LBAND
+ {1500000, 4, 0, 20, 0x300, 0x1912, 0x82c9, EN_LBD},
+ {1600000, 4, 1, 20, 0x300, 0x1912, 0x82c9, EN_LBD},
+ {1800000, 4, 3, 20, 0x300, 0x1912, 0x82c9, EN_LBD},
+#endif
+#ifdef CONFIG_BAND_SBAND
+ {2300000, 1, 4, 20, 0x300, 0x2d2A, 0x82c7, EN_SBD},
+ {2900000, 1, 7, 20, 0x280, 0x2deb, 0x8347, EN_SBD},
+#endif
+};
+
+static const struct dib0090_tuning dib0090_tuning_table_cband_7090[] = {
+#ifdef CONFIG_BAND_CBAND
+ {300000, 4, 3, 0x018F, 0x2c0, 0x2d22, 0xb9ce, EN_CAB},
+ {380000, 4, 10, 0x018F, 0x2c0, 0x2d22, 0xb9ce, EN_CAB},
+ {570000, 4, 10, 0x8190, 0x2c0, 0x2d22, 0xb9ce, EN_CAB},
+ {858000, 4, 5, 0x8190, 0x2c0, 0x2d22, 0xb9ce, EN_CAB},
+#endif
+};
+
+static int dib0090_captrim_search(struct dib0090_state *state, enum frontend_tune_state *tune_state)
+{
+ int ret = 0;
+ u16 lo4 = 0xe900;
+
+ s16 adc_target;
+ u16 adc;
+ s8 step_sign;
+ u8 force_soft_search = 0;
+
+ if (state->identity.version == SOC_8090_P1G_11R1 || state->identity.version == SOC_8090_P1G_21R1)
+ force_soft_search = 1;
+
+ if (*tune_state == CT_TUNER_START) {
+ dprintk("Start Captrim search : %s", (force_soft_search == 1) ? "FORCE SOFT SEARCH" : "AUTO");
+ dib0090_write_reg(state, 0x10, 0x2B1);
+ dib0090_write_reg(state, 0x1e, 0x0032);
+
+ if (!state->tuner_is_tuned) {
+ /* prepare a complete captrim */
+ if (!state->identity.p1g || force_soft_search)
+ state->step = state->captrim = state->fcaptrim = 64;
+
+ state->current_rf = state->rf_request;
+ } else { /* we are already tuned to this frequency - the configuration is correct */
+ if (!state->identity.p1g || force_soft_search) {
+ /* do a minimal captrim even if the frequency has not changed */
+ state->step = 4;
+ state->captrim = state->fcaptrim = dib0090_read_reg(state, 0x18) & 0x7f;
+ }
+ }
+ state->adc_diff = 3000;
+ *tune_state = CT_TUNER_STEP_0;
+
+ } else if (*tune_state == CT_TUNER_STEP_0) {
+ if (state->identity.p1g && !force_soft_search) {
+ u8 ratio = 31;
+
+ dib0090_write_reg(state, 0x40, (3 << 7) | (ratio << 2) | (1 << 1) | 1);
+ dib0090_read_reg(state, 0x40);
+ ret = 50;
+ } else {
+ state->step /= 2;
+ dib0090_write_reg(state, 0x18, lo4 | state->captrim);
+
+ if (state->identity.in_soc)
+ ret = 25;
+ }
+ *tune_state = CT_TUNER_STEP_1;
+
+ } else if (*tune_state == CT_TUNER_STEP_1) {
+ if (state->identity.p1g && !force_soft_search) {
+ dib0090_write_reg(state, 0x40, 0x18c | (0 << 1) | 0);
+ dib0090_read_reg(state, 0x40);
+
+ state->fcaptrim = dib0090_read_reg(state, 0x18) & 0x7F;
+ dprintk("***Final Captrim= 0x%x", state->fcaptrim);
+ *tune_state = CT_TUNER_STEP_3;
+
+ } else {
+ /* MERGE for all krosus before P1G */
+ adc = dib0090_get_slow_adc_val(state);
+ dprintk("CAPTRIM=%d; ADC = %d (ADC) & %dmV", (u32) state->captrim, (u32) adc, (u32) (adc) * (u32) 1800 / (u32) 1024);
+
+ if (state->rest == 0 || state->identity.in_soc) { /* Just for 8090P SOCS where auto captrim HW bug : TO CHECK IN ACI for SOCS !!! if 400 for 8090p SOC => tune issue !!! */
+ adc_target = 200;
+ } else
+ adc_target = 400;
+
+ if (adc >= adc_target) {
+ adc -= adc_target;
+ step_sign = -1;
+ } else {
+ adc = adc_target - adc;
+ step_sign = 1;
+ }
+
+ if (adc < state->adc_diff) {
+ dprintk("CAPTRIM=%d is closer to target (%d/%d)", (u32) state->captrim, (u32) adc, (u32) state->adc_diff);
+ state->adc_diff = adc;
+ state->fcaptrim = state->captrim;
+ }
+
+ state->captrim += step_sign * state->step;
+ if (state->step >= 1)
+ *tune_state = CT_TUNER_STEP_0;
+ else
+ *tune_state = CT_TUNER_STEP_2;
+
+ ret = 25;
+ }
+ } else if (*tune_state == CT_TUNER_STEP_2) { /* this step is only used by krosus < P1G */
+ /*write the final cptrim config */
+ dib0090_write_reg(state, 0x18, lo4 | state->fcaptrim);
+
+ *tune_state = CT_TUNER_STEP_3;
+
+ } else if (*tune_state == CT_TUNER_STEP_3) {
+ state->calibrate &= ~CAPTRIM_CAL;
+ *tune_state = CT_TUNER_STEP_0;
+ }
+
+ return ret;
+}
+
+static int dib0090_get_temperature(struct dib0090_state *state, enum frontend_tune_state *tune_state)
+{
+ int ret = 15;
+ s16 val;
+
+ switch (*tune_state) {
+ case CT_TUNER_START:
+ state->wbdmux = dib0090_read_reg(state, 0x10);
+ dib0090_write_reg(state, 0x10, (state->wbdmux & ~(0xff << 3)) | (0x8 << 3));
+
+ state->bias = dib0090_read_reg(state, 0x13);
+ dib0090_write_reg(state, 0x13, state->bias | (0x3 << 8));
+
+ *tune_state = CT_TUNER_STEP_0;
+ /* wait for the WBDMUX to switch and for the ADC to sample */
+ break;
+
+ case CT_TUNER_STEP_0:
+ state->adc_diff = dib0090_get_slow_adc_val(state);
+ dib0090_write_reg(state, 0x13, (state->bias & ~(0x3 << 8)) | (0x2 << 8));
+ *tune_state = CT_TUNER_STEP_1;
+ break;
+
+ case CT_TUNER_STEP_1:
+ val = dib0090_get_slow_adc_val(state);
+ state->temperature = ((s16) ((val - state->adc_diff) * 180) >> 8) + 55;
+
+ dprintk("temperature: %d C", state->temperature - 30);
+
+ *tune_state = CT_TUNER_STEP_2;
+ break;
+
+ case CT_TUNER_STEP_2:
+ dib0090_write_reg(state, 0x13, state->bias);
+ dib0090_write_reg(state, 0x10, state->wbdmux); /* write back original WBDMUX */
+
+ *tune_state = CT_TUNER_START;
+ state->calibrate &= ~TEMP_CAL;
+ if (state->config->analog_output == 0)
+ dib0090_write_reg(state, 0x23, dib0090_read_reg(state, 0x23) | (1 << 14));
+
+ break;
+
+ default:
+ ret = 0;
+ break;
+ }
+ return ret;
+}
+
#define WBD 0x781 /* 1 1 1 1 0000 0 0 1 */
static int dib0090_tune(struct dvb_frontend *fe)
{
@@ -1188,87 +2033,131 @@ static int dib0090_tune(struct dvb_frontend *fe)
const struct dib0090_pll *pll = state->current_pll_table_index;
enum frontend_tune_state *tune_state = &state->tune_state;
- u32 rf;
- u16 lo4 = 0xe900, lo5, lo6, Den;
+ u16 lo5, lo6, Den, tmp;
u32 FBDiv, Rest, FREF, VCOF_kHz = 0;
- u16 tmp, adc;
- int8_t step_sign;
int ret = 10; /* 1ms is the default delay most of the time */
u8 c, i;
- state->current_band = (u8) BAND_OF_FREQUENCY(fe->dtv_property_cache.frequency / 1000);
- rf = fe->dtv_property_cache.frequency / 1000 + (state->current_band ==
- BAND_UHF ? state->config->freq_offset_khz_uhf : state->config->freq_offset_khz_vhf);
- /* in any case we first need to do a reset if needed */
- if (state->reset & 0x1)
- return dib0090_dc_offset_calibration(state, tune_state);
- else if (state->reset & 0x2)
- return dib0090_wbd_calibration(state, tune_state);
-
- /************************* VCO ***************************/
+ /************************* VCO ***************************/
/* Default values for FG */
/* from these are needed : */
/* Cp,HFdiv,VCOband,SD,Num,Den,FB and REFDiv */
-#ifdef CONFIG_SYS_ISDBT
- if (state->fe->dtv_property_cache.delivery_system == SYS_ISDBT && state->fe->dtv_property_cache.isdbt_sb_mode == 1)
- rf += 850;
-#endif
+ /* in any case we first need to do a calibration if needed */
+ if (*tune_state == CT_TUNER_START) {
+ /* deactivate DataTX before some calibrations */
+ if (state->calibrate & (DC_CAL | TEMP_CAL | WBD_CAL))
+ dib0090_write_reg(state, 0x23, dib0090_read_reg(state, 0x23) & ~(1 << 14));
+ else
+ /* Activate DataTX in case a calibration has been done before */
+ if (state->config->analog_output == 0)
+ dib0090_write_reg(state, 0x23, dib0090_read_reg(state, 0x23) | (1 << 14));
+ }
- if (state->current_rf != rf) {
- state->tuner_is_tuned = 0;
+ if (state->calibrate & DC_CAL)
+ return dib0090_dc_offset_calibration(state, tune_state);
+ else if (state->calibrate & WBD_CAL) {
+ if (state->current_rf == 0)
+ state->current_rf = state->fe->dtv_property_cache.frequency / 1000;
+ return dib0090_wbd_calibration(state, tune_state);
+ } else if (state->calibrate & TEMP_CAL)
+ return dib0090_get_temperature(state, tune_state);
+ else if (state->calibrate & CAPTRIM_CAL)
+ return dib0090_captrim_search(state, tune_state);
- tune = dib0090_tuning_table;
+ if (*tune_state == CT_TUNER_START) {
+ /* if soc and AGC pwm control, disengage mux to be able to R/W access to 0x01 register to set the right filter (cutoff_freq_select) during the tune sequence, otherwise, SOC SERPAR error when accessing to 0x01 */
+ if (state->config->use_pwm_agc && state->identity.in_soc) {
+ tmp = dib0090_read_reg(state, 0x39);
+ if ((tmp >> 10) & 0x1)
+ dib0090_write_reg(state, 0x39, tmp & ~(1 << 10));
+ }
- tmp = (state->revision >> 5) & 0x7;
- if (tmp == 0x4 || tmp == 0x7) {
- /* CBAND tuner version for VHF */
- if (state->current_band == BAND_FM || state->current_band == BAND_VHF) {
- /* Force CBAND */
- state->current_band = BAND_CBAND;
- tune = dib0090_tuning_table_fm_vhf_on_cband;
+ state->current_band = (u8) BAND_OF_FREQUENCY(state->fe->dtv_property_cache.frequency / 1000);
+ state->rf_request =
+ state->fe->dtv_property_cache.frequency / 1000 + (state->current_band ==
+ BAND_UHF ? state->config->freq_offset_khz_uhf : state->config->
+ freq_offset_khz_vhf);
+
+ /* in ISDB-T 1seg we shift tuning frequency */
+ if ((state->fe->dtv_property_cache.delivery_system == SYS_ISDBT && state->fe->dtv_property_cache.isdbt_sb_mode == 1
+ && state->fe->dtv_property_cache.isdbt_partial_reception == 0)) {
+ const struct dib0090_low_if_offset_table *LUT_offset = state->config->low_if;
+ u8 found_offset = 0;
+ u32 margin_khz = 100;
+
+ if (LUT_offset != NULL) {
+ while (LUT_offset->RF_freq != 0xffff) {
+ if (((state->rf_request > (LUT_offset->RF_freq - margin_khz))
+ && (state->rf_request < (LUT_offset->RF_freq + margin_khz)))
+ && LUT_offset->std == state->fe->dtv_property_cache.delivery_system) {
+ state->rf_request += LUT_offset->offset_khz;
+ found_offset = 1;
+ break;
+ }
+ LUT_offset++;
+ }
}
+
+ if (found_offset == 0)
+ state->rf_request += 400;
}
+ if (state->current_rf != state->rf_request || (state->current_standard != state->fe->dtv_property_cache.delivery_system)) {
+ state->tuner_is_tuned = 0;
+ state->current_rf = 0;
+ state->current_standard = 0;
- pll = dib0090_pll_table;
- /* Look for the interval */
- while (rf > tune->max_freq)
- tune++;
- while (rf > pll->max_freq)
- pll++;
- state->current_tune_table_index = tune;
- state->current_pll_table_index = pll;
- }
+ tune = dib0090_tuning_table;
+ if (state->identity.p1g)
+ tune = dib0090_p1g_tuning_table;
- if (*tune_state == CT_TUNER_START) {
+ tmp = (state->identity.version >> 5) & 0x7;
- if (state->tuner_is_tuned == 0)
- state->current_rf = 0;
+ if (state->identity.in_soc) {
+ if (state->config->force_cband_input) { /* Use the CBAND input for all band */
+ if (state->current_band & BAND_CBAND || state->current_band & BAND_FM || state->current_band & BAND_VHF
+ || state->current_band & BAND_UHF) {
+ state->current_band = BAND_CBAND;
+ tune = dib0090_tuning_table_cband_7090;
+ }
+ } else { /* Use the CBAND input for all band under UHF */
+ if (state->current_band & BAND_CBAND || state->current_band & BAND_FM || state->current_band & BAND_VHF) {
+ state->current_band = BAND_CBAND;
+ tune = dib0090_tuning_table_cband_7090;
+ }
+ }
+ } else
+ if (tmp == 0x4 || tmp == 0x7) {
+ /* CBAND tuner version for VHF */
+ if (state->current_band == BAND_FM || state->current_band == BAND_CBAND || state->current_band == BAND_VHF) {
+ state->current_band = BAND_CBAND; /* Force CBAND */
+
+ tune = dib0090_tuning_table_fm_vhf_on_cband;
+ if (state->identity.p1g)
+ tune = dib0090_p1g_tuning_table_fm_vhf_on_cband;
+ }
+ }
- if (state->current_rf != rf) {
+ pll = dib0090_pll_table;
+ if (state->identity.p1g)
+ pll = dib0090_p1g_pll_table;
- dib0090_write_reg(state, 0x0b, 0xb800 | (tune->switch_trim));
+ /* Look for the interval */
+ while (state->rf_request > tune->max_freq)
+ tune++;
+ while (state->rf_request > pll->max_freq)
+ pll++;
- /* external loop filter, otherwise:
- * lo5 = (0 << 15) | (0 << 12) | (0 << 11) | (3 << 9) | (4 << 6) | (3 << 4) | 4;
- * lo6 = 0x0e34 */
- if (pll->vco_band)
- lo5 = 0x049e;
- else if (state->config->analog_output)
- lo5 = 0x041d;
- else
- lo5 = 0x041c;
-
- lo5 |= (pll->hfdiv_code << 11) | (pll->vco_band << 7); /* bit 15 is the split to the slave, we do not do it here */
+ state->current_tune_table_index = tune;
+ state->current_pll_table_index = pll;
- if (!state->config->io.pll_int_loop_filt)
- lo6 = 0xff28;
- else
- lo6 = (state->config->io.pll_int_loop_filt << 3);
+ dib0090_write_reg(state, 0x0b, 0xb800 | (tune->switch_trim));
- VCOF_kHz = (pll->hfdiv * rf) * 2;
+ VCOF_kHz = (pll->hfdiv * state->rf_request) * 2;
FREF = state->config->io.clock_khz;
+ if (state->config->fref_clock_ratio != 0)
+ FREF /= state->config->fref_clock_ratio;
FBDiv = (VCOF_kHz / pll->topresc / FREF);
Rest = (VCOF_kHz / pll->topresc) - FBDiv * FREF;
@@ -1283,144 +2172,132 @@ static int dib0090_tune(struct dvb_frontend *fe)
} else if (Rest > (FREF - 2 * LPF))
Rest = FREF - 2 * LPF;
Rest = (Rest * 6528) / (FREF / 10);
+ state->rest = Rest;
- Den = 1;
+ /* external loop filter, otherwise:
+ * lo5 = (0 << 15) | (0 << 12) | (0 << 11) | (3 << 9) | (4 << 6) | (3 << 4) | 4;
+ * lo6 = 0x0e34 */
+
+ if (Rest == 0) {
+ if (pll->vco_band)
+ lo5 = 0x049f;
+ else
+ lo5 = 0x041f;
+ } else {
+ if (pll->vco_band)
+ lo5 = 0x049e;
+ else if (state->config->analog_output)
+ lo5 = 0x041d;
+ else
+ lo5 = 0x041c;
+ }
+
+ if (state->identity.p1g) { /* Bias is done automatically in P1G */
+ if (state->identity.in_soc) {
+ if (state->identity.version == SOC_8090_P1G_11R1)
+ lo5 = 0x46f;
+ else
+ lo5 = 0x42f;
+ } else
+ lo5 = 0x42c;
+ }
+
+ lo5 |= (pll->hfdiv_code << 11) | (pll->vco_band << 7); /* bit 15 is the split to the slave, we do not do it here */
- dprintk(" ***** ******* Rest value = %d", Rest);
+ if (!state->config->io.pll_int_loop_filt) {
+ if (state->identity.in_soc)
+ lo6 = 0xff98;
+ else if (state->identity.p1g || (Rest == 0))
+ lo6 = 0xfff8;
+ else
+ lo6 = 0xff28;
+ } else
+ lo6 = (state->config->io.pll_int_loop_filt << 3);
+
+ Den = 1;
if (Rest > 0) {
if (state->config->analog_output)
lo6 |= (1 << 2) | 2;
- else
- lo6 |= (1 << 2) | 1;
+ else {
+ if (state->identity.in_soc)
+ lo6 |= (1 << 2) | 2;
+ else
+ lo6 |= (1 << 2) | 2;
+ }
Den = 255;
}
-#ifdef CONFIG_BAND_SBAND
- if (state->current_band == BAND_SBAND)
- lo6 &= 0xfffb;
-#endif
-
dib0090_write_reg(state, 0x15, (u16) FBDiv);
-
- dib0090_write_reg(state, 0x16, (Den << 8) | 1);
-
+ if (state->config->fref_clock_ratio != 0)
+ dib0090_write_reg(state, 0x16, (Den << 8) | state->config->fref_clock_ratio);
+ else
+ dib0090_write_reg(state, 0x16, (Den << 8) | 1);
dib0090_write_reg(state, 0x17, (u16) Rest);
-
dib0090_write_reg(state, 0x19, lo5);
-
dib0090_write_reg(state, 0x1c, lo6);
lo6 = tune->tuner_enable;
if (state->config->analog_output)
lo6 = (lo6 & 0xff9f) | 0x2;
- dib0090_write_reg(state, 0x24, lo6 | EN_LO
-#ifdef CONFIG_DIB0090_USE_PWM_AGC
- | state->config->use_pwm_agc * EN_CRYSTAL
-#endif
- );
-
- state->current_rf = rf;
-
- /* prepare a complete captrim */
- state->step = state->captrim = state->fcaptrim = 64;
-
- } else { /* we are already tuned to this frequency - the configuration is correct */
+ dib0090_write_reg(state, 0x24, lo6 | EN_LO | state->config->use_pwm_agc * EN_CRYSTAL);
- /* do a minimal captrim even if the frequency has not changed */
- state->step = 4;
- state->captrim = state->fcaptrim = dib0090_read_reg(state, 0x18) & 0x7f;
}
- state->adc_diff = 3000;
-
- dib0090_write_reg(state, 0x10, 0x2B1);
- dib0090_write_reg(state, 0x1e, 0x0032);
+ state->current_rf = state->rf_request;
+ state->current_standard = state->fe->dtv_property_cache.delivery_system;
ret = 20;
- *tune_state = CT_TUNER_STEP_1;
- } else if (*tune_state == CT_TUNER_STEP_0) {
- /* nothing */
- } else if (*tune_state == CT_TUNER_STEP_1) {
- state->step /= 2;
- dib0090_write_reg(state, 0x18, lo4 | state->captrim);
- *tune_state = CT_TUNER_STEP_2;
- } else if (*tune_state == CT_TUNER_STEP_2) {
+ state->calibrate = CAPTRIM_CAL; /* captrim serach now */
+ }
- adc = dib0090_read_reg(state, 0x1d);
- dprintk("FE %d CAPTRIM=%d; ADC = %d (ADC) & %dmV", (u32) fe->id, (u32) state->captrim, (u32) adc,
- (u32) (adc) * (u32) 1800 / (u32) 1024);
+ else if (*tune_state == CT_TUNER_STEP_0) { /* Warning : because of captrim cal, if you change this step, change it also in _cal.c file because it is the step following captrim cal state machine */
+ const struct dib0090_wbd_slope *wbd = state->current_wbd_table;
- if (adc >= 400) {
- adc -= 400;
- step_sign = -1;
- } else {
- adc = 400 - adc;
- step_sign = 1;
- }
+ while (state->current_rf / 1000 > wbd->max_freq)
+ wbd++;
- if (adc < state->adc_diff) {
- dprintk("FE %d CAPTRIM=%d is closer to target (%d/%d)", (u32) fe->id, (u32) state->captrim, (u32) adc, (u32) state->adc_diff);
- state->adc_diff = adc;
- state->fcaptrim = state->captrim;
-
- }
+ dib0090_write_reg(state, 0x1e, 0x07ff);
+ dprintk("Final Captrim: %d", (u32) state->fcaptrim);
+ dprintk("HFDIV code: %d", (u32) pll->hfdiv_code);
+ dprintk("VCO = %d", (u32) pll->vco_band);
+ dprintk("VCOF in kHz: %d ((%d*%d) << 1))", (u32) ((pll->hfdiv * state->rf_request) * 2), (u32) pll->hfdiv, (u32) state->rf_request);
+ dprintk("REFDIV: %d, FREF: %d", (u32) 1, (u32) state->config->io.clock_khz);
+ dprintk("FBDIV: %d, Rest: %d", (u32) dib0090_read_reg(state, 0x15), (u32) dib0090_read_reg(state, 0x17));
+ dprintk("Num: %d, Den: %d, SD: %d", (u32) dib0090_read_reg(state, 0x17), (u32) (dib0090_read_reg(state, 0x16) >> 8),
+ (u32) dib0090_read_reg(state, 0x1c) & 0x3);
- state->captrim += step_sign * state->step;
- if (state->step >= 1)
- *tune_state = CT_TUNER_STEP_1;
- else
- *tune_state = CT_TUNER_STEP_3;
+#define WBD 0x781 /* 1 1 1 1 0000 0 0 1 */
+ c = 4;
+ i = 3;
- ret = 15;
- } else if (*tune_state == CT_TUNER_STEP_3) {
- /*write the final cptrim config */
- dib0090_write_reg(state, 0x18, lo4 | state->fcaptrim);
+ if (wbd->wbd_gain != 0)
+ c = wbd->wbd_gain;
-#ifdef CONFIG_TUNER_DIB0090_CAPTRIM_MEMORY
- state->memory[state->memory_index].cap = state->fcaptrim;
-#endif
+ state->wbdmux = (c << 13) | (i << 11) | (WBD | (state->config->use_pwm_agc << 1));
+ dib0090_write_reg(state, 0x10, state->wbdmux);
- *tune_state = CT_TUNER_STEP_4;
- } else if (*tune_state == CT_TUNER_STEP_4) {
- dib0090_write_reg(state, 0x1e, 0x07ff);
-
- dprintk("FE %d Final Captrim: %d", (u32) fe->id, (u32) state->fcaptrim);
- dprintk("FE %d HFDIV code: %d", (u32) fe->id, (u32) pll->hfdiv_code);
- dprintk("FE %d VCO = %d", (u32) fe->id, (u32) pll->vco_band);
- dprintk("FE %d VCOF in kHz: %d ((%d*%d) << 1))", (u32) fe->id, (u32) ((pll->hfdiv * rf) * 2), (u32) pll->hfdiv, (u32) rf);
- dprintk("FE %d REFDIV: %d, FREF: %d", (u32) fe->id, (u32) 1, (u32) state->config->io.clock_khz);
- dprintk("FE %d FBDIV: %d, Rest: %d", (u32) fe->id, (u32) dib0090_read_reg(state, 0x15), (u32) dib0090_read_reg(state, 0x17));
- dprintk("FE %d Num: %d, Den: %d, SD: %d", (u32) fe->id, (u32) dib0090_read_reg(state, 0x17),
- (u32) (dib0090_read_reg(state, 0x16) >> 8), (u32) dib0090_read_reg(state, 0x1c) & 0x3);
+ if ((tune->tuner_enable == EN_CAB) && state->identity.p1g) {
+ dprintk("P1G : The cable band is selected and lna_tune = %d", tune->lna_tune);
+ dib0090_write_reg(state, 0x09, tune->lna_bias);
+ dib0090_write_reg(state, 0x0b, 0xb800 | (tune->lna_tune << 6) | (tune->switch_trim));
+ } else
+ dib0090_write_reg(state, 0x09, (tune->lna_tune << 5) | tune->lna_bias);
- c = 4;
- i = 3;
-#if defined(CONFIG_BAND_LBAND) || defined(CONFIG_BAND_SBAND)
- if ((state->current_band == BAND_LBAND) || (state->current_band == BAND_SBAND)) {
- c = 2;
- i = 2;
- }
-#endif
- dib0090_write_reg(state, 0x10, (c << 13) | (i << 11) | (WBD
-#ifdef CONFIG_DIB0090_USE_PWM_AGC
- | (state->config->use_pwm_agc << 1)
-#endif
- ));
- dib0090_write_reg(state, 0x09, (tune->lna_tune << 5) | (tune->lna_bias << 0));
dib0090_write_reg(state, 0x0c, tune->v2i);
dib0090_write_reg(state, 0x0d, tune->mix);
dib0090_write_reg(state, 0x0e, tune->load);
+ *tune_state = CT_TUNER_STEP_1;
- *tune_state = CT_TUNER_STEP_5;
- } else if (*tune_state == CT_TUNER_STEP_5) {
-
+ } else if (*tune_state == CT_TUNER_STEP_1) {
/* initialize the lt gain register */
state->rf_lt_def = 0x7c00;
- dib0090_write_reg(state, 0x0f, state->rf_lt_def);
dib0090_set_bandwidth(state);
state->tuner_is_tuned = 1;
+
+ state->calibrate |= WBD_CAL;
+ state->calibrate |= TEMP_CAL;
*tune_state = CT_TUNER_STOP;
} else
ret = FE_CALLBACK_TIME_NEVER;
@@ -1440,6 +2317,7 @@ enum frontend_tune_state dib0090_get_tune_state(struct dvb_frontend *fe)
return state->tune_state;
}
+
EXPORT_SYMBOL(dib0090_get_tune_state);
int dib0090_set_tune_state(struct dvb_frontend *fe, enum frontend_tune_state tune_state)
@@ -1449,6 +2327,7 @@ int dib0090_set_tune_state(struct dvb_frontend *fe, enum frontend_tune_state tun
state->tune_state = tune_state;
return 0;
}
+
EXPORT_SYMBOL(dib0090_set_tune_state);
static int dib0090_get_frequency(struct dvb_frontend *fe, u32 * frequency)
@@ -1462,7 +2341,7 @@ static int dib0090_get_frequency(struct dvb_frontend *fe, u32 * frequency)
static int dib0090_set_params(struct dvb_frontend *fe, struct dvb_frontend_parameters *p)
{
struct dib0090_state *state = fe->tuner_priv;
- uint32_t ret;
+ u32 ret;
state->tune_state = CT_TUNER_START;
@@ -1492,6 +2371,29 @@ static const struct dvb_tuner_ops dib0090_ops = {
.get_frequency = dib0090_get_frequency,
};
+static const struct dvb_tuner_ops dib0090_fw_ops = {
+ .info = {
+ .name = "DiBcom DiB0090",
+ .frequency_min = 45000000,
+ .frequency_max = 860000000,
+ .frequency_step = 1000,
+ },
+ .release = dib0090_release,
+
+ .init = NULL,
+ .sleep = NULL,
+ .set_params = NULL,
+ .get_frequency = NULL,
+};
+
+static const struct dib0090_wbd_slope dib0090_wbd_table_default[] = {
+ {470, 0, 250, 0, 100, 4},
+ {860, 51, 866, 21, 375, 4},
+ {1700, 0, 800, 0, 850, 4},
+ {2900, 0, 250, 0, 100, 6},
+ {0xFFFF, 0, 0, 0, 0, 0},
+};
+
struct dvb_frontend *dib0090_register(struct dvb_frontend *fe, struct i2c_adapter *i2c, const struct dib0090_config *config)
{
struct dib0090_state *st = kzalloc(sizeof(struct dib0090_state), GFP_KERNEL);
@@ -1503,6 +2405,11 @@ struct dvb_frontend *dib0090_register(struct dvb_frontend *fe, struct i2c_adapte
st->fe = fe;
fe->tuner_priv = st;
+ if (config->wbd == NULL)
+ st->current_wbd_table = dib0090_wbd_table_default;
+ else
+ st->current_wbd_table = config->wbd;
+
if (dib0090_reset(fe) != 0)
goto free_mem;
@@ -1515,8 +2422,34 @@ struct dvb_frontend *dib0090_register(struct dvb_frontend *fe, struct i2c_adapte
fe->tuner_priv = NULL;
return NULL;
}
+
EXPORT_SYMBOL(dib0090_register);
+struct dvb_frontend *dib0090_fw_register(struct dvb_frontend *fe, struct i2c_adapter *i2c, const struct dib0090_config *config)
+{
+ struct dib0090_fw_state *st = kzalloc(sizeof(struct dib0090_fw_state), GFP_KERNEL);
+ if (st == NULL)
+ return NULL;
+
+ st->config = config;
+ st->i2c = i2c;
+ st->fe = fe;
+ fe->tuner_priv = st;
+
+ if (dib0090_fw_reset_digital(fe, st->config) != 0)
+ goto free_mem;
+
+ dprintk("DiB0090 FW: successfully identified");
+ memcpy(&fe->ops.tuner_ops, &dib0090_fw_ops, sizeof(struct dvb_tuner_ops));
+
+ return fe;
+free_mem:
+ kfree(st);
+ fe->tuner_priv = NULL;
+ return NULL;
+}
+EXPORT_SYMBOL(dib0090_fw_register);
+
MODULE_AUTHOR("Patrick Boettcher <pboettcher@dibcom.fr>");
MODULE_AUTHOR("Olivier Grenie <olivier.grenie@dibcom.fr>");
MODULE_DESCRIPTION("Driver for the DiBcom 0090 base-band RF Tuner");
diff --git a/drivers/media/dvb/frontends/dib0090.h b/drivers/media/dvb/frontends/dib0090.h
index aa7711e8877..13d85244ec1 100644
--- a/drivers/media/dvb/frontends/dib0090.h
+++ b/drivers/media/dvb/frontends/dib0090.h
@@ -27,6 +27,21 @@ struct dib0090_io_config {
u16 pll_int_loop_filt;
};
+struct dib0090_wbd_slope {
+ u16 max_freq; /* for every frequency less than or equal to that field: this information is correct */
+ u16 slope_cold;
+ u16 offset_cold;
+ u16 slope_hot;
+ u16 offset_hot;
+ u8 wbd_gain;
+};
+
+struct dib0090_low_if_offset_table {
+ int std;
+ u32 RF_freq;
+ s32 offset_khz;
+};
+
struct dib0090_config {
struct dib0090_io_config io;
int (*reset) (struct dvb_frontend *, int);
@@ -47,10 +62,20 @@ struct dib0090_config {
u16 wbd_cband_offset;
u8 use_pwm_agc;
u8 clkoutdrive;
+
+ u8 ls_cfg_pad_drv;
+ u8 data_tx_drv;
+
+ u8 in_soc;
+ const struct dib0090_low_if_offset_table *low_if;
+ u8 fref_clock_ratio;
+ u16 force_cband_input;
+ struct dib0090_wbd_slope *wbd;
};
#if defined(CONFIG_DVB_TUNER_DIB0090) || (defined(CONFIG_DVB_TUNER_DIB0090_MODULE) && defined(MODULE))
extern struct dvb_frontend *dib0090_register(struct dvb_frontend *fe, struct i2c_adapter *i2c, const struct dib0090_config *config);
+extern struct dvb_frontend *dib0090_fw_register(struct dvb_frontend *fe, struct i2c_adapter *i2c, const struct dib0090_config *config);
extern void dib0090_dcc_freq(struct dvb_frontend *fe, u8 fast);
extern void dib0090_pwm_gain_reset(struct dvb_frontend *fe);
extern u16 dib0090_get_wbd_offset(struct dvb_frontend *tuner);
@@ -65,6 +90,12 @@ static inline struct dvb_frontend *dib0090_register(struct dvb_frontend *fe, str
return NULL;
}
+static inline struct dvb_frontend *dib0090_fw_register(struct dvb_frontend *fe, struct i2c_adapter *i2c, struct dib0090_config *config)
+{
+ printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
+ return NULL;
+}
+
static inline void dib0090_dcc_freq(struct dvb_frontend *fe, u8 fast)
{
printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
diff --git a/drivers/media/dvb/frontends/dib7000p.c b/drivers/media/dvb/frontends/dib7000p.c
index 6aa02cb8073..900af60b9d3 100644
--- a/drivers/media/dvb/frontends/dib7000p.c
+++ b/drivers/media/dvb/frontends/dib7000p.c
@@ -26,24 +26,29 @@ MODULE_PARM_DESC(buggy_sfn_workaround, "Enable work-around for buggy SFNs (defau
#define dprintk(args...) do { if (debug) { printk(KERN_DEBUG "DiB7000P: "); printk(args); printk("\n"); } } while (0)
+struct i2c_device {
+ struct i2c_adapter *i2c_adap;
+ u8 i2c_addr;
+};
+
struct dib7000p_state {
struct dvb_frontend demod;
- struct dib7000p_config cfg;
+ struct dib7000p_config cfg;
u8 i2c_addr;
- struct i2c_adapter *i2c_adap;
+ struct i2c_adapter *i2c_adap;
struct dibx000_i2c_master i2c_master;
u16 wbd_ref;
- u8 current_band;
+ u8 current_band;
u32 current_bandwidth;
struct dibx000_agc_config *current_agc;
u32 timf;
- u8 div_force_off : 1;
- u8 div_state : 1;
+ u8 div_force_off:1;
+ u8 div_state:1;
u16 div_sync_wait;
u8 agc_state;
@@ -51,7 +56,13 @@ struct dib7000p_state {
u16 gpio_dir;
u16 gpio_val;
- u8 sfn_workaround_active :1;
+ u8 sfn_workaround_active:1;
+
+#define SOC7090 0x7090
+ u16 version;
+
+ u16 tuner_enable;
+ struct i2c_adapter dib7090_tuner_adap;
};
enum dib7000p_power_mode {
@@ -60,17 +71,20 @@ enum dib7000p_power_mode {
DIB7000P_POWER_INTERFACE_ONLY,
};
+static int dib7090_set_output_mode(struct dvb_frontend *fe, int mode);
+static int dib7090_set_diversity_in(struct dvb_frontend *fe, int onoff);
+
static u16 dib7000p_read_word(struct dib7000p_state *state, u16 reg)
{
u8 wb[2] = { reg >> 8, reg & 0xff };
u8 rb[2];
struct i2c_msg msg[2] = {
- { .addr = state->i2c_addr >> 1, .flags = 0, .buf = wb, .len = 2 },
- { .addr = state->i2c_addr >> 1, .flags = I2C_M_RD, .buf = rb, .len = 2 },
+ {.addr = state->i2c_addr >> 1, .flags = 0, .buf = wb, .len = 2},
+ {.addr = state->i2c_addr >> 1, .flags = I2C_M_RD, .buf = rb, .len = 2},
};
if (i2c_transfer(state->i2c_adap, msg, 2) != 2)
- dprintk("i2c read error on %d",reg);
+ dprintk("i2c read error on %d", reg);
return (rb[0] << 8) | rb[1];
}
@@ -86,7 +100,8 @@ static int dib7000p_write_word(struct dib7000p_state *state, u16 reg, u16 val)
};
return i2c_transfer(state->i2c_adap, &msg, 1) != 1 ? -EREMOTEIO : 0;
}
-static void dib7000p_write_tab(struct dib7000p_state *state, u16 *buf)
+
+static void dib7000p_write_tab(struct dib7000p_state *state, u16 * buf)
{
u16 l = 0, r, *n;
n = buf;
@@ -104,54 +119,54 @@ static void dib7000p_write_tab(struct dib7000p_state *state, u16 *buf)
static int dib7000p_set_output_mode(struct dib7000p_state *state, int mode)
{
- int ret = 0;
+ int ret = 0;
u16 outreg, fifo_threshold, smo_mode;
outreg = 0;
fifo_threshold = 1792;
smo_mode = (dib7000p_read_word(state, 235) & 0x0050) | (1 << 1);
- dprintk( "setting output mode for demod %p to %d",
- &state->demod, mode);
+ dprintk("setting output mode for demod %p to %d", &state->demod, mode);
switch (mode) {
- case OUTMODE_MPEG2_PAR_GATED_CLK: // STBs with parallel gated clock
- outreg = (1 << 10); /* 0x0400 */
- break;
- case OUTMODE_MPEG2_PAR_CONT_CLK: // STBs with parallel continues clock
- outreg = (1 << 10) | (1 << 6); /* 0x0440 */
- break;
- case OUTMODE_MPEG2_SERIAL: // STBs with serial input
- outreg = (1 << 10) | (2 << 6) | (0 << 1); /* 0x0480 */
- break;
- case OUTMODE_DIVERSITY:
- if (state->cfg.hostbus_diversity)
- outreg = (1 << 10) | (4 << 6); /* 0x0500 */
- else
- outreg = (1 << 11);
- break;
- case OUTMODE_MPEG2_FIFO: // e.g. USB feeding
- smo_mode |= (3 << 1);
- fifo_threshold = 512;
- outreg = (1 << 10) | (5 << 6);
- break;
- case OUTMODE_ANALOG_ADC:
- outreg = (1 << 10) | (3 << 6);
- break;
- case OUTMODE_HIGH_Z: // disable
- outreg = 0;
- break;
- default:
- dprintk( "Unhandled output_mode passed to be set for demod %p",&state->demod);
- break;
+ case OUTMODE_MPEG2_PAR_GATED_CLK:
+ outreg = (1 << 10); /* 0x0400 */
+ break;
+ case OUTMODE_MPEG2_PAR_CONT_CLK:
+ outreg = (1 << 10) | (1 << 6); /* 0x0440 */
+ break;
+ case OUTMODE_MPEG2_SERIAL:
+ outreg = (1 << 10) | (2 << 6) | (0 << 1); /* 0x0480 */
+ break;
+ case OUTMODE_DIVERSITY:
+ if (state->cfg.hostbus_diversity)
+ outreg = (1 << 10) | (4 << 6); /* 0x0500 */
+ else
+ outreg = (1 << 11);
+ break;
+ case OUTMODE_MPEG2_FIFO:
+ smo_mode |= (3 << 1);
+ fifo_threshold = 512;
+ outreg = (1 << 10) | (5 << 6);
+ break;
+ case OUTMODE_ANALOG_ADC:
+ outreg = (1 << 10) | (3 << 6);
+ break;
+ case OUTMODE_HIGH_Z:
+ outreg = 0;
+ break;
+ default:
+ dprintk("Unhandled output_mode passed to be set for demod %p", &state->demod);
+ break;
}
if (state->cfg.output_mpeg2_in_188_bytes)
- smo_mode |= (1 << 5) ;
+ smo_mode |= (1 << 5);
- ret |= dib7000p_write_word(state, 235, smo_mode);
- ret |= dib7000p_write_word(state, 236, fifo_threshold); /* synchronous fread */
- ret |= dib7000p_write_word(state, 1286, outreg); /* P_Div_active */
+ ret |= dib7000p_write_word(state, 235, smo_mode);
+ ret |= dib7000p_write_word(state, 236, fifo_threshold); /* synchronous fread */
+ if (state->version != SOC7090)
+ ret |= dib7000p_write_word(state, 1286, outreg); /* P_Div_active */
return ret;
}
@@ -161,13 +176,13 @@ static int dib7000p_set_diversity_in(struct dvb_frontend *demod, int onoff)
struct dib7000p_state *state = demod->demodulator_priv;
if (state->div_force_off) {
- dprintk( "diversity combination deactivated - forced by COFDM parameters");
+ dprintk("diversity combination deactivated - forced by COFDM parameters");
onoff = 0;
dib7000p_write_word(state, 207, 0);
} else
dib7000p_write_word(state, 207, (state->div_sync_wait << 4) | (1 << 2) | (2 << 0));
- state->div_state = (u8)onoff;
+ state->div_state = (u8) onoff;
if (onoff) {
dib7000p_write_word(state, 204, 6);
@@ -184,37 +199,48 @@ static int dib7000p_set_diversity_in(struct dvb_frontend *demod, int onoff)
static int dib7000p_set_power_mode(struct dib7000p_state *state, enum dib7000p_power_mode mode)
{
/* by default everything is powered off */
- u16 reg_774 = 0xffff, reg_775 = 0xffff, reg_776 = 0x0007, reg_899 = 0x0003,
- reg_1280 = (0xfe00) | (dib7000p_read_word(state, 1280) & 0x01ff);
+ u16 reg_774 = 0x3fff, reg_775 = 0xffff, reg_776 = 0x0007, reg_899 = 0x0003, reg_1280 = (0xfe00) | (dib7000p_read_word(state, 1280) & 0x01ff);
/* now, depending on the requested mode, we power on */
switch (mode) {
/* power up everything in the demod */
- case DIB7000P_POWER_ALL:
- reg_774 = 0x0000; reg_775 = 0x0000; reg_776 = 0x0; reg_899 = 0x0; reg_1280 &= 0x01ff;
- break;
-
- case DIB7000P_POWER_ANALOG_ADC:
- /* dem, cfg, iqc, sad, agc */
- reg_774 &= ~((1 << 15) | (1 << 14) | (1 << 11) | (1 << 10) | (1 << 9));
- /* nud */
- reg_776 &= ~((1 << 0));
- /* Dout */
+ case DIB7000P_POWER_ALL:
+ reg_774 = 0x0000;
+ reg_775 = 0x0000;
+ reg_776 = 0x0;
+ reg_899 = 0x0;
+ if (state->version == SOC7090)
+ reg_1280 &= 0x001f;
+ else
+ reg_1280 &= 0x01ff;
+ break;
+
+ case DIB7000P_POWER_ANALOG_ADC:
+ /* dem, cfg, iqc, sad, agc */
+ reg_774 &= ~((1 << 15) | (1 << 14) | (1 << 11) | (1 << 10) | (1 << 9));
+ /* nud */
+ reg_776 &= ~((1 << 0));
+ /* Dout */
+ if (state->version != SOC7090)
reg_1280 &= ~((1 << 11));
- /* fall through wanted to enable the interfaces */
+ reg_1280 &= ~(1 << 6);
+ /* fall through wanted to enable the interfaces */
/* just leave power on the control-interfaces: GPIO and (I2C or SDIO) */
- case DIB7000P_POWER_INTERFACE_ONLY: /* TODO power up either SDIO or I2C */
+ case DIB7000P_POWER_INTERFACE_ONLY: /* TODO power up either SDIO or I2C */
+ if (state->version == SOC7090)
+ reg_1280 &= ~((1 << 7) | (1 << 5));
+ else
reg_1280 &= ~((1 << 14) | (1 << 13) | (1 << 12) | (1 << 10));
- break;
+ break;
/* TODO following stuff is just converted from the dib7000-driver - check when is used what */
}
- dib7000p_write_word(state, 774, reg_774);
- dib7000p_write_word(state, 775, reg_775);
- dib7000p_write_word(state, 776, reg_776);
- dib7000p_write_word(state, 899, reg_899);
+ dib7000p_write_word(state, 774, reg_774);
+ dib7000p_write_word(state, 775, reg_775);
+ dib7000p_write_word(state, 776, reg_776);
+ dib7000p_write_word(state, 899, reg_899);
dib7000p_write_word(state, 1280, reg_1280);
return 0;
@@ -222,40 +248,57 @@ static int dib7000p_set_power_mode(struct dib7000p_state *state, enum dib7000p_p
static void dib7000p_set_adc_state(struct dib7000p_state *state, enum dibx000_adc_states no)
{
- u16 reg_908 = dib7000p_read_word(state, 908),
- reg_909 = dib7000p_read_word(state, 909);
+ u16 reg_908 = dib7000p_read_word(state, 908), reg_909 = dib7000p_read_word(state, 909);
+ u16 reg;
switch (no) {
- case DIBX000_SLOW_ADC_ON:
+ case DIBX000_SLOW_ADC_ON:
+ if (state->version == SOC7090) {
+ reg = dib7000p_read_word(state, 1925);
+
+ dib7000p_write_word(state, 1925, reg | (1 << 4) | (1 << 2)); /* en_slowAdc = 1 & reset_sladc = 1 */
+
+ reg = dib7000p_read_word(state, 1925); /* read acces to make it works... strange ... */
+ msleep(200);
+ dib7000p_write_word(state, 1925, reg & ~(1 << 4)); /* en_slowAdc = 1 & reset_sladc = 0 */
+
+ reg = dib7000p_read_word(state, 72) & ~((0x3 << 14) | (0x3 << 12));
+ dib7000p_write_word(state, 72, reg | (1 << 14) | (3 << 12) | 524); /* ref = Vin1 => Vbg ; sel = Vin0 or Vin3 ; (Vin2 = Vcm) */
+ } else {
reg_909 |= (1 << 1) | (1 << 0);
dib7000p_write_word(state, 909, reg_909);
reg_909 &= ~(1 << 1);
- break;
+ }
+ break;
- case DIBX000_SLOW_ADC_OFF:
- reg_909 |= (1 << 1) | (1 << 0);
- break;
+ case DIBX000_SLOW_ADC_OFF:
+ if (state->version == SOC7090) {
+ reg = dib7000p_read_word(state, 1925);
+ dib7000p_write_word(state, 1925, (reg & ~(1 << 2)) | (1 << 4)); /* reset_sladc = 1 en_slowAdc = 0 */
+ } else
+ reg_909 |= (1 << 1) | (1 << 0);
+ break;
- case DIBX000_ADC_ON:
- reg_908 &= 0x0fff;
- reg_909 &= 0x0003;
- break;
+ case DIBX000_ADC_ON:
+ reg_908 &= 0x0fff;
+ reg_909 &= 0x0003;
+ break;
- case DIBX000_ADC_OFF: // leave the VBG voltage on
- reg_908 |= (1 << 14) | (1 << 13) | (1 << 12);
- reg_909 |= (1 << 5) | (1 << 4) | (1 << 3) | (1 << 2);
- break;
+ case DIBX000_ADC_OFF:
+ reg_908 |= (1 << 14) | (1 << 13) | (1 << 12);
+ reg_909 |= (1 << 5) | (1 << 4) | (1 << 3) | (1 << 2);
+ break;
- case DIBX000_VBG_ENABLE:
- reg_908 &= ~(1 << 15);
- break;
+ case DIBX000_VBG_ENABLE:
+ reg_908 &= ~(1 << 15);
+ break;
- case DIBX000_VBG_DISABLE:
- reg_908 |= (1 << 15);
- break;
+ case DIBX000_VBG_DISABLE:
+ reg_908 |= (1 << 15);
+ break;
- default:
- break;
+ default:
+ break;
}
// dprintk( "908: %x, 909: %x\n", reg_908, reg_909);
@@ -275,17 +318,17 @@ static int dib7000p_set_bandwidth(struct dib7000p_state *state, u32 bw)
state->current_bandwidth = bw;
if (state->timf == 0) {
- dprintk( "using default timf");
+ dprintk("using default timf");
timf = state->cfg.bw->timf;
} else {
- dprintk( "using updated timf");
+ dprintk("using updated timf");
timf = state->timf;
}
timf = timf * (bw / 50) / 160;
dib7000p_write_word(state, 23, (u16) ((timf >> 16) & 0xffff));
- dib7000p_write_word(state, 24, (u16) ((timf ) & 0xffff));
+ dib7000p_write_word(state, 24, (u16) ((timf) & 0xffff));
return 0;
}
@@ -293,9 +336,12 @@ static int dib7000p_set_bandwidth(struct dib7000p_state *state, u32 bw)
static int dib7000p_sad_calib(struct dib7000p_state *state)
{
/* internal */
-// dib7000p_write_word(state, 72, (3 << 14) | (1 << 12) | (524 << 0)); // sampling clock of the SAD is writting in set_bandwidth
dib7000p_write_word(state, 73, (0 << 1) | (0 << 0));
- dib7000p_write_word(state, 74, 776); // 0.625*3.3 / 4096
+
+ if (state->version == SOC7090)
+ dib7000p_write_word(state, 74, 2048);
+ else
+ dib7000p_write_word(state, 74, 776);
/* do the calibration */
dib7000p_write_word(state, 73, (1 << 0));
@@ -314,37 +360,91 @@ int dib7000p_set_wbd_ref(struct dvb_frontend *demod, u16 value)
state->wbd_ref = value;
return dib7000p_write_word(state, 105, (dib7000p_read_word(state, 105) & 0xf000) | value);
}
-
EXPORT_SYMBOL(dib7000p_set_wbd_ref);
+
static void dib7000p_reset_pll(struct dib7000p_state *state)
{
struct dibx000_bandwidth_config *bw = &state->cfg.bw[0];
u16 clk_cfg0;
- /* force PLL bypass */
- clk_cfg0 = (1 << 15) | ((bw->pll_ratio & 0x3f) << 9) |
- (bw->modulo << 7) | (bw->ADClkSrc << 6) | (bw->IO_CLK_en_core << 5) |
- (bw->bypclk_div << 2) | (bw->enable_refdiv << 1) | (0 << 0);
+ if (state->version == SOC7090) {
+ dib7000p_write_word(state, 1856, (!bw->pll_reset << 13) | (bw->pll_range << 12) | (bw->pll_ratio << 6) | (bw->pll_prediv));
+
+ while (((dib7000p_read_word(state, 1856) >> 15) & 0x1) != 1)
+ ;
- dib7000p_write_word(state, 900, clk_cfg0);
+ dib7000p_write_word(state, 1857, dib7000p_read_word(state, 1857) | (!bw->pll_bypass << 15));
+ } else {
+ /* force PLL bypass */
+ clk_cfg0 = (1 << 15) | ((bw->pll_ratio & 0x3f) << 9) |
+ (bw->modulo << 7) | (bw->ADClkSrc << 6) | (bw->IO_CLK_en_core << 5) | (bw->bypclk_div << 2) | (bw->enable_refdiv << 1) | (0 << 0);
+
+ dib7000p_write_word(state, 900, clk_cfg0);
- /* P_pll_cfg */
- dib7000p_write_word(state, 903, (bw->pll_prediv << 5) | (((bw->pll_ratio >> 6) & 0x3) << 3) | (bw->pll_range << 1) | bw->pll_reset);
- clk_cfg0 = (bw->pll_bypass << 15) | (clk_cfg0 & 0x7fff);
- dib7000p_write_word(state, 900, clk_cfg0);
+ /* P_pll_cfg */
+ dib7000p_write_word(state, 903, (bw->pll_prediv << 5) | (((bw->pll_ratio >> 6) & 0x3) << 3) | (bw->pll_range << 1) | bw->pll_reset);
+ clk_cfg0 = (bw->pll_bypass << 15) | (clk_cfg0 & 0x7fff);
+ dib7000p_write_word(state, 900, clk_cfg0);
+ }
- dib7000p_write_word(state, 18, (u16) (((bw->internal*1000) >> 16) & 0xffff));
- dib7000p_write_word(state, 19, (u16) ( (bw->internal*1000 ) & 0xffff));
- dib7000p_write_word(state, 21, (u16) ( (bw->ifreq >> 16) & 0xffff));
- dib7000p_write_word(state, 22, (u16) ( (bw->ifreq ) & 0xffff));
+ dib7000p_write_word(state, 18, (u16) (((bw->internal * 1000) >> 16) & 0xffff));
+ dib7000p_write_word(state, 19, (u16) ((bw->internal * 1000) & 0xffff));
+ dib7000p_write_word(state, 21, (u16) ((bw->ifreq >> 16) & 0xffff));
+ dib7000p_write_word(state, 22, (u16) ((bw->ifreq) & 0xffff));
dib7000p_write_word(state, 72, bw->sad_cfg);
}
+static u32 dib7000p_get_internal_freq(struct dib7000p_state *state)
+{
+ u32 internal = (u32) dib7000p_read_word(state, 18) << 16;
+ internal |= (u32) dib7000p_read_word(state, 19);
+ internal /= 1000;
+
+ return internal;
+}
+
+int dib7000p_update_pll(struct dvb_frontend *fe, struct dibx000_bandwidth_config *bw)
+{
+ struct dib7000p_state *state = fe->demodulator_priv;
+ u16 reg_1857, reg_1856 = dib7000p_read_word(state, 1856);
+ u8 loopdiv, prediv;
+ u32 internal, xtal;
+
+ /* get back old values */
+ prediv = reg_1856 & 0x3f;
+ loopdiv = (reg_1856 >> 6) & 0x3f;
+
+ if ((bw != NULL) && (bw->pll_prediv != prediv || bw->pll_ratio != loopdiv)) {
+ dprintk("Updating pll (prediv: old = %d new = %d ; loopdiv : old = %d new = %d)", prediv, bw->pll_prediv, loopdiv, bw->pll_ratio);
+ reg_1856 &= 0xf000;
+ reg_1857 = dib7000p_read_word(state, 1857);
+ dib7000p_write_word(state, 1857, reg_1857 & ~(1 << 15));
+
+ dib7000p_write_word(state, 1856, reg_1856 | ((bw->pll_ratio & 0x3f) << 6) | (bw->pll_prediv & 0x3f));
+
+ /* write new system clk into P_sec_len */
+ internal = dib7000p_get_internal_freq(state);
+ xtal = (internal / loopdiv) * prediv;
+ internal = 1000 * (xtal / bw->pll_prediv) * bw->pll_ratio; /* new internal */
+ dib7000p_write_word(state, 18, (u16) ((internal >> 16) & 0xffff));
+ dib7000p_write_word(state, 19, (u16) (internal & 0xffff));
+
+ dib7000p_write_word(state, 1857, reg_1857 | (1 << 15));
+
+ while (((dib7000p_read_word(state, 1856) >> 15) & 0x1) != 1)
+ dprintk("Waiting for PLL to lock");
+
+ return 0;
+ }
+ return -EIO;
+}
+EXPORT_SYMBOL(dib7000p_update_pll);
+
static int dib7000p_reset_gpio(struct dib7000p_state *st)
{
/* reset the GPIOs */
- dprintk( "gpio dir: %x: val: %x, pwm_pos: %x",st->gpio_dir, st->gpio_val,st->cfg.gpio_pwm_pos);
+ dprintk("gpio dir: %x: val: %x, pwm_pos: %x", st->gpio_dir, st->gpio_val, st->cfg.gpio_pwm_pos);
dib7000p_write_word(st, 1029, st->gpio_dir);
dib7000p_write_word(st, 1030, st->gpio_val);
@@ -360,13 +460,13 @@ static int dib7000p_reset_gpio(struct dib7000p_state *st)
static int dib7000p_cfg_gpio(struct dib7000p_state *st, u8 num, u8 dir, u8 val)
{
st->gpio_dir = dib7000p_read_word(st, 1029);
- st->gpio_dir &= ~(1 << num); /* reset the direction bit */
- st->gpio_dir |= (dir & 0x1) << num; /* set the new direction */
+ st->gpio_dir &= ~(1 << num); /* reset the direction bit */
+ st->gpio_dir |= (dir & 0x1) << num; /* set the new direction */
dib7000p_write_word(st, 1029, st->gpio_dir);
st->gpio_val = dib7000p_read_word(st, 1030);
- st->gpio_val &= ~(1 << num); /* reset the direction bit */
- st->gpio_val |= (val & 0x01) << num; /* set the new value */
+ st->gpio_val &= ~(1 << num); /* reset the direction bit */
+ st->gpio_val |= (val & 0x01) << num; /* set the new value */
dib7000p_write_word(st, 1030, st->gpio_val);
return 0;
@@ -377,96 +477,94 @@ int dib7000p_set_gpio(struct dvb_frontend *demod, u8 num, u8 dir, u8 val)
struct dib7000p_state *state = demod->demodulator_priv;
return dib7000p_cfg_gpio(state, num, dir, val);
}
-
EXPORT_SYMBOL(dib7000p_set_gpio);
-static u16 dib7000p_defaults[] =
-{
+static u16 dib7000p_defaults[] = {
// auto search configuration
3, 2,
- 0x0004,
- 0x1000,
- 0x0814, /* Equal Lock */
+ 0x0004,
+ 0x1000,
+ 0x0814, /* Equal Lock */
12, 6,
- 0x001b,
- 0x7740,
- 0x005b,
- 0x8d80,
- 0x01c9,
- 0xc380,
- 0x0000,
- 0x0080,
- 0x0000,
- 0x0090,
- 0x0001,
- 0xd4c0,
+ 0x001b,
+ 0x7740,
+ 0x005b,
+ 0x8d80,
+ 0x01c9,
+ 0xc380,
+ 0x0000,
+ 0x0080,
+ 0x0000,
+ 0x0090,
+ 0x0001,
+ 0xd4c0,
1, 26,
- 0x6680, // P_timf_alpha=6, P_corm_alpha=6, P_corm_thres=128 default: 6,4,26
+ 0x6680,
/* set ADC level to -16 */
11, 79,
- (1 << 13) - 825 - 117,
- (1 << 13) - 837 - 117,
- (1 << 13) - 811 - 117,
- (1 << 13) - 766 - 117,
- (1 << 13) - 737 - 117,
- (1 << 13) - 693 - 117,
- (1 << 13) - 648 - 117,
- (1 << 13) - 619 - 117,
- (1 << 13) - 575 - 117,
- (1 << 13) - 531 - 117,
- (1 << 13) - 501 - 117,
+ (1 << 13) - 825 - 117,
+ (1 << 13) - 837 - 117,
+ (1 << 13) - 811 - 117,
+ (1 << 13) - 766 - 117,
+ (1 << 13) - 737 - 117,
+ (1 << 13) - 693 - 117,
+ (1 << 13) - 648 - 117,
+ (1 << 13) - 619 - 117,
+ (1 << 13) - 575 - 117,
+ (1 << 13) - 531 - 117,
+ (1 << 13) - 501 - 117,
1, 142,
- 0x0410, // P_palf_filter_on=1, P_palf_filter_freeze=0, P_palf_alpha_regul=16
+ 0x0410,
/* disable power smoothing */
8, 145,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
1, 154,
- 1 << 13, // P_fft_freq_dir=1, P_fft_nb_to_cut=0
+ 1 << 13,
1, 168,
- 0x0ccd, // P_pha3_thres, default 0x3000
-
-// 1, 169,
-// 0x0010, // P_cti_use_cpe=0, P_cti_use_prog=0, P_cti_win_len=16, default: 0x0010
+ 0x0ccd,
1, 183,
- 0x200f, // P_cspu_regul=512, P_cspu_win_cut=15, default: 0x2005
+ 0x200f,
+
+ 1, 212,
+ 0x169,
5, 187,
- 0x023d, // P_adp_regul_cnt=573, default: 410
- 0x00a4, // P_adp_noise_cnt=
- 0x00a4, // P_adp_regul_ext
- 0x7ff0, // P_adp_noise_ext
- 0x3ccc, // P_adp_fil
+ 0x023d,
+ 0x00a4,
+ 0x00a4,
+ 0x7ff0,
+ 0x3ccc,
1, 198,
- 0x800, // P_equal_thres_wgn
+ 0x800,
1, 222,
- 0x0010, // P_fec_ber_rs_len=2
+ 0x0010,
1, 235,
- 0x0062, // P_smo_mode, P_smo_rs_discard, P_smo_fifo_flush, P_smo_pid_parse, P_smo_error_discard
+ 0x0062,
2, 901,
- 0x0006, // P_clk_cfg1
- (3 << 10) | (1 << 6), // P_divclksel=3 P_divbitsel=1
+ 0x0006,
+ (3 << 10) | (1 << 6),
1, 905,
- 0x2c8e, // Tuner IO bank: max drive (14mA) + divout pads max drive
+ 0x2c8e,
0,
};
@@ -475,51 +573,64 @@ static int dib7000p_demod_reset(struct dib7000p_state *state)
{
dib7000p_set_power_mode(state, DIB7000P_POWER_ALL);
+ if (state->version == SOC7090)
+ dibx000_reset_i2c_master(&state->i2c_master);
+
dib7000p_set_adc_state(state, DIBX000_VBG_ENABLE);
/* restart all parts */
- dib7000p_write_word(state, 770, 0xffff);
- dib7000p_write_word(state, 771, 0xffff);
- dib7000p_write_word(state, 772, 0x001f);
- dib7000p_write_word(state, 898, 0x0003);
- /* except i2c, sdio, gpio - control interfaces */
- dib7000p_write_word(state, 1280, 0x01fc - ((1 << 7) | (1 << 6) | (1 << 5)) );
-
- dib7000p_write_word(state, 770, 0);
- dib7000p_write_word(state, 771, 0);
- dib7000p_write_word(state, 772, 0);
- dib7000p_write_word(state, 898, 0);
+ dib7000p_write_word(state, 770, 0xffff);
+ dib7000p_write_word(state, 771, 0xffff);
+ dib7000p_write_word(state, 772, 0x001f);
+ dib7000p_write_word(state, 898, 0x0003);
+ dib7000p_write_word(state, 1280, 0x001f - ((1 << 4) | (1 << 3)));
+
+ dib7000p_write_word(state, 770, 0);
+ dib7000p_write_word(state, 771, 0);
+ dib7000p_write_word(state, 772, 0);
+ dib7000p_write_word(state, 898, 0);
dib7000p_write_word(state, 1280, 0);
/* default */
dib7000p_reset_pll(state);
if (dib7000p_reset_gpio(state) != 0)
- dprintk( "GPIO reset was not successful.");
-
- if (dib7000p_set_output_mode(state, OUTMODE_HIGH_Z) != 0)
- dprintk( "OUTPUT_MODE could not be reset.");
+ dprintk("GPIO reset was not successful.");
- /* unforce divstr regardless whether i2c enumeration was done or not */
- dib7000p_write_word(state, 1285, dib7000p_read_word(state, 1285) & ~(1 << 1) );
+ if (state->version == SOC7090) {
+ dib7000p_write_word(state, 899, 0);
- dib7000p_set_bandwidth(state, 8000);
+ /* impulse noise */
+ dib7000p_write_word(state, 42, (1<<5) | 3); /* P_iqc_thsat_ipc = 1 ; P_iqc_win2 = 3 */
+ dib7000p_write_word(state, 43, 0x2d4); /*-300 fag P_iqc_dect_min = -280 */
+ dib7000p_write_word(state, 44, 300); /* 300 fag P_iqc_dect_min = +280 */
+ dib7000p_write_word(state, 273, (1<<6) | 30);
+ }
+ if (dib7000p_set_output_mode(state, OUTMODE_HIGH_Z) != 0)
+ dprintk("OUTPUT_MODE could not be reset.");
dib7000p_set_adc_state(state, DIBX000_SLOW_ADC_ON);
dib7000p_sad_calib(state);
dib7000p_set_adc_state(state, DIBX000_SLOW_ADC_OFF);
- // P_iqc_alpha_pha, P_iqc_alpha_amp_dcc_alpha, ...
- if(state->cfg.tuner_is_baseband)
- dib7000p_write_word(state, 36,0x0755);
- else
- dib7000p_write_word(state, 36,0x1f55);
+ /* unforce divstr regardless whether i2c enumeration was done or not */
+ dib7000p_write_word(state, 1285, dib7000p_read_word(state, 1285) & ~(1 << 1));
+
+ dib7000p_set_bandwidth(state, 8000);
+
+ if (state->version == SOC7090) {
+ dib7000p_write_word(state, 36, 0x5755);/* P_iqc_impnc_on =1 & P_iqc_corr_inh = 1 for impulsive noise */
+ } else {
+ if (state->cfg.tuner_is_baseband)
+ dib7000p_write_word(state, 36, 0x0755);
+ else
+ dib7000p_write_word(state, 36, 0x1f55);
+ }
dib7000p_write_tab(state, dib7000p_defaults);
dib7000p_set_power_mode(state, DIB7000P_POWER_INTERFACE_ONLY);
-
return 0;
}
@@ -527,9 +638,9 @@ static void dib7000p_pll_clk_cfg(struct dib7000p_state *state)
{
u16 tmp = 0;
tmp = dib7000p_read_word(state, 903);
- dib7000p_write_word(state, 903, (tmp | 0x1)); //pwr-up pll
+ dib7000p_write_word(state, 903, (tmp | 0x1));
tmp = dib7000p_read_word(state, 900);
- dib7000p_write_word(state, 900, (tmp & 0x7fff) | (1 << 6)); //use High freq clock
+ dib7000p_write_word(state, 900, (tmp & 0x7fff) | (1 << 6));
}
static void dib7000p_restart_agc(struct dib7000p_state *state)
@@ -543,11 +654,9 @@ static int dib7000p_update_lna(struct dib7000p_state *state)
{
u16 dyn_gain;
- // when there is no LNA to program return immediatly
if (state->cfg.update_lna) {
- // read dyn_gain here (because it is demod-dependent and not fe)
dyn_gain = dib7000p_read_word(state, 394);
- if (state->cfg.update_lna(&state->demod,dyn_gain)) { // LNA has changed
+ if (state->cfg.update_lna(&state->demod, dyn_gain)) {
dib7000p_restart_agc(state);
return 1;
}
@@ -571,24 +680,24 @@ static int dib7000p_set_agc_config(struct dib7000p_state *state, u8 band)
}
if (agc == NULL) {
- dprintk( "no valid AGC configuration found for band 0x%02x",band);
+ dprintk("no valid AGC configuration found for band 0x%02x", band);
return -EINVAL;
}
state->current_agc = agc;
/* AGC */
- dib7000p_write_word(state, 75 , agc->setup );
- dib7000p_write_word(state, 76 , agc->inv_gain );
- dib7000p_write_word(state, 77 , agc->time_stabiliz );
+ dib7000p_write_word(state, 75, agc->setup);
+ dib7000p_write_word(state, 76, agc->inv_gain);
+ dib7000p_write_word(state, 77, agc->time_stabiliz);
dib7000p_write_word(state, 100, (agc->alpha_level << 12) | agc->thlock);
// Demod AGC loop configuration
dib7000p_write_word(state, 101, (agc->alpha_mant << 5) | agc->alpha_exp);
- dib7000p_write_word(state, 102, (agc->beta_mant << 6) | agc->beta_exp);
+ dib7000p_write_word(state, 102, (agc->beta_mant << 6) | agc->beta_exp);
/* AGC continued */
- dprintk( "WBD: ref: %d, sel: %d, active: %d, alpha: %d",
+ dprintk("WBD: ref: %d, sel: %d, active: %d, alpha: %d",
state->wbd_ref != 0 ? state->wbd_ref : agc->wbd_ref, agc->wbd_sel, !agc->perform_agc_softsplit, agc->wbd_sel);
if (state->wbd_ref != 0)
@@ -598,101 +707,135 @@ static int dib7000p_set_agc_config(struct dib7000p_state *state, u8 band)
dib7000p_write_word(state, 106, (agc->wbd_sel << 13) | (agc->wbd_alpha << 9) | (agc->perform_agc_softsplit << 8));
- dib7000p_write_word(state, 107, agc->agc1_max);
- dib7000p_write_word(state, 108, agc->agc1_min);
- dib7000p_write_word(state, 109, agc->agc2_max);
- dib7000p_write_word(state, 110, agc->agc2_min);
- dib7000p_write_word(state, 111, (agc->agc1_pt1 << 8) | agc->agc1_pt2);
- dib7000p_write_word(state, 112, agc->agc1_pt3);
+ dib7000p_write_word(state, 107, agc->agc1_max);
+ dib7000p_write_word(state, 108, agc->agc1_min);
+ dib7000p_write_word(state, 109, agc->agc2_max);
+ dib7000p_write_word(state, 110, agc->agc2_min);
+ dib7000p_write_word(state, 111, (agc->agc1_pt1 << 8) | agc->agc1_pt2);
+ dib7000p_write_word(state, 112, agc->agc1_pt3);
dib7000p_write_word(state, 113, (agc->agc1_slope1 << 8) | agc->agc1_slope2);
- dib7000p_write_word(state, 114, (agc->agc2_pt1 << 8) | agc->agc2_pt2);
+ dib7000p_write_word(state, 114, (agc->agc2_pt1 << 8) | agc->agc2_pt2);
dib7000p_write_word(state, 115, (agc->agc2_slope1 << 8) | agc->agc2_slope2);
return 0;
}
+static void dib7000p_set_dds(struct dib7000p_state *state, s32 offset_khz)
+{
+ u32 internal = dib7000p_get_internal_freq(state);
+ s32 unit_khz_dds_val = 67108864 / (internal); /* 2**26 / Fsampling is the unit 1KHz offset */
+ u32 abs_offset_khz = ABS(offset_khz);
+ u32 dds = state->cfg.bw->ifreq & 0x1ffffff;
+ u8 invert = !!(state->cfg.bw->ifreq & (1 << 25));
+
+ dprintk("setting a frequency offset of %dkHz internal freq = %d invert = %d", offset_khz, internal, invert);
+
+ if (offset_khz < 0)
+ unit_khz_dds_val *= -1;
+
+ /* IF tuner */
+ if (invert)
+ dds -= (abs_offset_khz * unit_khz_dds_val); /* /100 because of /100 on the unit_khz_dds_val line calc for better accuracy */
+ else
+ dds += (abs_offset_khz * unit_khz_dds_val);
+
+ if (abs_offset_khz <= (internal / 2)) { /* Max dds offset is the half of the demod freq */
+ dib7000p_write_word(state, 21, (u16) (((dds >> 16) & 0x1ff) | (0 << 10) | (invert << 9)));
+ dib7000p_write_word(state, 22, (u16) (dds & 0xffff));
+ }
+}
+
static int dib7000p_agc_startup(struct dvb_frontend *demod, struct dvb_frontend_parameters *ch)
{
struct dib7000p_state *state = demod->demodulator_priv;
int ret = -1;
u8 *agc_state = &state->agc_state;
u8 agc_split;
+ u16 reg;
+ u32 upd_demod_gain_period = 0x1000;
switch (state->agc_state) {
- case 0:
- // set power-up level: interf+analog+AGC
- dib7000p_set_power_mode(state, DIB7000P_POWER_ALL);
+ case 0:
+ dib7000p_set_power_mode(state, DIB7000P_POWER_ALL);
+ if (state->version == SOC7090) {
+ reg = dib7000p_read_word(state, 0x79b) & 0xff00;
+ dib7000p_write_word(state, 0x79a, upd_demod_gain_period & 0xFFFF); /* lsb */
+ dib7000p_write_word(state, 0x79b, reg | (1 << 14) | ((upd_demod_gain_period >> 16) & 0xFF));
+
+ /* enable adc i & q */
+ reg = dib7000p_read_word(state, 0x780);
+ dib7000p_write_word(state, 0x780, (reg | (0x3)) & (~(1 << 7)));
+ } else {
dib7000p_set_adc_state(state, DIBX000_ADC_ON);
dib7000p_pll_clk_cfg(state);
+ }
- if (dib7000p_set_agc_config(state, BAND_OF_FREQUENCY(ch->frequency/1000)) != 0)
- return -1;
-
- ret = 7;
- (*agc_state)++;
- break;
+ if (dib7000p_set_agc_config(state, BAND_OF_FREQUENCY(ch->frequency / 1000)) != 0)
+ return -1;
- case 1:
- // AGC initialization
- if (state->cfg.agc_control)
- state->cfg.agc_control(&state->demod, 1);
-
- dib7000p_write_word(state, 78, 32768);
- if (!state->current_agc->perform_agc_softsplit) {
- /* we are using the wbd - so slow AGC startup */
- /* force 0 split on WBD and restart AGC */
- dib7000p_write_word(state, 106, (state->current_agc->wbd_sel << 13) | (state->current_agc->wbd_alpha << 9) | (1 << 8));
- (*agc_state)++;
- ret = 5;
- } else {
- /* default AGC startup */
- (*agc_state) = 4;
- /* wait AGC rough lock time */
- ret = 7;
- }
+ dib7000p_set_dds(state, 0);
+ ret = 7;
+ (*agc_state)++;
+ break;
- dib7000p_restart_agc(state);
- break;
+ case 1:
+ if (state->cfg.agc_control)
+ state->cfg.agc_control(&state->demod, 1);
- case 2: /* fast split search path after 5sec */
- dib7000p_write_word(state, 75, state->current_agc->setup | (1 << 4)); /* freeze AGC loop */
- dib7000p_write_word(state, 106, (state->current_agc->wbd_sel << 13) | (2 << 9) | (0 << 8)); /* fast split search 0.25kHz */
+ dib7000p_write_word(state, 78, 32768);
+ if (!state->current_agc->perform_agc_softsplit) {
+ /* we are using the wbd - so slow AGC startup */
+ /* force 0 split on WBD and restart AGC */
+ dib7000p_write_word(state, 106, (state->current_agc->wbd_sel << 13) | (state->current_agc->wbd_alpha << 9) | (1 << 8));
(*agc_state)++;
- ret = 14;
- break;
+ ret = 5;
+ } else {
+ /* default AGC startup */
+ (*agc_state) = 4;
+ /* wait AGC rough lock time */
+ ret = 7;
+ }
- case 3: /* split search ended */
- agc_split = (u8)dib7000p_read_word(state, 396); /* store the split value for the next time */
- dib7000p_write_word(state, 78, dib7000p_read_word(state, 394)); /* set AGC gain start value */
+ dib7000p_restart_agc(state);
+ break;
- dib7000p_write_word(state, 75, state->current_agc->setup); /* std AGC loop */
- dib7000p_write_word(state, 106, (state->current_agc->wbd_sel << 13) | (state->current_agc->wbd_alpha << 9) | agc_split); /* standard split search */
+ case 2: /* fast split search path after 5sec */
+ dib7000p_write_word(state, 75, state->current_agc->setup | (1 << 4)); /* freeze AGC loop */
+ dib7000p_write_word(state, 106, (state->current_agc->wbd_sel << 13) | (2 << 9) | (0 << 8)); /* fast split search 0.25kHz */
+ (*agc_state)++;
+ ret = 14;
+ break;
- dib7000p_restart_agc(state);
+ case 3: /* split search ended */
+ agc_split = (u8) dib7000p_read_word(state, 396); /* store the split value for the next time */
+ dib7000p_write_word(state, 78, dib7000p_read_word(state, 394)); /* set AGC gain start value */
- dprintk( "SPLIT %p: %hd", demod, agc_split);
+ dib7000p_write_word(state, 75, state->current_agc->setup); /* std AGC loop */
+ dib7000p_write_word(state, 106, (state->current_agc->wbd_sel << 13) | (state->current_agc->wbd_alpha << 9) | agc_split); /* standard split search */
- (*agc_state)++;
- ret = 5;
- break;
+ dib7000p_restart_agc(state);
- case 4: /* LNA startup */
- // wait AGC accurate lock time
- ret = 7;
+ dprintk("SPLIT %p: %hd", demod, agc_split);
- if (dib7000p_update_lna(state))
- // wait only AGC rough lock time
- ret = 5;
- else // nothing was done, go to the next state
- (*agc_state)++;
- break;
+ (*agc_state)++;
+ ret = 5;
+ break;
- case 5:
- if (state->cfg.agc_control)
- state->cfg.agc_control(&state->demod, 0);
+ case 4: /* LNA startup */
+ ret = 7;
+
+ if (dib7000p_update_lna(state))
+ ret = 5;
+ else
(*agc_state)++;
- break;
- default:
- break;
+ break;
+
+ case 5:
+ if (state->cfg.agc_control)
+ state->cfg.agc_control(&state->demod, 0);
+ (*agc_state)++;
+ break;
+ default:
+ break;
}
return ret;
}
@@ -703,45 +846,89 @@ static void dib7000p_update_timf(struct dib7000p_state *state)
state->timf = timf * 160 / (state->current_bandwidth / 50);
dib7000p_write_word(state, 23, (u16) (timf >> 16));
dib7000p_write_word(state, 24, (u16) (timf & 0xffff));
- dprintk( "updated timf_frequency: %d (default: %d)",state->timf, state->cfg.bw->timf);
+ dprintk("updated timf_frequency: %d (default: %d)", state->timf, state->cfg.bw->timf);
+
+}
+u32 dib7000p_ctrl_timf(struct dvb_frontend *fe, u8 op, u32 timf)
+{
+ struct dib7000p_state *state = fe->demodulator_priv;
+ switch (op) {
+ case DEMOD_TIMF_SET:
+ state->timf = timf;
+ break;
+ case DEMOD_TIMF_UPDATE:
+ dib7000p_update_timf(state);
+ break;
+ case DEMOD_TIMF_GET:
+ break;
+ }
+ dib7000p_set_bandwidth(state, state->current_bandwidth);
+ return state->timf;
}
+EXPORT_SYMBOL(dib7000p_ctrl_timf);
static void dib7000p_set_channel(struct dib7000p_state *state, struct dvb_frontend_parameters *ch, u8 seq)
{
u16 value, est[4];
- dib7000p_set_bandwidth(state, BANDWIDTH_TO_KHZ(ch->u.ofdm.bandwidth));
+ dib7000p_set_bandwidth(state, BANDWIDTH_TO_KHZ(ch->u.ofdm.bandwidth));
/* nfft, guard, qam, alpha */
value = 0;
switch (ch->u.ofdm.transmission_mode) {
- case TRANSMISSION_MODE_2K: value |= (0 << 7); break;
- case TRANSMISSION_MODE_4K: value |= (2 << 7); break;
- default:
- case TRANSMISSION_MODE_8K: value |= (1 << 7); break;
+ case TRANSMISSION_MODE_2K:
+ value |= (0 << 7);
+ break;
+ case TRANSMISSION_MODE_4K:
+ value |= (2 << 7);
+ break;
+ default:
+ case TRANSMISSION_MODE_8K:
+ value |= (1 << 7);
+ break;
}
switch (ch->u.ofdm.guard_interval) {
- case GUARD_INTERVAL_1_32: value |= (0 << 5); break;
- case GUARD_INTERVAL_1_16: value |= (1 << 5); break;
- case GUARD_INTERVAL_1_4: value |= (3 << 5); break;
- default:
- case GUARD_INTERVAL_1_8: value |= (2 << 5); break;
+ case GUARD_INTERVAL_1_32:
+ value |= (0 << 5);
+ break;
+ case GUARD_INTERVAL_1_16:
+ value |= (1 << 5);
+ break;
+ case GUARD_INTERVAL_1_4:
+ value |= (3 << 5);
+ break;
+ default:
+ case GUARD_INTERVAL_1_8:
+ value |= (2 << 5);
+ break;
}
switch (ch->u.ofdm.constellation) {
- case QPSK: value |= (0 << 3); break;
- case QAM_16: value |= (1 << 3); break;
- default:
- case QAM_64: value |= (2 << 3); break;
+ case QPSK:
+ value |= (0 << 3);
+ break;
+ case QAM_16:
+ value |= (1 << 3);
+ break;
+ default:
+ case QAM_64:
+ value |= (2 << 3);
+ break;
}
switch (HIERARCHY_1) {
- case HIERARCHY_2: value |= 2; break;
- case HIERARCHY_4: value |= 4; break;
- default:
- case HIERARCHY_1: value |= 1; break;
+ case HIERARCHY_2:
+ value |= 2;
+ break;
+ case HIERARCHY_4:
+ value |= 4;
+ break;
+ default:
+ case HIERARCHY_1:
+ value |= 1;
+ break;
}
dib7000p_write_word(state, 0, value);
- dib7000p_write_word(state, 5, (seq << 4) | 1); /* do not force tps, search list 0 */
+ dib7000p_write_word(state, 5, (seq << 4) | 1); /* do not force tps, search list 0 */
/* P_dintl_native, P_dintlv_inv, P_hrch, P_code_rate, P_select_hp */
value = 0;
@@ -752,39 +939,63 @@ static void dib7000p_set_channel(struct dib7000p_state *state, struct dvb_fronte
if (1 == 1)
value |= 1;
switch ((ch->u.ofdm.hierarchy_information == 0 || 1 == 1) ? ch->u.ofdm.code_rate_HP : ch->u.ofdm.code_rate_LP) {
- case FEC_2_3: value |= (2 << 1); break;
- case FEC_3_4: value |= (3 << 1); break;
- case FEC_5_6: value |= (5 << 1); break;
- case FEC_7_8: value |= (7 << 1); break;
- default:
- case FEC_1_2: value |= (1 << 1); break;
+ case FEC_2_3:
+ value |= (2 << 1);
+ break;
+ case FEC_3_4:
+ value |= (3 << 1);
+ break;
+ case FEC_5_6:
+ value |= (5 << 1);
+ break;
+ case FEC_7_8:
+ value |= (7 << 1);
+ break;
+ default:
+ case FEC_1_2:
+ value |= (1 << 1);
+ break;
}
dib7000p_write_word(state, 208, value);
/* offset loop parameters */
- dib7000p_write_word(state, 26, 0x6680); // timf(6xxx)
- dib7000p_write_word(state, 32, 0x0003); // pha_off_max(xxx3)
- dib7000p_write_word(state, 29, 0x1273); // isi
- dib7000p_write_word(state, 33, 0x0005); // sfreq(xxx5)
+ dib7000p_write_word(state, 26, 0x6680);
+ dib7000p_write_word(state, 32, 0x0003);
+ dib7000p_write_word(state, 29, 0x1273);
+ dib7000p_write_word(state, 33, 0x0005);
/* P_dvsy_sync_wait */
switch (ch->u.ofdm.transmission_mode) {
- case TRANSMISSION_MODE_8K: value = 256; break;
- case TRANSMISSION_MODE_4K: value = 128; break;
- case TRANSMISSION_MODE_2K:
- default: value = 64; break;
+ case TRANSMISSION_MODE_8K:
+ value = 256;
+ break;
+ case TRANSMISSION_MODE_4K:
+ value = 128;
+ break;
+ case TRANSMISSION_MODE_2K:
+ default:
+ value = 64;
+ break;
}
switch (ch->u.ofdm.guard_interval) {
- case GUARD_INTERVAL_1_16: value *= 2; break;
- case GUARD_INTERVAL_1_8: value *= 4; break;
- case GUARD_INTERVAL_1_4: value *= 8; break;
- default:
- case GUARD_INTERVAL_1_32: value *= 1; break;
+ case GUARD_INTERVAL_1_16:
+ value *= 2;
+ break;
+ case GUARD_INTERVAL_1_8:
+ value *= 4;
+ break;
+ case GUARD_INTERVAL_1_4:
+ value *= 8;
+ break;
+ default:
+ case GUARD_INTERVAL_1_32:
+ value *= 1;
+ break;
}
if (state->cfg.diversity_delay == 0)
- state->div_sync_wait = (value * 3) / 2 + 48; // add 50% SFN margin + compensate for one DVSY-fifo
+ state->div_sync_wait = (value * 3) / 2 + 48;
else
- state->div_sync_wait = (value * 3) / 2 + state->cfg.diversity_delay; // add 50% SFN margin + compensate for one DVSY-fifo
+ state->div_sync_wait = (value * 3) / 2 + state->cfg.diversity_delay;
/* deactive the possibility of diversity reception if extended interleaver */
state->div_force_off = !1 && ch->u.ofdm.transmission_mode != TRANSMISSION_MODE_8K;
@@ -792,24 +1003,24 @@ static void dib7000p_set_channel(struct dib7000p_state *state, struct dvb_fronte
/* channel estimation fine configuration */
switch (ch->u.ofdm.constellation) {
- case QAM_64:
- est[0] = 0x0148; /* P_adp_regul_cnt 0.04 */
- est[1] = 0xfff0; /* P_adp_noise_cnt -0.002 */
- est[2] = 0x00a4; /* P_adp_regul_ext 0.02 */
- est[3] = 0xfff8; /* P_adp_noise_ext -0.001 */
- break;
- case QAM_16:
- est[0] = 0x023d; /* P_adp_regul_cnt 0.07 */
- est[1] = 0xffdf; /* P_adp_noise_cnt -0.004 */
- est[2] = 0x00a4; /* P_adp_regul_ext 0.02 */
- est[3] = 0xfff0; /* P_adp_noise_ext -0.002 */
- break;
- default:
- est[0] = 0x099a; /* P_adp_regul_cnt 0.3 */
- est[1] = 0xffae; /* P_adp_noise_cnt -0.01 */
- est[2] = 0x0333; /* P_adp_regul_ext 0.1 */
- est[3] = 0xfff8; /* P_adp_noise_ext -0.002 */
- break;
+ case QAM_64:
+ est[0] = 0x0148; /* P_adp_regul_cnt 0.04 */
+ est[1] = 0xfff0; /* P_adp_noise_cnt -0.002 */
+ est[2] = 0x00a4; /* P_adp_regul_ext 0.02 */
+ est[3] = 0xfff8; /* P_adp_noise_ext -0.001 */
+ break;
+ case QAM_16:
+ est[0] = 0x023d; /* P_adp_regul_cnt 0.07 */
+ est[1] = 0xffdf; /* P_adp_noise_cnt -0.004 */
+ est[2] = 0x00a4; /* P_adp_regul_ext 0.02 */
+ est[3] = 0xfff0; /* P_adp_noise_ext -0.002 */
+ break;
+ default:
+ est[0] = 0x099a; /* P_adp_regul_cnt 0.3 */
+ est[1] = 0xffae; /* P_adp_noise_cnt -0.01 */
+ est[2] = 0x0333; /* P_adp_regul_ext 0.1 */
+ est[3] = 0xfff8; /* P_adp_noise_ext -0.002 */
+ break;
}
for (value = 0; value < 4; value++)
dib7000p_write_word(state, 187 + value, est[value]);
@@ -820,14 +1031,15 @@ static int dib7000p_autosearch_start(struct dvb_frontend *demod, struct dvb_fron
struct dib7000p_state *state = demod->demodulator_priv;
struct dvb_frontend_parameters schan;
u32 value, factor;
+ u32 internal = dib7000p_get_internal_freq(state);
schan = *ch;
schan.u.ofdm.constellation = QAM_64;
- schan.u.ofdm.guard_interval = GUARD_INTERVAL_1_32;
- schan.u.ofdm.transmission_mode = TRANSMISSION_MODE_8K;
- schan.u.ofdm.code_rate_HP = FEC_2_3;
- schan.u.ofdm.code_rate_LP = FEC_3_4;
- schan.u.ofdm.hierarchy_information = 0;
+ schan.u.ofdm.guard_interval = GUARD_INTERVAL_1_32;
+ schan.u.ofdm.transmission_mode = TRANSMISSION_MODE_8K;
+ schan.u.ofdm.code_rate_HP = FEC_2_3;
+ schan.u.ofdm.code_rate_LP = FEC_3_4;
+ schan.u.ofdm.hierarchy_information = 0;
dib7000p_set_channel(state, &schan, 7);
@@ -837,16 +1049,15 @@ static int dib7000p_autosearch_start(struct dvb_frontend *demod, struct dvb_fron
else
factor = 6;
- // always use the setting for 8MHz here lock_time for 7,6 MHz are longer
- value = 30 * state->cfg.bw->internal * factor;
- dib7000p_write_word(state, 6, (u16) ((value >> 16) & 0xffff)); // lock0 wait time
- dib7000p_write_word(state, 7, (u16) (value & 0xffff)); // lock0 wait time
- value = 100 * state->cfg.bw->internal * factor;
- dib7000p_write_word(state, 8, (u16) ((value >> 16) & 0xffff)); // lock1 wait time
- dib7000p_write_word(state, 9, (u16) (value & 0xffff)); // lock1 wait time
- value = 500 * state->cfg.bw->internal * factor;
- dib7000p_write_word(state, 10, (u16) ((value >> 16) & 0xffff)); // lock2 wait time
- dib7000p_write_word(state, 11, (u16) (value & 0xffff)); // lock2 wait time
+ value = 30 * internal * factor;
+ dib7000p_write_word(state, 6, (u16) ((value >> 16) & 0xffff));
+ dib7000p_write_word(state, 7, (u16) (value & 0xffff));
+ value = 100 * internal * factor;
+ dib7000p_write_word(state, 8, (u16) ((value >> 16) & 0xffff));
+ dib7000p_write_word(state, 9, (u16) (value & 0xffff));
+ value = 500 * internal * factor;
+ dib7000p_write_word(state, 10, (u16) ((value >> 16) & 0xffff));
+ dib7000p_write_word(state, 11, (u16) (value & 0xffff));
value = dib7000p_read_word(state, 0);
dib7000p_write_word(state, 0, (u16) ((1 << 9) | value));
@@ -861,101 +1072,101 @@ static int dib7000p_autosearch_is_irq(struct dvb_frontend *demod)
struct dib7000p_state *state = demod->demodulator_priv;
u16 irq_pending = dib7000p_read_word(state, 1284);
- if (irq_pending & 0x1) // failed
+ if (irq_pending & 0x1)
return 1;
- if (irq_pending & 0x2) // succeeded
+ if (irq_pending & 0x2)
return 2;
- return 0; // still pending
+ return 0;
}
static void dib7000p_spur_protect(struct dib7000p_state *state, u32 rf_khz, u32 bw)
{
- static s16 notch[]={16143, 14402, 12238, 9713, 6902, 3888, 759, -2392};
- static u8 sine [] ={0, 2, 3, 5, 6, 8, 9, 11, 13, 14, 16, 17, 19, 20, 22,
- 24, 25, 27, 28, 30, 31, 33, 34, 36, 38, 39, 41, 42, 44, 45, 47, 48, 50, 51,
- 53, 55, 56, 58, 59, 61, 62, 64, 65, 67, 68, 70, 71, 73, 74, 76, 77, 79, 80,
- 82, 83, 85, 86, 88, 89, 91, 92, 94, 95, 97, 98, 99, 101, 102, 104, 105,
- 107, 108, 109, 111, 112, 114, 115, 117, 118, 119, 121, 122, 123, 125, 126,
- 128, 129, 130, 132, 133, 134, 136, 137, 138, 140, 141, 142, 144, 145, 146,
- 147, 149, 150, 151, 152, 154, 155, 156, 157, 159, 160, 161, 162, 164, 165,
- 166, 167, 168, 170, 171, 172, 173, 174, 175, 177, 178, 179, 180, 181, 182,
- 183, 184, 185, 186, 188, 189, 190, 191, 192, 193, 194, 195, 196, 197, 198,
- 199, 200, 201, 202, 203, 204, 205, 206, 207, 207, 208, 209, 210, 211, 212,
- 213, 214, 215, 215, 216, 217, 218, 219, 220, 220, 221, 222, 223, 224, 224,
- 225, 226, 227, 227, 228, 229, 229, 230, 231, 231, 232, 233, 233, 234, 235,
- 235, 236, 237, 237, 238, 238, 239, 239, 240, 241, 241, 242, 242, 243, 243,
- 244, 244, 245, 245, 245, 246, 246, 247, 247, 248, 248, 248, 249, 249, 249,
- 250, 250, 250, 251, 251, 251, 252, 252, 252, 252, 253, 253, 253, 253, 254,
- 254, 254, 254, 254, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255,
- 255, 255, 255, 255, 255, 255};
+ static s16 notch[] = { 16143, 14402, 12238, 9713, 6902, 3888, 759, -2392 };
+ static u8 sine[] = { 0, 2, 3, 5, 6, 8, 9, 11, 13, 14, 16, 17, 19, 20, 22,
+ 24, 25, 27, 28, 30, 31, 33, 34, 36, 38, 39, 41, 42, 44, 45, 47, 48, 50, 51,
+ 53, 55, 56, 58, 59, 61, 62, 64, 65, 67, 68, 70, 71, 73, 74, 76, 77, 79, 80,
+ 82, 83, 85, 86, 88, 89, 91, 92, 94, 95, 97, 98, 99, 101, 102, 104, 105,
+ 107, 108, 109, 111, 112, 114, 115, 117, 118, 119, 121, 122, 123, 125, 126,
+ 128, 129, 130, 132, 133, 134, 136, 137, 138, 140, 141, 142, 144, 145, 146,
+ 147, 149, 150, 151, 152, 154, 155, 156, 157, 159, 160, 161, 162, 164, 165,
+ 166, 167, 168, 170, 171, 172, 173, 174, 175, 177, 178, 179, 180, 181, 182,
+ 183, 184, 185, 186, 188, 189, 190, 191, 192, 193, 194, 195, 196, 197, 198,
+ 199, 200, 201, 202, 203, 204, 205, 206, 207, 207, 208, 209, 210, 211, 212,
+ 213, 214, 215, 215, 216, 217, 218, 219, 220, 220, 221, 222, 223, 224, 224,
+ 225, 226, 227, 227, 228, 229, 229, 230, 231, 231, 232, 233, 233, 234, 235,
+ 235, 236, 237, 237, 238, 238, 239, 239, 240, 241, 241, 242, 242, 243, 243,
+ 244, 244, 245, 245, 245, 246, 246, 247, 247, 248, 248, 248, 249, 249, 249,
+ 250, 250, 250, 251, 251, 251, 252, 252, 252, 252, 253, 253, 253, 253, 254,
+ 254, 254, 254, 254, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255,
+ 255, 255, 255, 255, 255, 255
+ };
u32 xtal = state->cfg.bw->xtal_hz / 1000;
int f_rel = DIV_ROUND_CLOSEST(rf_khz, xtal) * xtal - rf_khz;
int k;
- int coef_re[8],coef_im[8];
+ int coef_re[8], coef_im[8];
int bw_khz = bw;
u32 pha;
- dprintk( "relative position of the Spur: %dk (RF: %dk, XTAL: %dk)", f_rel, rf_khz, xtal);
-
+ dprintk("relative position of the Spur: %dk (RF: %dk, XTAL: %dk)", f_rel, rf_khz, xtal);
- if (f_rel < -bw_khz/2 || f_rel > bw_khz/2)
+ if (f_rel < -bw_khz / 2 || f_rel > bw_khz / 2)
return;
bw_khz /= 100;
- dib7000p_write_word(state, 142 ,0x0610);
+ dib7000p_write_word(state, 142, 0x0610);
for (k = 0; k < 8; k++) {
- pha = ((f_rel * (k+1) * 112 * 80/bw_khz) /1000) & 0x3ff;
+ pha = ((f_rel * (k + 1) * 112 * 80 / bw_khz) / 1000) & 0x3ff;
- if (pha==0) {
+ if (pha == 0) {
coef_re[k] = 256;
coef_im[k] = 0;
- } else if(pha < 256) {
- coef_re[k] = sine[256-(pha&0xff)];
- coef_im[k] = sine[pha&0xff];
+ } else if (pha < 256) {
+ coef_re[k] = sine[256 - (pha & 0xff)];
+ coef_im[k] = sine[pha & 0xff];
} else if (pha == 256) {
coef_re[k] = 0;
coef_im[k] = 256;
} else if (pha < 512) {
- coef_re[k] = -sine[pha&0xff];
- coef_im[k] = sine[256 - (pha&0xff)];
+ coef_re[k] = -sine[pha & 0xff];
+ coef_im[k] = sine[256 - (pha & 0xff)];
} else if (pha == 512) {
coef_re[k] = -256;
coef_im[k] = 0;
} else if (pha < 768) {
- coef_re[k] = -sine[256-(pha&0xff)];
- coef_im[k] = -sine[pha&0xff];
+ coef_re[k] = -sine[256 - (pha & 0xff)];
+ coef_im[k] = -sine[pha & 0xff];
} else if (pha == 768) {
coef_re[k] = 0;
coef_im[k] = -256;
} else {
- coef_re[k] = sine[pha&0xff];
- coef_im[k] = -sine[256 - (pha&0xff)];
+ coef_re[k] = sine[pha & 0xff];
+ coef_im[k] = -sine[256 - (pha & 0xff)];
}
coef_re[k] *= notch[k];
- coef_re[k] += (1<<14);
- if (coef_re[k] >= (1<<24))
- coef_re[k] = (1<<24) - 1;
- coef_re[k] /= (1<<15);
+ coef_re[k] += (1 << 14);
+ if (coef_re[k] >= (1 << 24))
+ coef_re[k] = (1 << 24) - 1;
+ coef_re[k] /= (1 << 15);
coef_im[k] *= notch[k];
- coef_im[k] += (1<<14);
- if (coef_im[k] >= (1<<24))
- coef_im[k] = (1<<24)-1;
- coef_im[k] /= (1<<15);
+ coef_im[k] += (1 << 14);
+ if (coef_im[k] >= (1 << 24))
+ coef_im[k] = (1 << 24) - 1;
+ coef_im[k] /= (1 << 15);
- dprintk( "PALF COEF: %d re: %d im: %d", k, coef_re[k], coef_im[k]);
+ dprintk("PALF COEF: %d re: %d im: %d", k, coef_re[k], coef_im[k]);
dib7000p_write_word(state, 143, (0 << 14) | (k << 10) | (coef_re[k] & 0x3ff));
dib7000p_write_word(state, 144, coef_im[k] & 0x3ff);
dib7000p_write_word(state, 143, (1 << 14) | (k << 10) | (coef_re[k] & 0x3ff));
}
- dib7000p_write_word(state,143 ,0);
+ dib7000p_write_word(state, 143, 0);
}
static int dib7000p_tune(struct dvb_frontend *demod, struct dvb_frontend_parameters *ch)
@@ -976,11 +1187,11 @@ static int dib7000p_tune(struct dvb_frontend *demod, struct dvb_frontend_paramet
/* P_ctrl_inh_cor=0, P_ctrl_alpha_cor=4, P_ctrl_inh_isi=0, P_ctrl_alpha_isi=3, P_ctrl_inh_cor4=1, P_ctrl_alpha_cor4=3 */
tmp = (0 << 14) | (4 << 10) | (0 << 9) | (3 << 5) | (1 << 4) | (0x3);
if (state->sfn_workaround_active) {
- dprintk( "SFN workaround is active");
+ dprintk("SFN workaround is active");
tmp |= (1 << 9);
- dib7000p_write_word(state, 166, 0x4000); // P_pha3_force_pha_shift
+ dib7000p_write_word(state, 166, 0x4000);
} else {
- dib7000p_write_word(state, 166, 0x0000); // P_pha3_force_pha_shift
+ dib7000p_write_word(state, 166, 0x0000);
}
dib7000p_write_word(state, 29, tmp);
@@ -993,51 +1204,72 @@ static int dib7000p_tune(struct dvb_frontend *demod, struct dvb_frontend_paramet
/* P_timf_alpha, P_corm_alpha=6, P_corm_thres=0x80 */
tmp = (6 << 8) | 0x80;
switch (ch->u.ofdm.transmission_mode) {
- case TRANSMISSION_MODE_2K: tmp |= (7 << 12); break;
- case TRANSMISSION_MODE_4K: tmp |= (8 << 12); break;
- default:
- case TRANSMISSION_MODE_8K: tmp |= (9 << 12); break;
+ case TRANSMISSION_MODE_2K:
+ tmp |= (2 << 12);
+ break;
+ case TRANSMISSION_MODE_4K:
+ tmp |= (3 << 12);
+ break;
+ default:
+ case TRANSMISSION_MODE_8K:
+ tmp |= (4 << 12);
+ break;
}
- dib7000p_write_word(state, 26, tmp); /* timf_a(6xxx) */
+ dib7000p_write_word(state, 26, tmp); /* timf_a(6xxx) */
/* P_ctrl_freeze_pha_shift=0, P_ctrl_pha_off_max */
tmp = (0 << 4);
switch (ch->u.ofdm.transmission_mode) {
- case TRANSMISSION_MODE_2K: tmp |= 0x6; break;
- case TRANSMISSION_MODE_4K: tmp |= 0x7; break;
- default:
- case TRANSMISSION_MODE_8K: tmp |= 0x8; break;
+ case TRANSMISSION_MODE_2K:
+ tmp |= 0x6;
+ break;
+ case TRANSMISSION_MODE_4K:
+ tmp |= 0x7;
+ break;
+ default:
+ case TRANSMISSION_MODE_8K:
+ tmp |= 0x8;
+ break;
}
- dib7000p_write_word(state, 32, tmp);
+ dib7000p_write_word(state, 32, tmp);
/* P_ctrl_sfreq_inh=0, P_ctrl_sfreq_step */
tmp = (0 << 4);
switch (ch->u.ofdm.transmission_mode) {
- case TRANSMISSION_MODE_2K: tmp |= 0x6; break;
- case TRANSMISSION_MODE_4K: tmp |= 0x7; break;
- default:
- case TRANSMISSION_MODE_8K: tmp |= 0x8; break;
+ case TRANSMISSION_MODE_2K:
+ tmp |= 0x6;
+ break;
+ case TRANSMISSION_MODE_4K:
+ tmp |= 0x7;
+ break;
+ default:
+ case TRANSMISSION_MODE_8K:
+ tmp |= 0x8;
+ break;
}
- dib7000p_write_word(state, 33, tmp);
+ dib7000p_write_word(state, 33, tmp);
- tmp = dib7000p_read_word(state,509);
+ tmp = dib7000p_read_word(state, 509);
if (!((tmp >> 6) & 0x1)) {
/* restart the fec */
- tmp = dib7000p_read_word(state,771);
+ tmp = dib7000p_read_word(state, 771);
dib7000p_write_word(state, 771, tmp | (1 << 1));
dib7000p_write_word(state, 771, tmp);
- msleep(10);
- tmp = dib7000p_read_word(state,509);
+ msleep(40);
+ tmp = dib7000p_read_word(state, 509);
}
-
// we achieved a lock - it's time to update the osc freq
- if ((tmp >> 6) & 0x1)
+ if ((tmp >> 6) & 0x1) {
dib7000p_update_timf(state);
+ /* P_timf_alpha += 2 */
+ tmp = dib7000p_read_word(state, 26);
+ dib7000p_write_word(state, 26, (tmp & ~(0xf << 12)) | ((((tmp >> 12) & 0xf) + 5) << 12));
+ }
if (state->cfg.spur_protect)
- dib7000p_spur_protect(state, ch->frequency/1000, BANDWIDTH_TO_KHZ(ch->u.ofdm.bandwidth));
+ dib7000p_spur_protect(state, ch->frequency / 1000, BANDWIDTH_TO_KHZ(ch->u.ofdm.bandwidth));
- dib7000p_set_bandwidth(state, BANDWIDTH_TO_KHZ(ch->u.ofdm.bandwidth));
+ dib7000p_set_bandwidth(state, BANDWIDTH_TO_KHZ(ch->u.ofdm.bandwidth));
return 0;
}
@@ -1046,63 +1278,82 @@ static int dib7000p_wakeup(struct dvb_frontend *demod)
struct dib7000p_state *state = demod->demodulator_priv;
dib7000p_set_power_mode(state, DIB7000P_POWER_ALL);
dib7000p_set_adc_state(state, DIBX000_SLOW_ADC_ON);
+ if (state->version == SOC7090)
+ dib7000p_sad_calib(state);
return 0;
}
static int dib7000p_sleep(struct dvb_frontend *demod)
{
struct dib7000p_state *state = demod->demodulator_priv;
+ if (state->version == SOC7090)
+ return dib7090_set_output_mode(demod, OUTMODE_HIGH_Z) | dib7000p_set_power_mode(state, DIB7000P_POWER_INTERFACE_ONLY);
return dib7000p_set_output_mode(state, OUTMODE_HIGH_Z) | dib7000p_set_power_mode(state, DIB7000P_POWER_INTERFACE_ONLY);
}
static int dib7000p_identify(struct dib7000p_state *st)
{
u16 value;
- dprintk( "checking demod on I2C address: %d (%x)",
- st->i2c_addr, st->i2c_addr);
+ dprintk("checking demod on I2C address: %d (%x)", st->i2c_addr, st->i2c_addr);
if ((value = dib7000p_read_word(st, 768)) != 0x01b3) {
- dprintk( "wrong Vendor ID (read=0x%x)",value);
+ dprintk("wrong Vendor ID (read=0x%x)", value);
return -EREMOTEIO;
}
if ((value = dib7000p_read_word(st, 769)) != 0x4000) {
- dprintk( "wrong Device ID (%x)",value);
+ dprintk("wrong Device ID (%x)", value);
return -EREMOTEIO;
}
return 0;
}
-
-static int dib7000p_get_frontend(struct dvb_frontend* fe,
- struct dvb_frontend_parameters *fep)
+static int dib7000p_get_frontend(struct dvb_frontend *fe, struct dvb_frontend_parameters *fep)
{
struct dib7000p_state *state = fe->demodulator_priv;
- u16 tps = dib7000p_read_word(state,463);
+ u16 tps = dib7000p_read_word(state, 463);
fep->inversion = INVERSION_AUTO;
fep->u.ofdm.bandwidth = BANDWIDTH_TO_INDEX(state->current_bandwidth);
switch ((tps >> 8) & 0x3) {
- case 0: fep->u.ofdm.transmission_mode = TRANSMISSION_MODE_2K; break;
- case 1: fep->u.ofdm.transmission_mode = TRANSMISSION_MODE_8K; break;
- /* case 2: fep->u.ofdm.transmission_mode = TRANSMISSION_MODE_4K; break; */
+ case 0:
+ fep->u.ofdm.transmission_mode = TRANSMISSION_MODE_2K;
+ break;
+ case 1:
+ fep->u.ofdm.transmission_mode = TRANSMISSION_MODE_8K;
+ break;
+ /* case 2: fep->u.ofdm.transmission_mode = TRANSMISSION_MODE_4K; break; */
}
switch (tps & 0x3) {
- case 0: fep->u.ofdm.guard_interval = GUARD_INTERVAL_1_32; break;
- case 1: fep->u.ofdm.guard_interval = GUARD_INTERVAL_1_16; break;
- case 2: fep->u.ofdm.guard_interval = GUARD_INTERVAL_1_8; break;
- case 3: fep->u.ofdm.guard_interval = GUARD_INTERVAL_1_4; break;
+ case 0:
+ fep->u.ofdm.guard_interval = GUARD_INTERVAL_1_32;
+ break;
+ case 1:
+ fep->u.ofdm.guard_interval = GUARD_INTERVAL_1_16;
+ break;
+ case 2:
+ fep->u.ofdm.guard_interval = GUARD_INTERVAL_1_8;
+ break;
+ case 3:
+ fep->u.ofdm.guard_interval = GUARD_INTERVAL_1_4;
+ break;
}
switch ((tps >> 14) & 0x3) {
- case 0: fep->u.ofdm.constellation = QPSK; break;
- case 1: fep->u.ofdm.constellation = QAM_16; break;
- case 2:
- default: fep->u.ofdm.constellation = QAM_64; break;
+ case 0:
+ fep->u.ofdm.constellation = QPSK;
+ break;
+ case 1:
+ fep->u.ofdm.constellation = QAM_16;
+ break;
+ case 2:
+ default:
+ fep->u.ofdm.constellation = QAM_64;
+ break;
}
/* as long as the frontend_param structure is fixed for hierarchical transmission I refuse to use it */
@@ -1110,22 +1361,42 @@ static int dib7000p_get_frontend(struct dvb_frontend* fe,
fep->u.ofdm.hierarchy_information = HIERARCHY_NONE;
switch ((tps >> 5) & 0x7) {
- case 1: fep->u.ofdm.code_rate_HP = FEC_1_2; break;
- case 2: fep->u.ofdm.code_rate_HP = FEC_2_3; break;
- case 3: fep->u.ofdm.code_rate_HP = FEC_3_4; break;
- case 5: fep->u.ofdm.code_rate_HP = FEC_5_6; break;
- case 7:
- default: fep->u.ofdm.code_rate_HP = FEC_7_8; break;
+ case 1:
+ fep->u.ofdm.code_rate_HP = FEC_1_2;
+ break;
+ case 2:
+ fep->u.ofdm.code_rate_HP = FEC_2_3;
+ break;
+ case 3:
+ fep->u.ofdm.code_rate_HP = FEC_3_4;
+ break;
+ case 5:
+ fep->u.ofdm.code_rate_HP = FEC_5_6;
+ break;
+ case 7:
+ default:
+ fep->u.ofdm.code_rate_HP = FEC_7_8;
+ break;
}
switch ((tps >> 2) & 0x7) {
- case 1: fep->u.ofdm.code_rate_LP = FEC_1_2; break;
- case 2: fep->u.ofdm.code_rate_LP = FEC_2_3; break;
- case 3: fep->u.ofdm.code_rate_LP = FEC_3_4; break;
- case 5: fep->u.ofdm.code_rate_LP = FEC_5_6; break;
- case 7:
- default: fep->u.ofdm.code_rate_LP = FEC_7_8; break;
+ case 1:
+ fep->u.ofdm.code_rate_LP = FEC_1_2;
+ break;
+ case 2:
+ fep->u.ofdm.code_rate_LP = FEC_2_3;
+ break;
+ case 3:
+ fep->u.ofdm.code_rate_LP = FEC_3_4;
+ break;
+ case 5:
+ fep->u.ofdm.code_rate_LP = FEC_5_6;
+ break;
+ case 7:
+ default:
+ fep->u.ofdm.code_rate_LP = FEC_7_8;
+ break;
}
/* native interleaver: (dib7000p_read_word(state, 464) >> 5) & 0x1 */
@@ -1133,15 +1404,18 @@ static int dib7000p_get_frontend(struct dvb_frontend* fe,
return 0;
}
-static int dib7000p_set_frontend(struct dvb_frontend* fe,
- struct dvb_frontend_parameters *fep)
+static int dib7000p_set_frontend(struct dvb_frontend *fe, struct dvb_frontend_parameters *fep)
{
struct dib7000p_state *state = fe->demodulator_priv;
int time, ret;
- dib7000p_set_output_mode(state, OUTMODE_HIGH_Z);
+ if (state->version == SOC7090) {
+ dib7090_set_diversity_in(fe, 0);
+ dib7090_set_output_mode(fe, OUTMODE_HIGH_Z);
+ } else
+ dib7000p_set_output_mode(state, OUTMODE_HIGH_Z);
- /* maybe the parameter has been changed */
+ /* maybe the parameter has been changed */
state->sfn_workaround_active = buggy_sfn_workaround;
if (fe->ops.tuner_ops.set_params)
@@ -1156,9 +1430,7 @@ static int dib7000p_set_frontend(struct dvb_frontend* fe,
} while (time != -1);
if (fep->u.ofdm.transmission_mode == TRANSMISSION_MODE_AUTO ||
- fep->u.ofdm.guard_interval == GUARD_INTERVAL_AUTO ||
- fep->u.ofdm.constellation == QAM_AUTO ||
- fep->u.ofdm.code_rate_HP == FEC_AUTO) {
+ fep->u.ofdm.guard_interval == GUARD_INTERVAL_AUTO || fep->u.ofdm.constellation == QAM_AUTO || fep->u.ofdm.code_rate_HP == FEC_AUTO) {
int i = 800, found;
dib7000p_autosearch_start(fe, fep);
@@ -1167,9 +1439,9 @@ static int dib7000p_set_frontend(struct dvb_frontend* fe,
found = dib7000p_autosearch_is_irq(fe);
} while (found == 0 && i--);
- dprintk("autosearch returns: %d",found);
+ dprintk("autosearch returns: %d", found);
if (found == 0 || found == 1)
- return 0; // no channel found
+ return 0;
dib7000p_get_frontend(fe, fep);
}
@@ -1177,11 +1449,15 @@ static int dib7000p_set_frontend(struct dvb_frontend* fe,
ret = dib7000p_tune(fe, fep);
/* make this a config parameter */
- dib7000p_set_output_mode(state, state->cfg.output_mode);
- return ret;
+ if (state->version == SOC7090)
+ dib7090_set_output_mode(fe, state->cfg.output_mode);
+ else
+ dib7000p_set_output_mode(state, state->cfg.output_mode);
+
+ return ret;
}
-static int dib7000p_read_status(struct dvb_frontend *fe, fe_status_t *stat)
+static int dib7000p_read_status(struct dvb_frontend *fe, fe_status_t * stat)
{
struct dib7000p_state *state = fe->demodulator_priv;
u16 lock = dib7000p_read_word(state, 509);
@@ -1196,27 +1472,27 @@ static int dib7000p_read_status(struct dvb_frontend *fe, fe_status_t *stat)
*stat |= FE_HAS_VITERBI;
if (lock & 0x0010)
*stat |= FE_HAS_SYNC;
- if ((lock & 0x0038) == 0x38)
+ if ((lock & 0x0038) == 0x38)
*stat |= FE_HAS_LOCK;
return 0;
}
-static int dib7000p_read_ber(struct dvb_frontend *fe, u32 *ber)
+static int dib7000p_read_ber(struct dvb_frontend *fe, u32 * ber)
{
struct dib7000p_state *state = fe->demodulator_priv;
*ber = (dib7000p_read_word(state, 500) << 16) | dib7000p_read_word(state, 501);
return 0;
}
-static int dib7000p_read_unc_blocks(struct dvb_frontend *fe, u32 *unc)
+static int dib7000p_read_unc_blocks(struct dvb_frontend *fe, u32 * unc)
{
struct dib7000p_state *state = fe->demodulator_priv;
*unc = dib7000p_read_word(state, 506);
return 0;
}
-static int dib7000p_read_signal_strength(struct dvb_frontend *fe, u16 *strength)
+static int dib7000p_read_signal_strength(struct dvb_frontend *fe, u16 * strength)
{
struct dib7000p_state *state = fe->demodulator_priv;
u16 val = dib7000p_read_word(state, 394);
@@ -1224,7 +1500,7 @@ static int dib7000p_read_signal_strength(struct dvb_frontend *fe, u16 *strength)
return 0;
}
-static int dib7000p_read_snr(struct dvb_frontend* fe, u16 *snr)
+static int dib7000p_read_snr(struct dvb_frontend *fe, u16 * snr)
{
struct dib7000p_state *state = fe->demodulator_priv;
u16 val;
@@ -1240,19 +1516,17 @@ static int dib7000p_read_snr(struct dvb_frontend* fe, u16 *snr)
noise_exp -= 0x40;
signal_mant = (val >> 6) & 0xFF;
- signal_exp = (val & 0x3F);
+ signal_exp = (val & 0x3F);
if ((signal_exp & 0x20) != 0)
signal_exp -= 0x40;
if (signal_mant != 0)
- result = intlog10(2) * 10 * signal_exp + 10 *
- intlog10(signal_mant);
+ result = intlog10(2) * 10 * signal_exp + 10 * intlog10(signal_mant);
else
result = intlog10(2) * 10 * signal_exp - 100;
if (noise_mant != 0)
- result -= intlog10(2) * 10 * noise_exp + 10 *
- intlog10(noise_mant);
+ result -= intlog10(2) * 10 * noise_exp + 10 * intlog10(noise_mant);
else
result -= intlog10(2) * 10 * noise_exp - 100;
@@ -1260,7 +1534,7 @@ static int dib7000p_read_snr(struct dvb_frontend* fe, u16 *snr)
return 0;
}
-static int dib7000p_fe_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings *tune)
+static int dib7000p_fe_get_tune_settings(struct dvb_frontend *fe, struct dvb_frontend_tune_settings *tune)
{
tune->min_delay_ms = 1000;
return 0;
@@ -1270,6 +1544,7 @@ static void dib7000p_release(struct dvb_frontend *demod)
{
struct dib7000p_state *st = demod->demodulator_priv;
dibx000_exit_i2c_master(&st->i2c_master);
+ i2c_del_adapter(&st->dib7090_tuner_adap);
kfree(st);
}
@@ -1277,8 +1552,8 @@ int dib7000pc_detection(struct i2c_adapter *i2c_adap)
{
u8 tx[2], rx[2];
struct i2c_msg msg[2] = {
- { .addr = 18 >> 1, .flags = 0, .buf = tx, .len = 2 },
- { .addr = 18 >> 1, .flags = I2C_M_RD, .buf = rx, .len = 2 },
+ {.addr = 18 >> 1, .flags = 0, .buf = tx, .len = 2},
+ {.addr = 18 >> 1, .flags = I2C_M_RD, .buf = rx, .len = 2},
};
tx[0] = 0x03;
@@ -1303,7 +1578,7 @@ int dib7000pc_detection(struct i2c_adapter *i2c_adap)
}
EXPORT_SYMBOL(dib7000pc_detection);
-struct i2c_adapter * dib7000p_get_i2c_master(struct dvb_frontend *demod, enum dibx000_i2c_interface intf, int gating)
+struct i2c_adapter *dib7000p_get_i2c_master(struct dvb_frontend *demod, enum dibx000_i2c_interface intf, int gating)
{
struct dib7000p_state *st = demod->demodulator_priv;
return dibx000_get_i2c_adapter(&st->i2c_master, intf, gating);
@@ -1312,19 +1587,19 @@ EXPORT_SYMBOL(dib7000p_get_i2c_master);
int dib7000p_pid_filter_ctrl(struct dvb_frontend *fe, u8 onoff)
{
- struct dib7000p_state *state = fe->demodulator_priv;
- u16 val = dib7000p_read_word(state, 235) & 0xffef;
- val |= (onoff & 0x1) << 4;
- dprintk("PID filter enabled %d", onoff);
- return dib7000p_write_word(state, 235, val);
+ struct dib7000p_state *state = fe->demodulator_priv;
+ u16 val = dib7000p_read_word(state, 235) & 0xffef;
+ val |= (onoff & 0x1) << 4;
+ dprintk("PID filter enabled %d", onoff);
+ return dib7000p_write_word(state, 235, val);
}
EXPORT_SYMBOL(dib7000p_pid_filter_ctrl);
int dib7000p_pid_filter(struct dvb_frontend *fe, u8 id, u16 pid, u8 onoff)
{
- struct dib7000p_state *state = fe->demodulator_priv;
- dprintk("PID filter: index %x, PID %d, OnOff %d", id, pid, onoff);
- return dib7000p_write_word(state, 241 + id, onoff ? (1 << 13) | pid : 0);
+ struct dib7000p_state *state = fe->demodulator_priv;
+ dprintk("PID filter: index %x, PID %d, OnOff %d", id, pid, onoff);
+ return dib7000p_write_word(state, 241 + id, onoff ? (1 << 13) | pid : 0);
}
EXPORT_SYMBOL(dib7000p_pid_filter);
@@ -1340,16 +1615,19 @@ int dib7000p_i2c_enumeration(struct i2c_adapter *i2c, int no_of_demods, u8 defau
dpst->i2c_adap = i2c;
- for (k = no_of_demods-1; k >= 0; k--) {
+ for (k = no_of_demods - 1; k >= 0; k--) {
dpst->cfg = cfg[k];
/* designated i2c address */
- new_addr = (0x40 + k) << 1;
+ if (cfg[k].default_i2c_addr != 0)
+ new_addr = cfg[k].default_i2c_addr + (k << 1);
+ else
+ new_addr = (0x40 + k) << 1;
dpst->i2c_addr = new_addr;
- dib7000p_write_word(dpst, 1287, 0x0003); /* sram lead in, rdy */
+ dib7000p_write_word(dpst, 1287, 0x0003); /* sram lead in, rdy */
if (dib7000p_identify(dpst) != 0) {
dpst->i2c_addr = default_addr;
- dib7000p_write_word(dpst, 1287, 0x0003); /* sram lead in, rdy */
+ dib7000p_write_word(dpst, 1287, 0x0003); /* sram lead in, rdy */
if (dib7000p_identify(dpst) != 0) {
dprintk("DiB7000P #%d: not identified\n", k);
kfree(dpst);
@@ -1368,7 +1646,10 @@ int dib7000p_i2c_enumeration(struct i2c_adapter *i2c, int no_of_demods, u8 defau
for (k = 0; k < no_of_demods; k++) {
dpst->cfg = cfg[k];
- dpst->i2c_addr = (0x40 + k) << 1;
+ if (cfg[k].default_i2c_addr != 0)
+ dpst->i2c_addr = (cfg[k].default_i2c_addr + k) << 1;
+ else
+ dpst->i2c_addr = (0x40 + k) << 1;
// unforce divstr
dib7000p_write_word(dpst, 1285, dpst->i2c_addr << 2);
@@ -1382,8 +1663,613 @@ int dib7000p_i2c_enumeration(struct i2c_adapter *i2c, int no_of_demods, u8 defau
}
EXPORT_SYMBOL(dib7000p_i2c_enumeration);
+static const s32 lut_1000ln_mant[] = {
+ 6908, 6956, 7003, 7047, 7090, 7131, 7170, 7208, 7244, 7279, 7313, 7346, 7377, 7408, 7438, 7467, 7495, 7523, 7549, 7575, 7600
+};
+
+static s32 dib7000p_get_adc_power(struct dvb_frontend *fe)
+{
+ struct dib7000p_state *state = fe->demodulator_priv;
+ u32 tmp_val = 0, exp = 0, mant = 0;
+ s32 pow_i;
+ u16 buf[2];
+ u8 ix = 0;
+
+ buf[0] = dib7000p_read_word(state, 0x184);
+ buf[1] = dib7000p_read_word(state, 0x185);
+ pow_i = (buf[0] << 16) | buf[1];
+ dprintk("raw pow_i = %d", pow_i);
+
+ tmp_val = pow_i;
+ while (tmp_val >>= 1)
+ exp++;
+
+ mant = (pow_i * 1000 / (1 << exp));
+ dprintk(" mant = %d exp = %d", mant / 1000, exp);
+
+ ix = (u8) ((mant - 1000) / 100); /* index of the LUT */
+ dprintk(" ix = %d", ix);
+
+ pow_i = (lut_1000ln_mant[ix] + 693 * (exp - 20) - 6908);
+ pow_i = (pow_i << 8) / 1000;
+ dprintk(" pow_i = %d", pow_i);
+
+ return pow_i;
+}
+
+static int map_addr_to_serpar_number(struct i2c_msg *msg)
+{
+ if ((msg->buf[0] <= 15))
+ msg->buf[0] -= 1;
+ else if (msg->buf[0] == 17)
+ msg->buf[0] = 15;
+ else if (msg->buf[0] == 16)
+ msg->buf[0] = 17;
+ else if (msg->buf[0] == 19)
+ msg->buf[0] = 16;
+ else if (msg->buf[0] >= 21 && msg->buf[0] <= 25)
+ msg->buf[0] -= 3;
+ else if (msg->buf[0] == 28)
+ msg->buf[0] = 23;
+ else
+ return -EINVAL;
+ return 0;
+}
+
+static int w7090p_tuner_write_serpar(struct i2c_adapter *i2c_adap, struct i2c_msg msg[], int num)
+{
+ struct dib7000p_state *state = i2c_get_adapdata(i2c_adap);
+ u8 n_overflow = 1;
+ u16 i = 1000;
+ u16 serpar_num = msg[0].buf[0];
+
+ while (n_overflow == 1 && i) {
+ n_overflow = (dib7000p_read_word(state, 1984) >> 1) & 0x1;
+ i--;
+ if (i == 0)
+ dprintk("Tuner ITF: write busy (overflow)");
+ }
+ dib7000p_write_word(state, 1985, (1 << 6) | (serpar_num & 0x3f));
+ dib7000p_write_word(state, 1986, (msg[0].buf[1] << 8) | msg[0].buf[2]);
+
+ return num;
+}
+
+static int w7090p_tuner_read_serpar(struct i2c_adapter *i2c_adap, struct i2c_msg msg[], int num)
+{
+ struct dib7000p_state *state = i2c_get_adapdata(i2c_adap);
+ u8 n_overflow = 1, n_empty = 1;
+ u16 i = 1000;
+ u16 serpar_num = msg[0].buf[0];
+ u16 read_word;
+
+ while (n_overflow == 1 && i) {
+ n_overflow = (dib7000p_read_word(state, 1984) >> 1) & 0x1;
+ i--;
+ if (i == 0)
+ dprintk("TunerITF: read busy (overflow)");
+ }
+ dib7000p_write_word(state, 1985, (0 << 6) | (serpar_num & 0x3f));
+
+ i = 1000;
+ while (n_empty == 1 && i) {
+ n_empty = dib7000p_read_word(state, 1984) & 0x1;
+ i--;
+ if (i == 0)
+ dprintk("TunerITF: read busy (empty)");
+ }
+ read_word = dib7000p_read_word(state, 1987);
+ msg[1].buf[0] = (read_word >> 8) & 0xff;
+ msg[1].buf[1] = (read_word) & 0xff;
+
+ return num;
+}
+
+static int w7090p_tuner_rw_serpar(struct i2c_adapter *i2c_adap, struct i2c_msg msg[], int num)
+{
+ if (map_addr_to_serpar_number(&msg[0]) == 0) { /* else = Tuner regs to ignore : DIG_CFG, CTRL_RF_LT, PLL_CFG, PWM1_REG, ADCCLK, DIG_CFG_3; SLEEP_EN... */
+ if (num == 1) { /* write */
+ return w7090p_tuner_write_serpar(i2c_adap, msg, 1);
+ } else { /* read */
+ return w7090p_tuner_read_serpar(i2c_adap, msg, 2);
+ }
+ }
+ return num;
+}
+
+int dib7090p_rw_on_apb(struct i2c_adapter *i2c_adap, struct i2c_msg msg[], int num, u16 apb_address)
+{
+ struct dib7000p_state *state = i2c_get_adapdata(i2c_adap);
+ u16 word;
+
+ if (num == 1) { /* write */
+ dib7000p_write_word(state, apb_address, ((msg[0].buf[1] << 8) | (msg[0].buf[2])));
+ } else {
+ word = dib7000p_read_word(state, apb_address);
+ msg[1].buf[0] = (word >> 8) & 0xff;
+ msg[1].buf[1] = (word) & 0xff;
+ }
+
+ return num;
+}
+
+static int dib7090_tuner_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg msg[], int num)
+{
+ struct dib7000p_state *state = i2c_get_adapdata(i2c_adap);
+
+ u16 apb_address = 0, word;
+ int i = 0;
+ switch (msg[0].buf[0]) {
+ case 0x12:
+ apb_address = 1920;
+ break;
+ case 0x14:
+ apb_address = 1921;
+ break;
+ case 0x24:
+ apb_address = 1922;
+ break;
+ case 0x1a:
+ apb_address = 1923;
+ break;
+ case 0x22:
+ apb_address = 1924;
+ break;
+ case 0x33:
+ apb_address = 1926;
+ break;
+ case 0x34:
+ apb_address = 1927;
+ break;
+ case 0x35:
+ apb_address = 1928;
+ break;
+ case 0x36:
+ apb_address = 1929;
+ break;
+ case 0x37:
+ apb_address = 1930;
+ break;
+ case 0x38:
+ apb_address = 1931;
+ break;
+ case 0x39:
+ apb_address = 1932;
+ break;
+ case 0x2a:
+ apb_address = 1935;
+ break;
+ case 0x2b:
+ apb_address = 1936;
+ break;
+ case 0x2c:
+ apb_address = 1937;
+ break;
+ case 0x2d:
+ apb_address = 1938;
+ break;
+ case 0x2e:
+ apb_address = 1939;
+ break;
+ case 0x2f:
+ apb_address = 1940;
+ break;
+ case 0x30:
+ apb_address = 1941;
+ break;
+ case 0x31:
+ apb_address = 1942;
+ break;
+ case 0x32:
+ apb_address = 1943;
+ break;
+ case 0x3e:
+ apb_address = 1944;
+ break;
+ case 0x3f:
+ apb_address = 1945;
+ break;
+ case 0x40:
+ apb_address = 1948;
+ break;
+ case 0x25:
+ apb_address = 914;
+ break;
+ case 0x26:
+ apb_address = 915;
+ break;
+ case 0x27:
+ apb_address = 916;
+ break;
+ case 0x28:
+ apb_address = 917;
+ break;
+ case 0x1d:
+ i = ((dib7000p_read_word(state, 72) >> 12) & 0x3);
+ word = dib7000p_read_word(state, 384 + i);
+ msg[1].buf[0] = (word >> 8) & 0xff;
+ msg[1].buf[1] = (word) & 0xff;
+ return num;
+ case 0x1f:
+ if (num == 1) { /* write */
+ word = (u16) ((msg[0].buf[1] << 8) | msg[0].buf[2]);
+ word &= 0x3;
+ word = (dib7000p_read_word(state, 72) & ~(3 << 12)) | (word << 12);
+ dib7000p_write_word(state, 72, word); /* Set the proper input */
+ return num;
+ }
+ }
+
+ if (apb_address != 0) /* R/W acces via APB */
+ return dib7090p_rw_on_apb(i2c_adap, msg, num, apb_address);
+ else /* R/W access via SERPAR */
+ return w7090p_tuner_rw_serpar(i2c_adap, msg, num);
+
+ return 0;
+}
+
+static u32 dib7000p_i2c_func(struct i2c_adapter *adapter)
+{
+ return I2C_FUNC_I2C;
+}
+
+static struct i2c_algorithm dib7090_tuner_xfer_algo = {
+ .master_xfer = dib7090_tuner_xfer,
+ .functionality = dib7000p_i2c_func,
+};
+
+struct i2c_adapter *dib7090_get_i2c_tuner(struct dvb_frontend *fe)
+{
+ struct dib7000p_state *st = fe->demodulator_priv;
+ return &st->dib7090_tuner_adap;
+}
+EXPORT_SYMBOL(dib7090_get_i2c_tuner);
+
+static int dib7090_host_bus_drive(struct dib7000p_state *state, u8 drive)
+{
+ u16 reg;
+
+ /* drive host bus 2, 3, 4 */
+ reg = dib7000p_read_word(state, 1798) & ~((0x7) | (0x7 << 6) | (0x7 << 12));
+ reg |= (drive << 12) | (drive << 6) | drive;
+ dib7000p_write_word(state, 1798, reg);
+
+ /* drive host bus 5,6 */
+ reg = dib7000p_read_word(state, 1799) & ~((0x7 << 2) | (0x7 << 8));
+ reg |= (drive << 8) | (drive << 2);
+ dib7000p_write_word(state, 1799, reg);
+
+ /* drive host bus 7, 8, 9 */
+ reg = dib7000p_read_word(state, 1800) & ~((0x7) | (0x7 << 6) | (0x7 << 12));
+ reg |= (drive << 12) | (drive << 6) | drive;
+ dib7000p_write_word(state, 1800, reg);
+
+ /* drive host bus 10, 11 */
+ reg = dib7000p_read_word(state, 1801) & ~((0x7 << 2) | (0x7 << 8));
+ reg |= (drive << 8) | (drive << 2);
+ dib7000p_write_word(state, 1801, reg);
+
+ /* drive host bus 12, 13, 14 */
+ reg = dib7000p_read_word(state, 1802) & ~((0x7) | (0x7 << 6) | (0x7 << 12));
+ reg |= (drive << 12) | (drive << 6) | drive;
+ dib7000p_write_word(state, 1802, reg);
+
+ return 0;
+}
+
+static u32 dib7090_calcSyncFreq(u32 P_Kin, u32 P_Kout, u32 insertExtSynchro, u32 syncSize)
+{
+ u32 quantif = 3;
+ u32 nom = (insertExtSynchro * P_Kin + syncSize);
+ u32 denom = P_Kout;
+ u32 syncFreq = ((nom << quantif) / denom);
+
+ if ((syncFreq & ((1 << quantif) - 1)) != 0)
+ syncFreq = (syncFreq >> quantif) + 1;
+ else
+ syncFreq = (syncFreq >> quantif);
+
+ if (syncFreq != 0)
+ syncFreq = syncFreq - 1;
+
+ return syncFreq;
+}
+
+static int dib7090_cfg_DibTx(struct dib7000p_state *state, u32 P_Kin, u32 P_Kout, u32 insertExtSynchro, u32 synchroMode, u32 syncWord, u32 syncSize)
+{
+ u8 index_buf;
+ u16 rx_copy_buf[22];
+
+ dprintk("Configure DibStream Tx");
+ for (index_buf = 0; index_buf < 22; index_buf++)
+ rx_copy_buf[index_buf] = dib7000p_read_word(state, 1536+index_buf);
+
+ dib7000p_write_word(state, 1615, 1);
+ dib7000p_write_word(state, 1603, P_Kin);
+ dib7000p_write_word(state, 1605, P_Kout);
+ dib7000p_write_word(state, 1606, insertExtSynchro);
+ dib7000p_write_word(state, 1608, synchroMode);
+ dib7000p_write_word(state, 1609, (syncWord >> 16) & 0xffff);
+ dib7000p_write_word(state, 1610, syncWord & 0xffff);
+ dib7000p_write_word(state, 1612, syncSize);
+ dib7000p_write_word(state, 1615, 0);
+
+ for (index_buf = 0; index_buf < 22; index_buf++)
+ dib7000p_write_word(state, 1536+index_buf, rx_copy_buf[index_buf]);
+
+ return 0;
+}
+
+static int dib7090_cfg_DibRx(struct dib7000p_state *state, u32 P_Kin, u32 P_Kout, u32 synchroMode, u32 insertExtSynchro, u32 syncWord, u32 syncSize,
+ u32 dataOutRate)
+{
+ u32 syncFreq;
+
+ dprintk("Configure DibStream Rx");
+ if ((P_Kin != 0) && (P_Kout != 0)) {
+ syncFreq = dib7090_calcSyncFreq(P_Kin, P_Kout, insertExtSynchro, syncSize);
+ dib7000p_write_word(state, 1542, syncFreq);
+ }
+ dib7000p_write_word(state, 1554, 1);
+ dib7000p_write_word(state, 1536, P_Kin);
+ dib7000p_write_word(state, 1537, P_Kout);
+ dib7000p_write_word(state, 1539, synchroMode);
+ dib7000p_write_word(state, 1540, (syncWord >> 16) & 0xffff);
+ dib7000p_write_word(state, 1541, syncWord & 0xffff);
+ dib7000p_write_word(state, 1543, syncSize);
+ dib7000p_write_word(state, 1544, dataOutRate);
+ dib7000p_write_word(state, 1554, 0);
+
+ return 0;
+}
+
+static int dib7090_enDivOnHostBus(struct dib7000p_state *state)
+{
+ u16 reg;
+
+ dprintk("Enable Diversity on host bus");
+ reg = (1 << 8) | (1 << 5);
+ dib7000p_write_word(state, 1288, reg);
+
+ return dib7090_cfg_DibTx(state, 5, 5, 0, 0, 0, 0);
+}
+
+static int dib7090_enAdcOnHostBus(struct dib7000p_state *state)
+{
+ u16 reg;
+
+ dprintk("Enable ADC on host bus");
+ reg = (1 << 7) | (1 << 5);
+ dib7000p_write_word(state, 1288, reg);
+
+ return dib7090_cfg_DibTx(state, 20, 5, 10, 0, 0, 0);
+}
+
+static int dib7090_enMpegOnHostBus(struct dib7000p_state *state)
+{
+ u16 reg;
+
+ dprintk("Enable Mpeg on host bus");
+ reg = (1 << 9) | (1 << 5);
+ dib7000p_write_word(state, 1288, reg);
+
+ return dib7090_cfg_DibTx(state, 8, 5, 0, 0, 0, 0);
+}
+
+static int dib7090_enMpegInput(struct dib7000p_state *state)
+{
+ dprintk("Enable Mpeg input");
+ return dib7090_cfg_DibRx(state, 8, 5, 0, 0, 0, 8, 0); /*outputRate = 8 */
+}
+
+static int dib7090_enMpegMux(struct dib7000p_state *state, u16 pulseWidth, u16 enSerialMode, u16 enSerialClkDiv2)
+{
+ u16 reg = (1 << 7) | ((pulseWidth & 0x1f) << 2) | ((enSerialMode & 0x1) << 1) | (enSerialClkDiv2 & 0x1);
+
+ dprintk("Enable Mpeg mux");
+ dib7000p_write_word(state, 1287, reg);
+
+ reg &= ~(1 << 7);
+ dib7000p_write_word(state, 1287, reg);
+
+ reg = (1 << 4);
+ dib7000p_write_word(state, 1288, reg);
+
+ return 0;
+}
+
+static int dib7090_disableMpegMux(struct dib7000p_state *state)
+{
+ u16 reg;
+
+ dprintk("Disable Mpeg mux");
+ dib7000p_write_word(state, 1288, 0);
+
+ reg = dib7000p_read_word(state, 1287);
+ reg &= ~(1 << 7);
+ dib7000p_write_word(state, 1287, reg);
+
+ return 0;
+}
+
+static int dib7090_set_input_mode(struct dvb_frontend *fe, int mode)
+{
+ struct dib7000p_state *state = fe->demodulator_priv;
+
+ switch (mode) {
+ case INPUT_MODE_DIVERSITY:
+ dprintk("Enable diversity INPUT");
+ dib7090_cfg_DibRx(state, 5, 5, 0, 0, 0, 0, 0);
+ break;
+ case INPUT_MODE_MPEG:
+ dprintk("Enable Mpeg INPUT");
+ dib7090_cfg_DibRx(state, 8, 5, 0, 0, 0, 8, 0); /*outputRate = 8 */
+ break;
+ case INPUT_MODE_OFF:
+ default:
+ dprintk("Disable INPUT");
+ dib7090_cfg_DibRx(state, 0, 0, 0, 0, 0, 0, 0);
+ break;
+ }
+ return 0;
+}
+
+static int dib7090_set_diversity_in(struct dvb_frontend *fe, int onoff)
+{
+ switch (onoff) {
+ case 0: /* only use the internal way - not the diversity input */
+ dib7090_set_input_mode(fe, INPUT_MODE_MPEG);
+ break;
+ case 1: /* both ways */
+ case 2: /* only the diversity input */
+ dib7090_set_input_mode(fe, INPUT_MODE_DIVERSITY);
+ break;
+ }
+
+ return 0;
+}
+
+static int dib7090_set_output_mode(struct dvb_frontend *fe, int mode)
+{
+ struct dib7000p_state *state = fe->demodulator_priv;
+
+ u16 outreg, smo_mode, fifo_threshold;
+ u8 prefer_mpeg_mux_use = 1;
+ int ret = 0;
+
+ dib7090_host_bus_drive(state, 1);
+
+ fifo_threshold = 1792;
+ smo_mode = (dib7000p_read_word(state, 235) & 0x0050) | (1 << 1);
+ outreg = dib7000p_read_word(state, 1286) & ~((1 << 10) | (0x7 << 6) | (1 << 1));
+
+ switch (mode) {
+ case OUTMODE_HIGH_Z:
+ outreg = 0;
+ break;
+
+ case OUTMODE_MPEG2_SERIAL:
+ if (prefer_mpeg_mux_use) {
+ dprintk("Sip 7090P setting output mode TS_SERIAL using Mpeg Mux");
+ dib7090_enMpegOnHostBus(state);
+ dib7090_enMpegInput(state);
+ if (state->cfg.enMpegOutput == 1)
+ dib7090_enMpegMux(state, 3, 1, 1);
+
+ } else { /* Use Smooth block */
+ dprintk("Sip 7090P setting output mode TS_SERIAL using Smooth bloc");
+ dib7090_disableMpegMux(state);
+ dib7000p_write_word(state, 1288, (1 << 6));
+ outreg |= (2 << 6) | (0 << 1);
+ }
+ break;
+
+ case OUTMODE_MPEG2_PAR_GATED_CLK:
+ if (prefer_mpeg_mux_use) {
+ dprintk("Sip 7090P setting output mode TS_PARALLEL_GATED using Mpeg Mux");
+ dib7090_enMpegOnHostBus(state);
+ dib7090_enMpegInput(state);
+ if (state->cfg.enMpegOutput == 1)
+ dib7090_enMpegMux(state, 2, 0, 0);
+ } else { /* Use Smooth block */
+ dprintk("Sip 7090P setting output mode TS_PARALLEL_GATED using Smooth block");
+ dib7090_disableMpegMux(state);
+ dib7000p_write_word(state, 1288, (1 << 6));
+ outreg |= (0 << 6);
+ }
+ break;
+
+ case OUTMODE_MPEG2_PAR_CONT_CLK: /* Using Smooth block only */
+ dprintk("Sip 7090P setting output mode TS_PARALLEL_CONT using Smooth block");
+ dib7090_disableMpegMux(state);
+ dib7000p_write_word(state, 1288, (1 << 6));
+ outreg |= (1 << 6);
+ break;
+
+ case OUTMODE_MPEG2_FIFO: /* Using Smooth block because not supported by new Mpeg Mux bloc */
+ dprintk("Sip 7090P setting output mode TS_FIFO using Smooth block");
+ dib7090_disableMpegMux(state);
+ dib7000p_write_word(state, 1288, (1 << 6));
+ outreg |= (5 << 6);
+ smo_mode |= (3 << 1);
+ fifo_threshold = 512;
+ break;
+
+ case OUTMODE_DIVERSITY:
+ dprintk("Sip 7090P setting output mode MODE_DIVERSITY");
+ dib7090_disableMpegMux(state);
+ dib7090_enDivOnHostBus(state);
+ break;
+
+ case OUTMODE_ANALOG_ADC:
+ dprintk("Sip 7090P setting output mode MODE_ANALOG_ADC");
+ dib7090_enAdcOnHostBus(state);
+ break;
+ }
+
+ if (state->cfg.output_mpeg2_in_188_bytes)
+ smo_mode |= (1 << 5);
+
+ ret |= dib7000p_write_word(state, 235, smo_mode);
+ ret |= dib7000p_write_word(state, 236, fifo_threshold); /* synchronous fread */
+ ret |= dib7000p_write_word(state, 1286, outreg | (1 << 10)); /* allways set Dout active = 1 !!! */
+
+ return ret;
+}
+
+int dib7090_tuner_sleep(struct dvb_frontend *fe, int onoff)
+{
+ struct dib7000p_state *state = fe->demodulator_priv;
+ u16 en_cur_state;
+
+ dprintk("sleep dib7090: %d", onoff);
+
+ en_cur_state = dib7000p_read_word(state, 1922);
+
+ if (en_cur_state > 0xff)
+ state->tuner_enable = en_cur_state;
+
+ if (onoff)
+ en_cur_state &= 0x00ff;
+ else {
+ if (state->tuner_enable != 0)
+ en_cur_state = state->tuner_enable;
+ }
+
+ dib7000p_write_word(state, 1922, en_cur_state);
+
+ return 0;
+}
+EXPORT_SYMBOL(dib7090_tuner_sleep);
+
+int dib7090_agc_restart(struct dvb_frontend *fe, u8 restart)
+{
+ dprintk("AGC restart callback: %d", restart);
+ return 0;
+}
+EXPORT_SYMBOL(dib7090_agc_restart);
+
+int dib7090_get_adc_power(struct dvb_frontend *fe)
+{
+ return dib7000p_get_adc_power(fe);
+}
+EXPORT_SYMBOL(dib7090_get_adc_power);
+
+int dib7090_slave_reset(struct dvb_frontend *fe)
+{
+ struct dib7000p_state *state = fe->demodulator_priv;
+ u16 reg;
+
+ reg = dib7000p_read_word(state, 1794);
+ dib7000p_write_word(state, 1794, reg | (4 << 12));
+
+ dib7000p_write_word(state, 1032, 0xffff);
+ return 0;
+}
+EXPORT_SYMBOL(dib7090_slave_reset);
+
static struct dvb_frontend_ops dib7000p_ops;
-struct dvb_frontend * dib7000p_attach(struct i2c_adapter *i2c_adap, u8 i2c_addr, struct dib7000p_config *cfg)
+struct dvb_frontend *dib7000p_attach(struct i2c_adapter *i2c_adap, u8 i2c_addr, struct dib7000p_config *cfg)
{
struct dvb_frontend *demod;
struct dib7000p_state *st;
@@ -1400,28 +2286,41 @@ struct dvb_frontend * dib7000p_attach(struct i2c_adapter *i2c_adap, u8 i2c_addr,
/* Ensure the output mode remains at the previous default if it's
* not specifically set by the caller.
*/
- if ((st->cfg.output_mode != OUTMODE_MPEG2_SERIAL) &&
- (st->cfg.output_mode != OUTMODE_MPEG2_PAR_GATED_CLK))
+ if ((st->cfg.output_mode != OUTMODE_MPEG2_SERIAL) && (st->cfg.output_mode != OUTMODE_MPEG2_PAR_GATED_CLK))
st->cfg.output_mode = OUTMODE_MPEG2_FIFO;
- demod = &st->demod;
+ demod = &st->demod;
demod->demodulator_priv = st;
memcpy(&st->demod.ops, &dib7000p_ops, sizeof(struct dvb_frontend_ops));
- dib7000p_write_word(st, 1287, 0x0003); /* sram lead in, rdy */
+ dib7000p_write_word(st, 1287, 0x0003); /* sram lead in, rdy */
if (dib7000p_identify(st) != 0)
goto error;
+ st->version = dib7000p_read_word(st, 897);
+
/* FIXME: make sure the dev.parent field is initialized, or else
- request_firmware() will hit an OOPS (this should be moved somewhere
- more common) */
- st->i2c_master.gated_tuner_i2c_adap.dev.parent = i2c_adap->dev.parent;
+ request_firmware() will hit an OOPS (this should be moved somewhere
+ more common) */
dibx000_init_i2c_master(&st->i2c_master, DIB7000P, st->i2c_adap, st->i2c_addr);
+ /* init 7090 tuner adapter */
+ strncpy(st->dib7090_tuner_adap.name, "DiB7090 tuner interface", sizeof(st->dib7090_tuner_adap.name));
+ st->dib7090_tuner_adap.algo = &dib7090_tuner_xfer_algo;
+ st->dib7090_tuner_adap.algo_data = NULL;
+ st->dib7090_tuner_adap.dev.parent = st->i2c_adap->dev.parent;
+ i2c_set_adapdata(&st->dib7090_tuner_adap, st);
+ i2c_add_adapter(&st->dib7090_tuner_adap);
+
dib7000p_demod_reset(st);
+ if (st->version == SOC7090) {
+ dib7090_set_output_mode(demod, st->cfg.output_mode);
+ dib7090_set_diversity_in(demod, 0);
+ }
+
return demod;
error:
@@ -1432,37 +2331,35 @@ EXPORT_SYMBOL(dib7000p_attach);
static struct dvb_frontend_ops dib7000p_ops = {
.info = {
- .name = "DiBcom 7000PC",
- .type = FE_OFDM,
- .frequency_min = 44250000,
- .frequency_max = 867250000,
- .frequency_stepsize = 62500,
- .caps = FE_CAN_INVERSION_AUTO |
- FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
- FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
- FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
- FE_CAN_TRANSMISSION_MODE_AUTO |
- FE_CAN_GUARD_INTERVAL_AUTO |
- FE_CAN_RECOVER |
- FE_CAN_HIERARCHY_AUTO,
- },
-
- .release = dib7000p_release,
-
- .init = dib7000p_wakeup,
- .sleep = dib7000p_sleep,
-
- .set_frontend = dib7000p_set_frontend,
- .get_tune_settings = dib7000p_fe_get_tune_settings,
- .get_frontend = dib7000p_get_frontend,
-
- .read_status = dib7000p_read_status,
- .read_ber = dib7000p_read_ber,
+ .name = "DiBcom 7000PC",
+ .type = FE_OFDM,
+ .frequency_min = 44250000,
+ .frequency_max = 867250000,
+ .frequency_stepsize = 62500,
+ .caps = FE_CAN_INVERSION_AUTO |
+ FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
+ FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
+ FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
+ FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_RECOVER | FE_CAN_HIERARCHY_AUTO,
+ },
+
+ .release = dib7000p_release,
+
+ .init = dib7000p_wakeup,
+ .sleep = dib7000p_sleep,
+
+ .set_frontend = dib7000p_set_frontend,
+ .get_tune_settings = dib7000p_fe_get_tune_settings,
+ .get_frontend = dib7000p_get_frontend,
+
+ .read_status = dib7000p_read_status,
+ .read_ber = dib7000p_read_ber,
.read_signal_strength = dib7000p_read_signal_strength,
- .read_snr = dib7000p_read_snr,
- .read_ucblocks = dib7000p_read_unc_blocks,
+ .read_snr = dib7000p_read_snr,
+ .read_ucblocks = dib7000p_read_unc_blocks,
};
+MODULE_AUTHOR("Olivier Grenie <ogrenie@dibcom.fr>");
MODULE_AUTHOR("Patrick Boettcher <pboettcher@dibcom.fr>");
MODULE_DESCRIPTION("Driver for the DiBcom 7000PC COFDM demodulator");
MODULE_LICENSE("GPL");
diff --git a/drivers/media/dvb/frontends/dib7000p.h b/drivers/media/dvb/frontends/dib7000p.h
index da17345bf5b..0179f9474ba 100644
--- a/drivers/media/dvb/frontends/dib7000p.h
+++ b/drivers/media/dvb/frontends/dib7000p.h
@@ -33,59 +33,54 @@ struct dib7000p_config {
int (*agc_control) (struct dvb_frontend *, u8 before);
u8 output_mode;
- u8 disable_sample_and_hold : 1;
+ u8 disable_sample_and_hold:1;
- u8 enable_current_mirror : 1;
- u8 diversity_delay;
+ u8 enable_current_mirror:1;
+ u16 diversity_delay;
+ u8 default_i2c_addr;
+ u8 enMpegOutput:1;
};
#define DEFAULT_DIB7000P_I2C_ADDRESS 18
#if defined(CONFIG_DVB_DIB7000P) || (defined(CONFIG_DVB_DIB7000P_MODULE) && \
- defined(MODULE))
-extern struct dvb_frontend *dib7000p_attach(struct i2c_adapter *i2c_adap,
- u8 i2c_addr,
- struct dib7000p_config *cfg);
-extern struct i2c_adapter *dib7000p_get_i2c_master(struct dvb_frontend *,
- enum dibx000_i2c_interface,
- int);
-extern int dib7000p_i2c_enumeration(struct i2c_adapter *i2c,
- int no_of_demods, u8 default_addr,
- struct dib7000p_config cfg[]);
+ defined(MODULE))
+extern struct dvb_frontend *dib7000p_attach(struct i2c_adapter *i2c_adap, u8 i2c_addr, struct dib7000p_config *cfg);
+extern struct i2c_adapter *dib7000p_get_i2c_master(struct dvb_frontend *, enum dibx000_i2c_interface, int);
+extern int dib7000p_i2c_enumeration(struct i2c_adapter *i2c, int no_of_demods, u8 default_addr, struct dib7000p_config cfg[]);
extern int dib7000p_set_gpio(struct dvb_frontend *, u8 num, u8 dir, u8 val);
extern int dib7000p_set_wbd_ref(struct dvb_frontend *, u16 value);
extern int dib7000pc_detection(struct i2c_adapter *i2c_adap);
extern int dib7000p_pid_filter(struct dvb_frontend *, u8 id, u16 pid, u8 onoff);
extern int dib7000p_pid_filter_ctrl(struct dvb_frontend *fe, u8 onoff);
+extern int dib7000p_update_pll(struct dvb_frontend *fe, struct dibx000_bandwidth_config *bw);
+extern u32 dib7000p_ctrl_timf(struct dvb_frontend *fe, u8 op, u32 timf);
+extern int dib7090_agc_restart(struct dvb_frontend *fe, u8 restart);
+extern int dib7090_tuner_sleep(struct dvb_frontend *fe, int onoff);
+extern int dib7090_get_adc_power(struct dvb_frontend *fe);
+extern struct i2c_adapter *dib7090_get_i2c_tuner(struct dvb_frontend *fe);
+extern int dib7090_slave_reset(struct dvb_frontend *fe);
#else
-static inline
-struct dvb_frontend *dib7000p_attach(struct i2c_adapter *i2c_adap, u8 i2c_addr,
- struct dib7000p_config *cfg)
+static inline struct dvb_frontend *dib7000p_attach(struct i2c_adapter *i2c_adap, u8 i2c_addr, struct dib7000p_config *cfg)
{
printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
return NULL;
}
-static inline
-struct i2c_adapter *dib7000p_get_i2c_master(struct dvb_frontend *fe,
- enum dibx000_i2c_interface i,
- int x)
+static inline struct i2c_adapter *dib7000p_get_i2c_master(struct dvb_frontend *fe, enum dibx000_i2c_interface i, int x)
{
printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
return NULL;
}
-static inline int dib7000p_i2c_enumeration(struct i2c_adapter *i2c,
- int no_of_demods, u8 default_addr,
- struct dib7000p_config cfg[])
+static inline int dib7000p_i2c_enumeration(struct i2c_adapter *i2c, int no_of_demods, u8 default_addr, struct dib7000p_config cfg[])
{
printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
return -ENODEV;
}
-static inline int dib7000p_set_gpio(struct dvb_frontend *fe,
- u8 num, u8 dir, u8 val)
+static inline int dib7000p_set_gpio(struct dvb_frontend *fe, u8 num, u8 dir, u8 val)
{
printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
return -ENODEV;
@@ -102,16 +97,59 @@ static inline int dib7000pc_detection(struct i2c_adapter *i2c_adap)
printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
return -ENODEV;
}
+
static inline int dib7000p_pid_filter(struct dvb_frontend *fe, u8 id, u16 pid, u8 onoff)
{
- printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
- return -ENODEV;
+ printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
+ return -ENODEV;
}
static inline int dib7000p_pid_filter_ctrl(struct dvb_frontend *fe, uint8_t onoff)
{
- printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
- return -ENODEV;
+ printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
+ return -ENODEV;
+}
+
+static inline int dib7000p_update_pll(struct dvb_frontend *fe, struct dibx000_bandwidth_config *bw)
+{
+ printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
+ return -ENODEV;
+}
+
+static inline u32 dib7000p_ctrl_timf(struct dvb_frontend *fe, u8 op, u32 timf)
+{
+ printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
+ return 0;
+}
+
+static inline int dib7090_agc_restart(struct dvb_frontend *fe, u8 restart)
+{
+ printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
+ return -ENODEV;
+}
+
+static inline int dib7090_tuner_sleep(struct dvb_frontend *fe, int onoff)
+{
+ printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
+ return -ENODEV;
+}
+
+static inline int dib7090_get_adc_power(struct dvb_frontend *fe)
+{
+ printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
+ return -ENODEV;
+}
+
+static inline struct i2c_adapter *dib7090_get_i2c_tuner(struct dvb_frontend *fe)
+{
+ printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
+ return NULL;
+}
+
+static inline int dib7090_slave_reset(struct dvb_frontend *fe)
+{
+ printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
+ return -ENODEV;
}
#endif
diff --git a/drivers/media/dvb/frontends/dib8000.c b/drivers/media/dvb/frontends/dib8000.c
index df17b91b325..c1c3e26906e 100644
--- a/drivers/media/dvb/frontends/dib8000.c
+++ b/drivers/media/dvb/frontends/dib8000.c
@@ -22,6 +22,7 @@
#define LAYER_C 3
#define FE_CALLBACK_TIME_NEVER 0xffffffff
+#define MAX_NUMBER_OF_FRONTENDS 6
static int debug;
module_param(debug, int, 0644);
@@ -37,7 +38,6 @@ struct i2c_device {
};
struct dib8000_state {
- struct dvb_frontend fe;
struct dib8000_config cfg;
struct i2c_device i2c;
@@ -68,6 +68,8 @@ struct dib8000_state {
u8 isdbt_cfg_loaded;
enum frontend_tune_state tune_state;
u32 status;
+
+ struct dvb_frontend *fe[MAX_NUMBER_OF_FRONTENDS];
};
enum dib8000_power_mode {
@@ -122,111 +124,111 @@ static int dib8000_write_word(struct dib8000_state *state, u16 reg, u16 val)
return dib8000_i2c_write16(&state->i2c, reg, val);
}
-static const int16_t coeff_2k_sb_1seg_dqpsk[8] = {
+static const s16 coeff_2k_sb_1seg_dqpsk[8] = {
(769 << 5) | 0x0a, (745 << 5) | 0x03, (595 << 5) | 0x0d, (769 << 5) | 0x0a, (920 << 5) | 0x09, (784 << 5) | 0x02, (519 << 5) | 0x0c,
- (920 << 5) | 0x09
+ (920 << 5) | 0x09
};
-static const int16_t coeff_2k_sb_1seg[8] = {
+static const s16 coeff_2k_sb_1seg[8] = {
(692 << 5) | 0x0b, (683 << 5) | 0x01, (519 << 5) | 0x09, (692 << 5) | 0x0b, 0 | 0x1f, 0 | 0x1f, 0 | 0x1f, 0 | 0x1f
};
-static const int16_t coeff_2k_sb_3seg_0dqpsk_1dqpsk[8] = {
+static const s16 coeff_2k_sb_3seg_0dqpsk_1dqpsk[8] = {
(832 << 5) | 0x10, (912 << 5) | 0x05, (900 << 5) | 0x12, (832 << 5) | 0x10, (-931 << 5) | 0x0f, (912 << 5) | 0x04, (807 << 5) | 0x11,
- (-931 << 5) | 0x0f
+ (-931 << 5) | 0x0f
};
-static const int16_t coeff_2k_sb_3seg_0dqpsk[8] = {
+static const s16 coeff_2k_sb_3seg_0dqpsk[8] = {
(622 << 5) | 0x0c, (941 << 5) | 0x04, (796 << 5) | 0x10, (622 << 5) | 0x0c, (982 << 5) | 0x0c, (519 << 5) | 0x02, (572 << 5) | 0x0e,
- (982 << 5) | 0x0c
+ (982 << 5) | 0x0c
};
-static const int16_t coeff_2k_sb_3seg_1dqpsk[8] = {
+static const s16 coeff_2k_sb_3seg_1dqpsk[8] = {
(699 << 5) | 0x14, (607 << 5) | 0x04, (944 << 5) | 0x13, (699 << 5) | 0x14, (-720 << 5) | 0x0d, (640 << 5) | 0x03, (866 << 5) | 0x12,
- (-720 << 5) | 0x0d
+ (-720 << 5) | 0x0d
};
-static const int16_t coeff_2k_sb_3seg[8] = {
+static const s16 coeff_2k_sb_3seg[8] = {
(664 << 5) | 0x0c, (925 << 5) | 0x03, (937 << 5) | 0x10, (664 << 5) | 0x0c, (-610 << 5) | 0x0a, (697 << 5) | 0x01, (836 << 5) | 0x0e,
- (-610 << 5) | 0x0a
+ (-610 << 5) | 0x0a
};
-static const int16_t coeff_4k_sb_1seg_dqpsk[8] = {
+static const s16 coeff_4k_sb_1seg_dqpsk[8] = {
(-955 << 5) | 0x0e, (687 << 5) | 0x04, (818 << 5) | 0x10, (-955 << 5) | 0x0e, (-922 << 5) | 0x0d, (750 << 5) | 0x03, (665 << 5) | 0x0f,
- (-922 << 5) | 0x0d
+ (-922 << 5) | 0x0d
};
-static const int16_t coeff_4k_sb_1seg[8] = {
+static const s16 coeff_4k_sb_1seg[8] = {
(638 << 5) | 0x0d, (683 << 5) | 0x02, (638 << 5) | 0x0d, (638 << 5) | 0x0d, (-655 << 5) | 0x0a, (517 << 5) | 0x00, (698 << 5) | 0x0d,
- (-655 << 5) | 0x0a
+ (-655 << 5) | 0x0a
};
-static const int16_t coeff_4k_sb_3seg_0dqpsk_1dqpsk[8] = {
+static const s16 coeff_4k_sb_3seg_0dqpsk_1dqpsk[8] = {
(-707 << 5) | 0x14, (910 << 5) | 0x06, (889 << 5) | 0x16, (-707 << 5) | 0x14, (-958 << 5) | 0x13, (993 << 5) | 0x05, (523 << 5) | 0x14,
- (-958 << 5) | 0x13
+ (-958 << 5) | 0x13
};
-static const int16_t coeff_4k_sb_3seg_0dqpsk[8] = {
+static const s16 coeff_4k_sb_3seg_0dqpsk[8] = {
(-723 << 5) | 0x13, (910 << 5) | 0x05, (777 << 5) | 0x14, (-723 << 5) | 0x13, (-568 << 5) | 0x0f, (547 << 5) | 0x03, (696 << 5) | 0x12,
- (-568 << 5) | 0x0f
+ (-568 << 5) | 0x0f
};
-static const int16_t coeff_4k_sb_3seg_1dqpsk[8] = {
+static const s16 coeff_4k_sb_3seg_1dqpsk[8] = {
(-940 << 5) | 0x15, (607 << 5) | 0x05, (915 << 5) | 0x16, (-940 << 5) | 0x15, (-848 << 5) | 0x13, (683 << 5) | 0x04, (543 << 5) | 0x14,
- (-848 << 5) | 0x13
+ (-848 << 5) | 0x13
};
-static const int16_t coeff_4k_sb_3seg[8] = {
+static const s16 coeff_4k_sb_3seg[8] = {
(612 << 5) | 0x12, (910 << 5) | 0x04, (864 << 5) | 0x14, (612 << 5) | 0x12, (-869 << 5) | 0x13, (683 << 5) | 0x02, (869 << 5) | 0x12,
- (-869 << 5) | 0x13
+ (-869 << 5) | 0x13
};
-static const int16_t coeff_8k_sb_1seg_dqpsk[8] = {
+static const s16 coeff_8k_sb_1seg_dqpsk[8] = {
(-835 << 5) | 0x12, (684 << 5) | 0x05, (735 << 5) | 0x14, (-835 << 5) | 0x12, (-598 << 5) | 0x10, (781 << 5) | 0x04, (739 << 5) | 0x13,
- (-598 << 5) | 0x10
+ (-598 << 5) | 0x10
};
-static const int16_t coeff_8k_sb_1seg[8] = {
+static const s16 coeff_8k_sb_1seg[8] = {
(673 << 5) | 0x0f, (683 << 5) | 0x03, (808 << 5) | 0x12, (673 << 5) | 0x0f, (585 << 5) | 0x0f, (512 << 5) | 0x01, (780 << 5) | 0x0f,
- (585 << 5) | 0x0f
+ (585 << 5) | 0x0f
};
-static const int16_t coeff_8k_sb_3seg_0dqpsk_1dqpsk[8] = {
+static const s16 coeff_8k_sb_3seg_0dqpsk_1dqpsk[8] = {
(863 << 5) | 0x17, (930 << 5) | 0x07, (878 << 5) | 0x19, (863 << 5) | 0x17, (0 << 5) | 0x14, (521 << 5) | 0x05, (980 << 5) | 0x18,
- (0 << 5) | 0x14
+ (0 << 5) | 0x14
};
-static const int16_t coeff_8k_sb_3seg_0dqpsk[8] = {
+static const s16 coeff_8k_sb_3seg_0dqpsk[8] = {
(-924 << 5) | 0x17, (910 << 5) | 0x06, (774 << 5) | 0x17, (-924 << 5) | 0x17, (-877 << 5) | 0x15, (565 << 5) | 0x04, (553 << 5) | 0x15,
- (-877 << 5) | 0x15
+ (-877 << 5) | 0x15
};
-static const int16_t coeff_8k_sb_3seg_1dqpsk[8] = {
+static const s16 coeff_8k_sb_3seg_1dqpsk[8] = {
(-921 << 5) | 0x19, (607 << 5) | 0x06, (881 << 5) | 0x19, (-921 << 5) | 0x19, (-921 << 5) | 0x14, (713 << 5) | 0x05, (1018 << 5) | 0x18,
- (-921 << 5) | 0x14
+ (-921 << 5) | 0x14
};
-static const int16_t coeff_8k_sb_3seg[8] = {
+static const s16 coeff_8k_sb_3seg[8] = {
(514 << 5) | 0x14, (910 << 5) | 0x05, (861 << 5) | 0x17, (514 << 5) | 0x14, (690 << 5) | 0x14, (683 << 5) | 0x03, (662 << 5) | 0x15,
- (690 << 5) | 0x14
+ (690 << 5) | 0x14
};
-static const int16_t ana_fe_coeff_3seg[24] = {
+static const s16 ana_fe_coeff_3seg[24] = {
81, 80, 78, 74, 68, 61, 54, 45, 37, 28, 19, 11, 4, 1022, 1017, 1013, 1010, 1008, 1008, 1008, 1008, 1010, 1014, 1017
};
-static const int16_t ana_fe_coeff_1seg[24] = {
+static const s16 ana_fe_coeff_1seg[24] = {
249, 226, 164, 82, 5, 981, 970, 988, 1018, 20, 31, 26, 8, 1012, 1000, 1018, 1012, 8, 15, 14, 9, 3, 1017, 1003
};
-static const int16_t ana_fe_coeff_13seg[24] = {
+static const s16 ana_fe_coeff_13seg[24] = {
396, 305, 105, -51, -77, -12, 41, 31, -11, -30, -11, 14, 15, -2, -13, -7, 5, 8, 1, -6, -7, -3, 0, 1
};
static u16 fft_to_mode(struct dib8000_state *state)
{
u16 mode;
- switch (state->fe.dtv_property_cache.transmission_mode) {
+ switch (state->fe[0]->dtv_property_cache.transmission_mode) {
case TRANSMISSION_MODE_2K:
mode = 1;
break;
@@ -249,16 +251,18 @@ static void dib8000_set_acquisition_mode(struct dib8000_state *state)
dprintk("acquisition mode activated");
dib8000_write_word(state, 298, nud);
}
-
-static int dib8000_set_output_mode(struct dib8000_state *state, int mode)
+static int dib8000_set_output_mode(struct dvb_frontend *fe, int mode)
{
+ struct dib8000_state *state = fe->demodulator_priv;
+
u16 outreg, fifo_threshold, smo_mode, sram = 0x0205; /* by default SDRAM deintlv is enabled */
outreg = 0;
fifo_threshold = 1792;
smo_mode = (dib8000_read_word(state, 299) & 0x0050) | (1 << 1);
- dprintk("-I- Setting output mode for demod %p to %d", &state->fe, mode);
+ dprintk("-I- Setting output mode for demod %p to %d",
+ &state->fe[0], mode);
switch (mode) {
case OUTMODE_MPEG2_PAR_GATED_CLK: // STBs with parallel gated clock
@@ -292,7 +296,8 @@ static int dib8000_set_output_mode(struct dib8000_state *state, int mode)
break;
default:
- dprintk("Unhandled output_mode passed to be set for demod %p", &state->fe);
+ dprintk("Unhandled output_mode passed to be set for demod %p",
+ &state->fe[0]);
return -EINVAL;
}
@@ -342,7 +347,8 @@ static void dib8000_set_power_mode(struct dib8000_state *state, enum dib8000_pow
{
/* by default everything is going to be powered off */
u16 reg_774 = 0x3fff, reg_775 = 0xffff, reg_776 = 0xffff,
- reg_900 = (dib8000_read_word(state, 900) & 0xfffc) | 0x3, reg_1280 = (dib8000_read_word(state, 1280) & 0x00ff) | 0xff00;
+ reg_900 = (dib8000_read_word(state, 900) & 0xfffc) | 0x3,
+ reg_1280 = (dib8000_read_word(state, 1280) & 0x00ff) | 0xff00;
/* now, depending on the requested mode, we power on */
switch (mode) {
@@ -411,8 +417,9 @@ static int dib8000_set_adc_state(struct dib8000_state *state, enum dibx000_adc_s
return ret;
}
-static int dib8000_set_bandwidth(struct dib8000_state *state, u32 bw)
+static int dib8000_set_bandwidth(struct dvb_frontend *fe, u32 bw)
{
+ struct dib8000_state *state = fe->demodulator_priv;
u32 timf;
if (bw == 0)
@@ -478,7 +485,8 @@ static void dib8000_reset_pll(struct dib8000_state *state)
// clk_cfg1
clk_cfg1 = (1 << 10) | (0 << 9) | (pll->IO_CLK_en_core << 8) |
- (pll->bypclk_div << 5) | (pll->enable_refdiv << 4) | (1 << 3) | (pll->pll_range << 1) | (pll->pll_reset << 0);
+ (pll->bypclk_div << 5) | (pll->enable_refdiv << 4) | (1 << 3) |
+ (pll->pll_range << 1) | (pll->pll_reset << 0);
dib8000_write_word(state, 902, clk_cfg1);
clk_cfg1 = (clk_cfg1 & 0xfff7) | (pll->pll_bypass << 3);
@@ -488,11 +496,12 @@ static void dib8000_reset_pll(struct dib8000_state *state)
/* smpl_cfg: P_refclksel=2, P_ensmplsel=1 nodivsmpl=1 */
if (state->cfg.pll->ADClkSrc == 0)
- dib8000_write_word(state, 904, (0 << 15) | (0 << 12) | (0 << 10) | (pll->modulo << 8) | (pll->ADClkSrc << 7) | (0 << 1));
+ dib8000_write_word(state, 904, (0 << 15) | (0 << 12) | (0 << 10) |
+ (pll->modulo << 8) | (pll->ADClkSrc << 7) | (0 << 1));
else if (state->cfg.refclksel != 0)
- dib8000_write_word(state, 904,
- (0 << 15) | (1 << 12) | ((state->cfg.refclksel & 0x3) << 10) | (pll->modulo << 8) | (pll->
- ADClkSrc << 7) | (0 << 1));
+ dib8000_write_word(state, 904, (0 << 15) | (1 << 12) |
+ ((state->cfg.refclksel & 0x3) << 10) | (pll->modulo << 8) |
+ (pll->ADClkSrc << 7) | (0 << 1));
else
dib8000_write_word(state, 904, (0 << 15) | (1 << 12) | (3 << 10) | (pll->modulo << 8) | (pll->ADClkSrc << 7) | (0 << 1));
@@ -560,7 +569,7 @@ static const u16 dib8000_defaults[] = {
0xd4c0,
/*1, 32,
- 0x6680 // P_corm_thres Lock algorithms configuration */
+ 0x6680 // P_corm_thres Lock algorithms configuration */
11, 80, /* set ADC level to -16 */
(1 << 13) - 825 - 117,
@@ -623,14 +632,14 @@ static const u16 dib8000_defaults[] = {
1, 285,
0x0020, //p_fec_
1, 299,
- 0x0062, // P_smo_mode, P_smo_rs_discard, P_smo_fifo_flush, P_smo_pid_parse, P_smo_error_discard
+ 0x0062, /* P_smo_mode, P_smo_rs_discard, P_smo_fifo_flush, P_smo_pid_parse, P_smo_error_discard */
1, 338,
(1 << 12) | // P_ctrl_corm_thres4pre_freq_inh=1
- (1 << 10) | // P_ctrl_pre_freq_mode_sat=1
- (0 << 9) | // P_ctrl_pre_freq_inh=0
- (3 << 5) | // P_ctrl_pre_freq_step=3
- (1 << 0), // P_pre_freq_win_len=1
+ (1 << 10) |
+ (0 << 9) | /* P_ctrl_pre_freq_inh=0 */
+ (3 << 5) | /* P_ctrl_pre_freq_step=3 */
+ (1 << 0), /* P_pre_freq_win_len=1 */
1, 903,
(0 << 4) | 2, // P_divclksel=0 P_divbitsel=2 (was clk=3,bit=1 for MPW)
@@ -717,7 +726,7 @@ static int dib8000_reset(struct dvb_frontend *fe)
if (dib8000_reset_gpio(state) != 0)
dprintk("GPIO reset was not successful.");
- if (dib8000_set_output_mode(state, OUTMODE_HIGH_Z) != 0)
+ if (dib8000_set_output_mode(fe, OUTMODE_HIGH_Z) != 0)
dprintk("OUTPUT_MODE could not be resetted.");
state->current_agc = NULL;
@@ -752,7 +761,7 @@ static int dib8000_reset(struct dvb_frontend *fe)
/* unforce divstr regardless whether i2c enumeration was done or not */
dib8000_write_word(state, 1285, dib8000_read_word(state, 1285) & ~(1 << 1));
- dib8000_set_bandwidth(state, 6000);
+ dib8000_set_bandwidth(fe, 6000);
dib8000_set_adc_state(state, DIBX000_SLOW_ADC_ON);
dib8000_sad_calib(state);
@@ -778,7 +787,7 @@ static int dib8000_update_lna(struct dib8000_state *state)
// read dyn_gain here (because it is demod-dependent and not tuner)
dyn_gain = dib8000_read_word(state, 390);
- if (state->cfg.update_lna(&state->fe, dyn_gain)) { // LNA has changed
+ if (state->cfg.update_lna(state->fe[0], dyn_gain)) {
dib8000_restart_agc(state);
return 1;
}
@@ -865,7 +874,8 @@ static int dib8000_agc_soft_split(struct dib8000_state *state)
split_offset = state->current_agc->split.max;
else
split_offset = state->current_agc->split.max *
- (agc - state->current_agc->split.min_thres) / (state->current_agc->split.max_thres - state->current_agc->split.min_thres);
+ (agc - state->current_agc->split.min_thres) /
+ (state->current_agc->split.max_thres - state->current_agc->split.min_thres);
dprintk("AGC split_offset: %d", split_offset);
@@ -900,7 +910,7 @@ static int dib8000_agc_startup(struct dvb_frontend *fe)
case CT_AGC_STEP_0:
//AGC initialization
if (state->cfg.agc_control)
- state->cfg.agc_control(&state->fe, 1);
+ state->cfg.agc_control(fe, 1);
dib8000_restart_agc(state);
@@ -924,7 +934,7 @@ static int dib8000_agc_startup(struct dvb_frontend *fe)
dib8000_agc_soft_split(state);
if (state->cfg.agc_control)
- state->cfg.agc_control(&state->fe, 0);
+ state->cfg.agc_control(fe, 0);
*tune_state = CT_AGC_STOP;
break;
@@ -936,29 +946,28 @@ static int dib8000_agc_startup(struct dvb_frontend *fe)
}
-static const int32_t lut_1000ln_mant[] =
+static const s32 lut_1000ln_mant[] =
{
908, 7003, 7090, 7170, 7244, 7313, 7377, 7438, 7495, 7549, 7600
};
-int32_t dib8000_get_adc_power(struct dvb_frontend *fe, uint8_t mode)
+s32 dib8000_get_adc_power(struct dvb_frontend *fe, u8 mode)
{
- struct dib8000_state *state = fe->demodulator_priv;
- uint32_t ix = 0, tmp_val = 0, exp = 0, mant = 0;
- int32_t val;
-
- val = dib8000_read32(state, 384);
- /* mode = 1 : ln_agcpower calc using mant-exp conversion and mantis look up table */
- if (mode) {
- tmp_val = val;
- while (tmp_val >>= 1)
- exp++;
- mant = (val * 1000 / (1<<exp));
- ix = (uint8_t)((mant-1000)/100); /* index of the LUT */
- val = (lut_1000ln_mant[ix] + 693*(exp-20) - 6908); /* 1000 * ln(adcpower_real) ; 693 = 1000ln(2) ; 6908 = 1000*ln(1000) ; 20 comes from adc_real = adc_pow_int / 2**20 */
- val = (val*256)/1000;
- }
- return val;
+ struct dib8000_state *state = fe->demodulator_priv;
+ u32 ix = 0, tmp_val = 0, exp = 0, mant = 0;
+ s32 val;
+
+ val = dib8000_read32(state, 384);
+ if (mode) {
+ tmp_val = val;
+ while (tmp_val >>= 1)
+ exp++;
+ mant = (val * 1000 / (1<<exp));
+ ix = (u8)((mant-1000)/100); /* index of the LUT */
+ val = (lut_1000ln_mant[ix] + 693*(exp-20) - 6908);
+ val = (val*256)/1000;
+ }
+ return val;
}
EXPORT_SYMBOL(dib8000_get_adc_power);
@@ -1002,22 +1011,23 @@ static void dib8000_set_channel(struct dib8000_state *state, u8 seq, u8 autosear
dib8000_write_word(state, 285, dib8000_read_word(state, 285) & 0x60);
i = dib8000_read_word(state, 26) & 1; // P_dds_invspec
- dib8000_write_word(state, 26, state->fe.dtv_property_cache.inversion ^ i);
+ dib8000_write_word(state, 26, state->fe[0]->dtv_property_cache.inversion^i);
- if (state->fe.dtv_property_cache.isdbt_sb_mode) {
+ if (state->fe[0]->dtv_property_cache.isdbt_sb_mode) {
//compute new dds_freq for the seg and adjust prbs
int seg_offset =
- state->fe.dtv_property_cache.isdbt_sb_segment_idx - (state->fe.dtv_property_cache.isdbt_sb_segment_count / 2) -
- (state->fe.dtv_property_cache.isdbt_sb_segment_count % 2);
+ state->fe[0]->dtv_property_cache.isdbt_sb_segment_idx -
+ (state->fe[0]->dtv_property_cache.isdbt_sb_segment_count / 2) -
+ (state->fe[0]->dtv_property_cache.isdbt_sb_segment_count % 2);
int clk = state->cfg.pll->internal;
u32 segtodds = ((u32) (430 << 23) / clk) << 3; // segtodds = SegBW / Fclk * pow(2,26)
int dds_offset = seg_offset * segtodds;
int new_dds, sub_channel;
- if ((state->fe.dtv_property_cache.isdbt_sb_segment_count % 2) == 0) // if even
+ if ((state->fe[0]->dtv_property_cache.isdbt_sb_segment_count % 2) == 0)
dds_offset -= (int)(segtodds / 2);
if (state->cfg.pll->ifreq == 0) {
- if ((state->fe.dtv_property_cache.inversion ^ i) == 0) {
+ if ((state->fe[0]->dtv_property_cache.inversion ^ i) == 0) {
dib8000_write_word(state, 26, dib8000_read_word(state, 26) | 1);
new_dds = dds_offset;
} else
@@ -1027,35 +1037,35 @@ static void dib8000_set_channel(struct dib8000_state *state, u8 seq, u8 autosear
// - the segment of center frequency with an odd total number of segments
// - the segment to the left of center frequency with an even total number of segments
// - the segment to the right of center frequency with an even total number of segments
- if ((state->fe.dtv_property_cache.delivery_system == SYS_ISDBT) && (state->fe.dtv_property_cache.isdbt_sb_mode == 1)
- &&
- (((state->fe.dtv_property_cache.isdbt_sb_segment_count % 2)
- && (state->fe.dtv_property_cache.isdbt_sb_segment_idx ==
- ((state->fe.dtv_property_cache.isdbt_sb_segment_count / 2) + 1)))
- || (((state->fe.dtv_property_cache.isdbt_sb_segment_count % 2) == 0)
- && (state->fe.dtv_property_cache.isdbt_sb_segment_idx == (state->fe.dtv_property_cache.isdbt_sb_segment_count / 2)))
- || (((state->fe.dtv_property_cache.isdbt_sb_segment_count % 2) == 0)
- && (state->fe.dtv_property_cache.isdbt_sb_segment_idx ==
- ((state->fe.dtv_property_cache.isdbt_sb_segment_count / 2) + 1)))
- )) {
+ if ((state->fe[0]->dtv_property_cache.delivery_system == SYS_ISDBT)
+ && (state->fe[0]->dtv_property_cache.isdbt_sb_mode == 1)
+ && (((state->fe[0]->dtv_property_cache.isdbt_sb_segment_count % 2)
+ && (state->fe[0]->dtv_property_cache.isdbt_sb_segment_idx ==
+ ((state->fe[0]->dtv_property_cache.isdbt_sb_segment_count / 2) + 1)))
+ || (((state->fe[0]->dtv_property_cache.isdbt_sb_segment_count % 2) == 0)
+ && (state->fe[0]->dtv_property_cache.isdbt_sb_segment_idx == (state->fe[0]->dtv_property_cache.isdbt_sb_segment_count / 2)))
+ || (((state->fe[0]->dtv_property_cache.isdbt_sb_segment_count % 2) == 0)
+ && (state->fe[0]->dtv_property_cache.isdbt_sb_segment_idx ==
+ ((state->fe[0]->dtv_property_cache.isdbt_sb_segment_count / 2) + 1)))
+ )) {
new_dds -= ((u32) (850 << 22) / clk) << 4; // new_dds = 850 (freq shift in KHz) / Fclk * pow(2,26)
}
} else {
- if ((state->fe.dtv_property_cache.inversion ^ i) == 0)
+ if ((state->fe[0]->dtv_property_cache.inversion ^ i) == 0)
new_dds = state->cfg.pll->ifreq - dds_offset;
else
new_dds = state->cfg.pll->ifreq + dds_offset;
}
dib8000_write_word(state, 27, (u16) ((new_dds >> 16) & 0x01ff));
dib8000_write_word(state, 28, (u16) (new_dds & 0xffff));
- if (state->fe.dtv_property_cache.isdbt_sb_segment_count % 2) // if odd
- sub_channel = ((state->fe.dtv_property_cache.isdbt_sb_subchannel + (3 * seg_offset) + 1) % 41) / 3;
- else // if even
- sub_channel = ((state->fe.dtv_property_cache.isdbt_sb_subchannel + (3 * seg_offset)) % 41) / 3;
+ if (state->fe[0]->dtv_property_cache.isdbt_sb_segment_count % 2)
+ sub_channel = ((state->fe[0]->dtv_property_cache.isdbt_sb_subchannel + (3 * seg_offset) + 1) % 41) / 3;
+ else
+ sub_channel = ((state->fe[0]->dtv_property_cache.isdbt_sb_subchannel + (3 * seg_offset)) % 41) / 3;
sub_channel -= 6;
- if (state->fe.dtv_property_cache.transmission_mode == TRANSMISSION_MODE_2K
- || state->fe.dtv_property_cache.transmission_mode == TRANSMISSION_MODE_4K) {
+ if (state->fe[0]->dtv_property_cache.transmission_mode == TRANSMISSION_MODE_2K
+ || state->fe[0]->dtv_property_cache.transmission_mode == TRANSMISSION_MODE_4K) {
dib8000_write_word(state, 219, dib8000_read_word(state, 219) | 0x1); //adp_pass =1
dib8000_write_word(state, 190, dib8000_read_word(state, 190) | (0x1 << 14)); //pha3_force_pha_shift = 1
} else {
@@ -1063,7 +1073,7 @@ static void dib8000_set_channel(struct dib8000_state *state, u8 seq, u8 autosear
dib8000_write_word(state, 190, dib8000_read_word(state, 190) & 0xbfff); //pha3_force_pha_shift = 0
}
- switch (state->fe.dtv_property_cache.transmission_mode) {
+ switch (state->fe[0]->dtv_property_cache.transmission_mode) {
case TRANSMISSION_MODE_2K:
switch (sub_channel) {
case -6:
@@ -1209,7 +1219,7 @@ static void dib8000_set_channel(struct dib8000_state *state, u8 seq, u8 autosear
}
break;
}
- } else { // if not state->fe.dtv_property_cache.isdbt_sb_mode
+ } else {
dib8000_write_word(state, 27, (u16) ((state->cfg.pll->ifreq >> 16) & 0x01ff));
dib8000_write_word(state, 28, (u16) (state->cfg.pll->ifreq & 0xffff));
dib8000_write_word(state, 26, (u16) ((state->cfg.pll->ifreq >> 25) & 0x0003));
@@ -1218,7 +1228,7 @@ static void dib8000_set_channel(struct dib8000_state *state, u8 seq, u8 autosear
dib8000_write_word(state, 10, (seq << 4));
// dib8000_write_word(state, 287, (dib8000_read_word(state, 287) & 0xe000) | 0x1000);
- switch (state->fe.dtv_property_cache.guard_interval) {
+ switch (state->fe[0]->dtv_property_cache.guard_interval) {
case GUARD_INTERVAL_1_32:
guard = 0;
break;
@@ -1238,7 +1248,7 @@ static void dib8000_set_channel(struct dib8000_state *state, u8 seq, u8 autosear
max_constellation = DQPSK;
for (i = 0; i < 3; i++) {
- switch (state->fe.dtv_property_cache.layer[i].modulation) {
+ switch (state->fe[0]->dtv_property_cache.layer[i].modulation) {
case DQPSK:
constellation = 0;
break;
@@ -1254,7 +1264,7 @@ static void dib8000_set_channel(struct dib8000_state *state, u8 seq, u8 autosear
break;
}
- switch (state->fe.dtv_property_cache.layer[i].fec) {
+ switch (state->fe[0]->dtv_property_cache.layer[i].fec) {
case FEC_1_2:
crate = 1;
break;
@@ -1273,26 +1283,26 @@ static void dib8000_set_channel(struct dib8000_state *state, u8 seq, u8 autosear
break;
}
- if ((state->fe.dtv_property_cache.layer[i].interleaving > 0) &&
- ((state->fe.dtv_property_cache.layer[i].interleaving <= 3) ||
- (state->fe.dtv_property_cache.layer[i].interleaving == 4 && state->fe.dtv_property_cache.isdbt_sb_mode == 1))
- )
- timeI = state->fe.dtv_property_cache.layer[i].interleaving;
+ if ((state->fe[0]->dtv_property_cache.layer[i].interleaving > 0) &&
+ ((state->fe[0]->dtv_property_cache.layer[i].interleaving <= 3) ||
+ (state->fe[0]->dtv_property_cache.layer[i].interleaving == 4 && state->fe[0]->dtv_property_cache.isdbt_sb_mode == 1))
+ )
+ timeI = state->fe[0]->dtv_property_cache.layer[i].interleaving;
else
timeI = 0;
- dib8000_write_word(state, 2 + i, (constellation << 10) | ((state->fe.dtv_property_cache.layer[i].segment_count & 0xf) << 6) |
- (crate << 3) | timeI);
- if (state->fe.dtv_property_cache.layer[i].segment_count > 0) {
+ dib8000_write_word(state, 2 + i, (constellation << 10) | ((state->fe[0]->dtv_property_cache.layer[i].segment_count & 0xf) << 6) |
+ (crate << 3) | timeI);
+ if (state->fe[0]->dtv_property_cache.layer[i].segment_count > 0) {
switch (max_constellation) {
case DQPSK:
case QPSK:
- if (state->fe.dtv_property_cache.layer[i].modulation == QAM_16 ||
- state->fe.dtv_property_cache.layer[i].modulation == QAM_64)
- max_constellation = state->fe.dtv_property_cache.layer[i].modulation;
+ if (state->fe[0]->dtv_property_cache.layer[i].modulation == QAM_16 ||
+ state->fe[0]->dtv_property_cache.layer[i].modulation == QAM_64)
+ max_constellation = state->fe[0]->dtv_property_cache.layer[i].modulation;
break;
case QAM_16:
- if (state->fe.dtv_property_cache.layer[i].modulation == QAM_64)
- max_constellation = state->fe.dtv_property_cache.layer[i].modulation;
+ if (state->fe[0]->dtv_property_cache.layer[i].modulation == QAM_64)
+ max_constellation = state->fe[0]->dtv_property_cache.layer[i].modulation;
break;
}
}
@@ -1303,34 +1313,34 @@ static void dib8000_set_channel(struct dib8000_state *state, u8 seq, u8 autosear
//dib8000_write_word(state, 5, 13); /*p_last_seg = 13*/
dib8000_write_word(state, 274, (dib8000_read_word(state, 274) & 0xffcf) |
- ((state->fe.dtv_property_cache.isdbt_partial_reception & 1) << 5) | ((state->fe.dtv_property_cache.
+ ((state->fe[0]->dtv_property_cache.isdbt_partial_reception & 1) << 5) | ((state->fe[0]->dtv_property_cache.
isdbt_sb_mode & 1) << 4));
- dprintk("mode = %d ; guard = %d", mode, state->fe.dtv_property_cache.guard_interval);
+ dprintk("mode = %d ; guard = %d", mode, state->fe[0]->dtv_property_cache.guard_interval);
/* signal optimization parameter */
- if (state->fe.dtv_property_cache.isdbt_partial_reception) {
- seg_diff_mask = (state->fe.dtv_property_cache.layer[0].modulation == DQPSK) << permu_seg[0];
+ if (state->fe[0]->dtv_property_cache.isdbt_partial_reception) {
+ seg_diff_mask = (state->fe[0]->dtv_property_cache.layer[0].modulation == DQPSK) << permu_seg[0];
for (i = 1; i < 3; i++)
nbseg_diff +=
- (state->fe.dtv_property_cache.layer[i].modulation == DQPSK) * state->fe.dtv_property_cache.layer[i].segment_count;
+ (state->fe[0]->dtv_property_cache.layer[i].modulation == DQPSK) * state->fe[0]->dtv_property_cache.layer[i].segment_count;
for (i = 0; i < nbseg_diff; i++)
seg_diff_mask |= 1 << permu_seg[i + 1];
} else {
for (i = 0; i < 3; i++)
nbseg_diff +=
- (state->fe.dtv_property_cache.layer[i].modulation == DQPSK) * state->fe.dtv_property_cache.layer[i].segment_count;
+ (state->fe[0]->dtv_property_cache.layer[i].modulation == DQPSK) * state->fe[0]->dtv_property_cache.layer[i].segment_count;
for (i = 0; i < nbseg_diff; i++)
seg_diff_mask |= 1 << permu_seg[i];
}
dprintk("nbseg_diff = %X (%d)", seg_diff_mask, seg_diff_mask);
state->differential_constellation = (seg_diff_mask != 0);
- dib8000_set_diversity_in(&state->fe, state->diversity_onoff);
+ dib8000_set_diversity_in(state->fe[0], state->diversity_onoff);
- if (state->fe.dtv_property_cache.isdbt_sb_mode == 1) { // ISDB-Tsb
- if (state->fe.dtv_property_cache.isdbt_partial_reception == 1) // 3-segments
+ if (state->fe[0]->dtv_property_cache.isdbt_sb_mode == 1) {
+ if (state->fe[0]->dtv_property_cache.isdbt_partial_reception == 1)
seg_mask13 = 0x00E0;
else // 1-segment
seg_mask13 = 0x0040;
@@ -1340,7 +1350,7 @@ static void dib8000_set_channel(struct dib8000_state *state, u8 seq, u8 autosear
// WRITE: Mode & Diff mask
dib8000_write_word(state, 0, (mode << 13) | seg_diff_mask);
- if ((seg_diff_mask) || (state->fe.dtv_property_cache.isdbt_sb_mode))
+ if ((seg_diff_mask) || (state->fe[0]->dtv_property_cache.isdbt_sb_mode))
dib8000_write_word(state, 268, (dib8000_read_word(state, 268) & 0xF9FF) | 0x0200);
else
dib8000_write_word(state, 268, (2 << 9) | 39); //init value
@@ -1351,26 +1361,25 @@ static void dib8000_set_channel(struct dib8000_state *state, u8 seq, u8 autosear
dib8000_write_word(state, 353, seg_mask13); // ADDR 353
-/* // P_small_narrow_band=0, P_small_last_seg=13, P_small_offset_num_car=5 */
- // dib8000_write_word(state, 351, (state->fe.dtv_property_cache.isdbt_sb_mode << 8) | (13 << 4) | 5 );
+/* // P_small_narrow_band=0, P_small_last_seg=13, P_small_offset_num_car=5 */
// ---- SMALL ----
- if (state->fe.dtv_property_cache.isdbt_sb_mode == 1) {
- switch (state->fe.dtv_property_cache.transmission_mode) {
+ if (state->fe[0]->dtv_property_cache.isdbt_sb_mode == 1) {
+ switch (state->fe[0]->dtv_property_cache.transmission_mode) {
case TRANSMISSION_MODE_2K:
- if (state->fe.dtv_property_cache.isdbt_partial_reception == 0) { // 1-seg
- if (state->fe.dtv_property_cache.layer[0].modulation == DQPSK) // DQPSK
+ if (state->fe[0]->dtv_property_cache.isdbt_partial_reception == 0) {
+ if (state->fe[0]->dtv_property_cache.layer[0].modulation == DQPSK)
ncoeff = coeff_2k_sb_1seg_dqpsk;
else // QPSK or QAM
ncoeff = coeff_2k_sb_1seg;
} else { // 3-segments
- if (state->fe.dtv_property_cache.layer[0].modulation == DQPSK) { // DQPSK on central segment
- if (state->fe.dtv_property_cache.layer[1].modulation == DQPSK) // DQPSK on external segments
+ if (state->fe[0]->dtv_property_cache.layer[0].modulation == DQPSK) {
+ if (state->fe[0]->dtv_property_cache.layer[1].modulation == DQPSK)
ncoeff = coeff_2k_sb_3seg_0dqpsk_1dqpsk;
else // QPSK or QAM on external segments
ncoeff = coeff_2k_sb_3seg_0dqpsk;
} else { // QPSK or QAM on central segment
- if (state->fe.dtv_property_cache.layer[1].modulation == DQPSK) // DQPSK on external segments
+ if (state->fe[0]->dtv_property_cache.layer[1].modulation == DQPSK)
ncoeff = coeff_2k_sb_3seg_1dqpsk;
else // QPSK or QAM on external segments
ncoeff = coeff_2k_sb_3seg;
@@ -1379,20 +1388,20 @@ static void dib8000_set_channel(struct dib8000_state *state, u8 seq, u8 autosear
break;
case TRANSMISSION_MODE_4K:
- if (state->fe.dtv_property_cache.isdbt_partial_reception == 0) { // 1-seg
- if (state->fe.dtv_property_cache.layer[0].modulation == DQPSK) // DQPSK
+ if (state->fe[0]->dtv_property_cache.isdbt_partial_reception == 0) {
+ if (state->fe[0]->dtv_property_cache.layer[0].modulation == DQPSK)
ncoeff = coeff_4k_sb_1seg_dqpsk;
else // QPSK or QAM
ncoeff = coeff_4k_sb_1seg;
} else { // 3-segments
- if (state->fe.dtv_property_cache.layer[0].modulation == DQPSK) { // DQPSK on central segment
- if (state->fe.dtv_property_cache.layer[1].modulation == DQPSK) { // DQPSK on external segments
+ if (state->fe[0]->dtv_property_cache.layer[0].modulation == DQPSK) {
+ if (state->fe[0]->dtv_property_cache.layer[1].modulation == DQPSK) {
ncoeff = coeff_4k_sb_3seg_0dqpsk_1dqpsk;
} else { // QPSK or QAM on external segments
ncoeff = coeff_4k_sb_3seg_0dqpsk;
}
} else { // QPSK or QAM on central segment
- if (state->fe.dtv_property_cache.layer[1].modulation == DQPSK) { // DQPSK on external segments
+ if (state->fe[0]->dtv_property_cache.layer[1].modulation == DQPSK) {
ncoeff = coeff_4k_sb_3seg_1dqpsk;
} else // QPSK or QAM on external segments
ncoeff = coeff_4k_sb_3seg;
@@ -1403,20 +1412,20 @@ static void dib8000_set_channel(struct dib8000_state *state, u8 seq, u8 autosear
case TRANSMISSION_MODE_AUTO:
case TRANSMISSION_MODE_8K:
default:
- if (state->fe.dtv_property_cache.isdbt_partial_reception == 0) { // 1-seg
- if (state->fe.dtv_property_cache.layer[0].modulation == DQPSK) // DQPSK
+ if (state->fe[0]->dtv_property_cache.isdbt_partial_reception == 0) {
+ if (state->fe[0]->dtv_property_cache.layer[0].modulation == DQPSK)
ncoeff = coeff_8k_sb_1seg_dqpsk;
else // QPSK or QAM
ncoeff = coeff_8k_sb_1seg;
} else { // 3-segments
- if (state->fe.dtv_property_cache.layer[0].modulation == DQPSK) { // DQPSK on central segment
- if (state->fe.dtv_property_cache.layer[1].modulation == DQPSK) { // DQPSK on external segments
+ if (state->fe[0]->dtv_property_cache.layer[0].modulation == DQPSK) {
+ if (state->fe[0]->dtv_property_cache.layer[1].modulation == DQPSK) {
ncoeff = coeff_8k_sb_3seg_0dqpsk_1dqpsk;
} else { // QPSK or QAM on external segments
ncoeff = coeff_8k_sb_3seg_0dqpsk;
}
} else { // QPSK or QAM on central segment
- if (state->fe.dtv_property_cache.layer[1].modulation == DQPSK) { // DQPSK on external segments
+ if (state->fe[0]->dtv_property_cache.layer[1].modulation == DQPSK) {
ncoeff = coeff_8k_sb_3seg_1dqpsk;
} else // QPSK or QAM on external segments
ncoeff = coeff_8k_sb_3seg;
@@ -1430,22 +1439,22 @@ static void dib8000_set_channel(struct dib8000_state *state, u8 seq, u8 autosear
// P_small_coef_ext_enable=ISDB-Tsb, P_small_narrow_band=ISDB-Tsb, P_small_last_seg=13, P_small_offset_num_car=5
dib8000_write_word(state, 351,
- (state->fe.dtv_property_cache.isdbt_sb_mode << 9) | (state->fe.dtv_property_cache.isdbt_sb_mode << 8) | (13 << 4) | 5);
+ (state->fe[0]->dtv_property_cache.isdbt_sb_mode << 9) | (state->fe[0]->dtv_property_cache.isdbt_sb_mode << 8) | (13 << 4) | 5);
// ---- COFF ----
// Carloff, the most robust
- if (state->fe.dtv_property_cache.isdbt_sb_mode == 1) { // Sound Broadcasting mode - use both TMCC and AC pilots
+ if (state->fe[0]->dtv_property_cache.isdbt_sb_mode == 1) {
// P_coff_cpil_alpha=4, P_coff_inh=0, P_coff_cpil_winlen=64
// P_coff_narrow_band=1, P_coff_square_val=1, P_coff_one_seg=~partial_rcpt, P_coff_use_tmcc=1, P_coff_use_ac=1
dib8000_write_word(state, 187,
- (4 << 12) | (0 << 11) | (63 << 5) | (0x3 << 3) | ((~state->fe.dtv_property_cache.isdbt_partial_reception & 1) << 2)
- | 0x3);
+ (4 << 12) | (0 << 11) | (63 << 5) | (0x3 << 3) | ((~state->fe[0]->dtv_property_cache.isdbt_partial_reception & 1) << 2)
+ | 0x3);
-/* // P_small_coef_ext_enable = 1 */
-/* dib8000_write_word(state, 351, dib8000_read_word(state, 351) | 0x200); */
+/* // P_small_coef_ext_enable = 1 */
+/* dib8000_write_word(state, 351, dib8000_read_word(state, 351) | 0x200); */
- if (state->fe.dtv_property_cache.isdbt_partial_reception == 0) { // Sound Broadcasting mode 1 seg
+ if (state->fe[0]->dtv_property_cache.isdbt_partial_reception == 0) {
// P_coff_winlen=63, P_coff_thres_lock=15, P_coff_one_seg_width= (P_mode == 3) , P_coff_one_seg_sym= (P_mode-1)
if (mode == 3)
@@ -1469,10 +1478,10 @@ static void dib8000_set_channel(struct dib8000_state *state, u8 seq, u8 autosear
dib8000_write_word(state, 186, 80);
} else { // Sound Broadcasting mode 3 seg
// P_coff_one_seg_sym= 1, P_coff_one_seg_width= 1, P_coff_winlen=63, P_coff_thres_lock=15
- /* if (mode == 3) */
- /* dib8000_write_word(state, 180, 0x2fca | ((0) << 14)); */
- /* else */
- /* dib8000_write_word(state, 180, 0x2fca | ((1) << 14)); */
+ /* if (mode == 3) */
+ /* dib8000_write_word(state, 180, 0x2fca | ((0) << 14)); */
+ /* else */
+ /* dib8000_write_word(state, 180, 0x2fca | ((1) << 14)); */
dib8000_write_word(state, 180, 0x1fcf | (1 << 14));
// P_ctrl_corm_thres4pre_freq_inh = 1, P_ctrl_pre_freq_mode_sat=1,
@@ -1509,7 +1518,7 @@ static void dib8000_set_channel(struct dib8000_state *state, u8 seq, u8 autosear
dib8000_write_word(state, 341, (4 << 3) | (1 << 2) | (1 << 1) | (1 << 0));
}
// ---- FFT ----
- if (state->fe.dtv_property_cache.isdbt_sb_mode == 1 && state->fe.dtv_property_cache.isdbt_partial_reception == 0) // 1-seg
+ if (state->fe[0]->dtv_property_cache.isdbt_sb_mode == 1 && state->fe[0]->dtv_property_cache.isdbt_partial_reception == 0)
dib8000_write_word(state, 178, 64); // P_fft_powrange=64
else
dib8000_write_word(state, 178, 32); // P_fft_powrange=32
@@ -1518,12 +1527,12 @@ static void dib8000_set_channel(struct dib8000_state *state, u8 seq, u8 autosear
* 6bits; p_coff_thres_lock 6bits (for coff lock if needed)
*/
/* if ( ( nbseg_diff>0)&&(nbseg_diff<13))
- dib8000_write_word(state, 187, (dib8000_read_word(state, 187) & 0xfffb) | (1 << 3)); */
+ dib8000_write_word(state, 187, (dib8000_read_word(state, 187) & 0xfffb) | (1 << 3)); */
dib8000_write_word(state, 189, ~seg_mask13 | seg_diff_mask); /* P_lmod4_seg_inh */
dib8000_write_word(state, 192, ~seg_mask13 | seg_diff_mask); /* P_pha3_seg_inh */
dib8000_write_word(state, 225, ~seg_mask13 | seg_diff_mask); /* P_tac_seg_inh */
- if ((!state->fe.dtv_property_cache.isdbt_sb_mode) && (state->cfg.pll->ifreq == 0))
+ if ((!state->fe[0]->dtv_property_cache.isdbt_sb_mode) && (state->cfg.pll->ifreq == 0))
dib8000_write_word(state, 266, ~seg_mask13 | seg_diff_mask | 0x40); /* P_equal_noise_seg_inh */
else
dib8000_write_word(state, 266, ~seg_mask13 | seg_diff_mask); /* P_equal_noise_seg_inh */
@@ -1538,8 +1547,8 @@ static void dib8000_set_channel(struct dib8000_state *state, u8 seq, u8 autosear
dib8000_write_word(state, 211, seg_mask13 & (~seg_diff_mask)); /* P_des_seg_enabled */
/* offset loop parameters */
- if (state->fe.dtv_property_cache.isdbt_sb_mode == 1) {
- if (state->fe.dtv_property_cache.isdbt_partial_reception == 0) // Sound Broadcasting mode 1 seg
+ if (state->fe[0]->dtv_property_cache.isdbt_sb_mode == 1) {
+ if (state->fe[0]->dtv_property_cache.isdbt_partial_reception == 0)
/* P_timf_alpha = (11-P_mode), P_corm_alpha=6, P_corm_thres=0x80 */
dib8000_write_word(state, 32, ((11 - mode) << 12) | (6 << 8) | 0x40);
@@ -1551,8 +1560,8 @@ static void dib8000_set_channel(struct dib8000_state *state, u8 seq, u8 autosear
/* P_timf_alpha = (9-P_mode, P_corm_alpha=6, P_corm_thres=0x80 */
dib8000_write_word(state, 32, ((9 - mode) << 12) | (6 << 8) | 0x80);
- if (state->fe.dtv_property_cache.isdbt_sb_mode == 1) {
- if (state->fe.dtv_property_cache.isdbt_partial_reception == 0) // Sound Broadcasting mode 1 seg
+ if (state->fe[0]->dtv_property_cache.isdbt_sb_mode == 1) {
+ if (state->fe[0]->dtv_property_cache.isdbt_partial_reception == 0)
/* P_ctrl_pha_off_max=3 P_ctrl_sfreq_inh =0 P_ctrl_sfreq_step = (11-P_mode) */
dib8000_write_word(state, 37, (3 << 5) | (0 << 4) | (10 - mode));
@@ -1564,7 +1573,7 @@ static void dib8000_set_channel(struct dib8000_state *state, u8 seq, u8 autosear
dib8000_write_word(state, 37, (3 << 5) | (0 << 4) | (8 - mode));
/* P_dvsy_sync_wait - reuse mode */
- switch (state->fe.dtv_property_cache.transmission_mode) {
+ switch (state->fe[0]->dtv_property_cache.transmission_mode) {
case TRANSMISSION_MODE_8K:
mode = 256;
break;
@@ -1624,15 +1633,15 @@ static void dib8000_set_channel(struct dib8000_state *state, u8 seq, u8 autosear
}
// ---- ANA_FE ----
- if (state->fe.dtv_property_cache.isdbt_sb_mode) {
- if (state->fe.dtv_property_cache.isdbt_partial_reception == 1) // 3-segments
+ if (state->fe[0]->dtv_property_cache.isdbt_sb_mode) {
+ if (state->fe[0]->dtv_property_cache.isdbt_partial_reception == 1)
ana_fe = ana_fe_coeff_3seg;
else // 1-segment
ana_fe = ana_fe_coeff_1seg;
} else
ana_fe = ana_fe_coeff_13seg;
- if (state->fe.dtv_property_cache.isdbt_sb_mode == 1 || state->isdbt_cfg_loaded == 0)
+ if (state->fe[0]->dtv_property_cache.isdbt_sb_mode == 1 || state->isdbt_cfg_loaded == 0)
for (mode = 0; mode < 24; mode++)
dib8000_write_word(state, 117 + mode, ana_fe[mode]);
@@ -1648,11 +1657,11 @@ static void dib8000_set_channel(struct dib8000_state *state, u8 seq, u8 autosear
// "P_cspu_left_edge" not used => do not care
// "P_cspu_right_edge" not used => do not care
- if (state->fe.dtv_property_cache.isdbt_sb_mode == 1) { // ISDB-Tsb
+ if (state->fe[0]->dtv_property_cache.isdbt_sb_mode == 1) {
dib8000_write_word(state, 228, 1); // P_2d_mode_byp=1
dib8000_write_word(state, 205, dib8000_read_word(state, 205) & 0xfff0); // P_cspu_win_cut = 0
- if (state->fe.dtv_property_cache.isdbt_partial_reception == 0 // 1-segment
- && state->fe.dtv_property_cache.transmission_mode == TRANSMISSION_MODE_2K) {
+ if (state->fe[0]->dtv_property_cache.isdbt_partial_reception == 0
+ && state->fe[0]->dtv_property_cache.transmission_mode == TRANSMISSION_MODE_2K) {
//dib8000_write_word(state, 219, dib8000_read_word(state, 219) & 0xfffe); // P_adp_pass = 0
dib8000_write_word(state, 265, 15); // P_equal_noise_sel = 15
}
@@ -1664,7 +1673,7 @@ static void dib8000_set_channel(struct dib8000_state *state, u8 seq, u8 autosear
// ---- TMCC ----
for (i = 0; i < 3; i++)
tmcc_pow +=
- (((state->fe.dtv_property_cache.layer[i].modulation == DQPSK) * 4 + 1) * state->fe.dtv_property_cache.layer[i].segment_count);
+ (((state->fe[0]->dtv_property_cache.layer[i].modulation == DQPSK) * 4 + 1) * state->fe[0]->dtv_property_cache.layer[i].segment_count);
// Quantif of "P_tmcc_dec_thres_?k" is (0, 5+mode, 9);
// Threshold is set at 1/4 of max power.
tmcc_pow *= (1 << (9 - 2));
@@ -1678,7 +1687,7 @@ static void dib8000_set_channel(struct dib8000_state *state, u8 seq, u8 autosear
if (state->isdbt_cfg_loaded == 0)
dib8000_write_word(state, 250, 3285); /*p_2d_hspeed_thr0 */
- if (state->fe.dtv_property_cache.isdbt_sb_mode == 1)
+ if (state->fe[0]->dtv_property_cache.isdbt_sb_mode == 1)
state->isdbt_cfg_loaded = 0;
else
state->isdbt_cfg_loaded = 1;
@@ -1693,38 +1702,38 @@ static int dib8000_autosearch_start(struct dvb_frontend *fe)
int slist = 0;
- state->fe.dtv_property_cache.inversion = 0;
- if (!state->fe.dtv_property_cache.isdbt_sb_mode)
- state->fe.dtv_property_cache.layer[0].segment_count = 13;
- state->fe.dtv_property_cache.layer[0].modulation = QAM_64;
- state->fe.dtv_property_cache.layer[0].fec = FEC_2_3;
- state->fe.dtv_property_cache.layer[0].interleaving = 0;
+ state->fe[0]->dtv_property_cache.inversion = 0;
+ if (!state->fe[0]->dtv_property_cache.isdbt_sb_mode)
+ state->fe[0]->dtv_property_cache.layer[0].segment_count = 13;
+ state->fe[0]->dtv_property_cache.layer[0].modulation = QAM_64;
+ state->fe[0]->dtv_property_cache.layer[0].fec = FEC_2_3;
+ state->fe[0]->dtv_property_cache.layer[0].interleaving = 0;
//choose the right list, in sb, always do everything
- if (state->fe.dtv_property_cache.isdbt_sb_mode) {
- state->fe.dtv_property_cache.transmission_mode = TRANSMISSION_MODE_8K;
- state->fe.dtv_property_cache.guard_interval = GUARD_INTERVAL_1_8;
+ if (state->fe[0]->dtv_property_cache.isdbt_sb_mode) {
+ state->fe[0]->dtv_property_cache.transmission_mode = TRANSMISSION_MODE_8K;
+ state->fe[0]->dtv_property_cache.guard_interval = GUARD_INTERVAL_1_8;
slist = 7;
dib8000_write_word(state, 0, (dib8000_read_word(state, 0) & 0x9fff) | (1 << 13));
} else {
- if (state->fe.dtv_property_cache.guard_interval == GUARD_INTERVAL_AUTO) {
- if (state->fe.dtv_property_cache.transmission_mode == TRANSMISSION_MODE_AUTO) {
+ if (state->fe[0]->dtv_property_cache.guard_interval == GUARD_INTERVAL_AUTO) {
+ if (state->fe[0]->dtv_property_cache.transmission_mode == TRANSMISSION_MODE_AUTO) {
slist = 7;
dib8000_write_word(state, 0, (dib8000_read_word(state, 0) & 0x9fff) | (1 << 13)); // P_mode = 1 to have autosearch start ok with mode2
} else
slist = 3;
} else {
- if (state->fe.dtv_property_cache.transmission_mode == TRANSMISSION_MODE_AUTO) {
+ if (state->fe[0]->dtv_property_cache.transmission_mode == TRANSMISSION_MODE_AUTO) {
slist = 2;
dib8000_write_word(state, 0, (dib8000_read_word(state, 0) & 0x9fff) | (1 << 13)); // P_mode = 1
} else
slist = 0;
}
- if (state->fe.dtv_property_cache.transmission_mode == TRANSMISSION_MODE_AUTO)
- state->fe.dtv_property_cache.transmission_mode = TRANSMISSION_MODE_8K;
- if (state->fe.dtv_property_cache.guard_interval == GUARD_INTERVAL_AUTO)
- state->fe.dtv_property_cache.guard_interval = GUARD_INTERVAL_1_8;
+ if (state->fe[0]->dtv_property_cache.transmission_mode == TRANSMISSION_MODE_AUTO)
+ state->fe[0]->dtv_property_cache.transmission_mode = TRANSMISSION_MODE_8K;
+ if (state->fe[0]->dtv_property_cache.guard_interval == GUARD_INTERVAL_AUTO)
+ state->fe[0]->dtv_property_cache.guard_interval = GUARD_INTERVAL_1_8;
dprintk("using list for autosearch : %d", slist);
dib8000_set_channel(state, (unsigned char)slist, 1);
@@ -1786,7 +1795,7 @@ static int dib8000_tune(struct dvb_frontend *fe)
if (state == NULL)
return -EINVAL;
- dib8000_set_bandwidth(state, state->fe.dtv_property_cache.bandwidth_hz / 1000);
+ dib8000_set_bandwidth(fe, state->fe[0]->dtv_property_cache.bandwidth_hz / 1000);
dib8000_set_channel(state, 0, 0);
// restart demod
@@ -1799,17 +1808,16 @@ static int dib8000_tune(struct dvb_frontend *fe)
// never achieved a lock before - wait for timfreq to update
if (state->timf == 0) {
- if (state->fe.dtv_property_cache.isdbt_sb_mode == 1) {
- if (state->fe.dtv_property_cache.isdbt_partial_reception == 0) // Sound Broadcasting mode 1 seg
+ if (state->fe[0]->dtv_property_cache.isdbt_sb_mode == 1) {
+ if (state->fe[0]->dtv_property_cache.isdbt_partial_reception == 0)
msleep(300);
else // Sound Broadcasting mode 3 seg
msleep(500);
} else // 13 seg
msleep(200);
}
- //dump_reg(state);
- if (state->fe.dtv_property_cache.isdbt_sb_mode == 1) {
- if (state->fe.dtv_property_cache.isdbt_partial_reception == 0) { // Sound Broadcasting mode 1 seg
+ if (state->fe[0]->dtv_property_cache.isdbt_sb_mode == 1) {
+ if (state->fe[0]->dtv_property_cache.isdbt_partial_reception == 0) {
/* P_timf_alpha = (13-P_mode) , P_corm_alpha=6, P_corm_thres=0x40 alpha to check on board */
dib8000_write_word(state, 32, ((13 - mode) << 12) | (6 << 8) | 0x40);
@@ -1854,26 +1862,38 @@ static int dib8000_tune(struct dvb_frontend *fe)
static int dib8000_wakeup(struct dvb_frontend *fe)
{
struct dib8000_state *state = fe->demodulator_priv;
+ u8 index_frontend;
+ int ret;
dib8000_set_power_mode(state, DIB8000M_POWER_ALL);
dib8000_set_adc_state(state, DIBX000_ADC_ON);
if (dib8000_set_adc_state(state, DIBX000_SLOW_ADC_ON) != 0)
dprintk("could not start Slow ADC");
+ for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
+ ret = state->fe[index_frontend]->ops.init(state->fe[index_frontend]);
+ if (ret < 0)
+ return ret;
+ }
+
return 0;
}
static int dib8000_sleep(struct dvb_frontend *fe)
{
- struct dib8000_state *st = fe->demodulator_priv;
- if (1) {
- dib8000_set_output_mode(st, OUTMODE_HIGH_Z);
- dib8000_set_power_mode(st, DIB8000M_POWER_INTERFACE_ONLY);
- return dib8000_set_adc_state(st, DIBX000_SLOW_ADC_OFF) | dib8000_set_adc_state(st, DIBX000_ADC_OFF);
- } else {
+ struct dib8000_state *state = fe->demodulator_priv;
+ u8 index_frontend;
+ int ret;
- return 0;
+ for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
+ ret = state->fe[index_frontend]->ops.sleep(state->fe[index_frontend]);
+ if (ret < 0)
+ return ret;
}
+
+ dib8000_set_output_mode(fe, OUTMODE_HIGH_Z);
+ dib8000_set_power_mode(state, DIB8000M_POWER_INTERFACE_ONLY);
+ return dib8000_set_adc_state(state, DIBX000_SLOW_ADC_OFF) | dib8000_set_adc_state(state, DIBX000_ADC_OFF);
}
enum frontend_tune_state dib8000_get_tune_state(struct dvb_frontend *fe)
@@ -1891,16 +1911,40 @@ int dib8000_set_tune_state(struct dvb_frontend *fe, enum frontend_tune_state tun
}
EXPORT_SYMBOL(dib8000_set_tune_state);
-
-
-
static int dib8000_get_frontend(struct dvb_frontend *fe, struct dvb_frontend_parameters *fep)
{
struct dib8000_state *state = fe->demodulator_priv;
u16 i, val = 0;
+ fe_status_t stat;
+ u8 index_frontend, sub_index_frontend;
fe->dtv_property_cache.bandwidth_hz = 6000000;
+ for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
+ state->fe[index_frontend]->ops.read_status(state->fe[index_frontend], &stat);
+ if (stat&FE_HAS_SYNC) {
+ dprintk("TMCC lock on the slave%i", index_frontend);
+ /* synchronize the cache with the other frontends */
+ state->fe[index_frontend]->ops.get_frontend(state->fe[index_frontend], fep);
+ for (sub_index_frontend = 0; (sub_index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[sub_index_frontend] != NULL); sub_index_frontend++) {
+ if (sub_index_frontend != index_frontend) {
+ state->fe[sub_index_frontend]->dtv_property_cache.isdbt_sb_mode = state->fe[index_frontend]->dtv_property_cache.isdbt_sb_mode;
+ state->fe[sub_index_frontend]->dtv_property_cache.inversion = state->fe[index_frontend]->dtv_property_cache.inversion;
+ state->fe[sub_index_frontend]->dtv_property_cache.transmission_mode = state->fe[index_frontend]->dtv_property_cache.transmission_mode;
+ state->fe[sub_index_frontend]->dtv_property_cache.guard_interval = state->fe[index_frontend]->dtv_property_cache.guard_interval;
+ state->fe[sub_index_frontend]->dtv_property_cache.isdbt_partial_reception = state->fe[index_frontend]->dtv_property_cache.isdbt_partial_reception;
+ for (i = 0; i < 3; i++) {
+ state->fe[sub_index_frontend]->dtv_property_cache.layer[i].segment_count = state->fe[index_frontend]->dtv_property_cache.layer[i].segment_count;
+ state->fe[sub_index_frontend]->dtv_property_cache.layer[i].interleaving = state->fe[index_frontend]->dtv_property_cache.layer[i].interleaving;
+ state->fe[sub_index_frontend]->dtv_property_cache.layer[i].fec = state->fe[index_frontend]->dtv_property_cache.layer[i].fec;
+ state->fe[sub_index_frontend]->dtv_property_cache.layer[i].modulation = state->fe[index_frontend]->dtv_property_cache.layer[i].modulation;
+ }
+ }
+ }
+ return 0;
+ }
+ }
+
fe->dtv_property_cache.isdbt_sb_mode = dib8000_read_word(state, 508) & 0x1;
val = dib8000_read_word(state, 570);
@@ -1992,112 +2036,200 @@ static int dib8000_get_frontend(struct dvb_frontend *fe, struct dvb_frontend_par
break;
}
}
+
+ /* synchronize the cache with the other frontends */
+ for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
+ state->fe[index_frontend]->dtv_property_cache.isdbt_sb_mode = fe->dtv_property_cache.isdbt_sb_mode;
+ state->fe[index_frontend]->dtv_property_cache.inversion = fe->dtv_property_cache.inversion;
+ state->fe[index_frontend]->dtv_property_cache.transmission_mode = fe->dtv_property_cache.transmission_mode;
+ state->fe[index_frontend]->dtv_property_cache.guard_interval = fe->dtv_property_cache.guard_interval;
+ state->fe[index_frontend]->dtv_property_cache.isdbt_partial_reception = fe->dtv_property_cache.isdbt_partial_reception;
+ for (i = 0; i < 3; i++) {
+ state->fe[index_frontend]->dtv_property_cache.layer[i].segment_count = fe->dtv_property_cache.layer[i].segment_count;
+ state->fe[index_frontend]->dtv_property_cache.layer[i].interleaving = fe->dtv_property_cache.layer[i].interleaving;
+ state->fe[index_frontend]->dtv_property_cache.layer[i].fec = fe->dtv_property_cache.layer[i].fec;
+ state->fe[index_frontend]->dtv_property_cache.layer[i].modulation = fe->dtv_property_cache.layer[i].modulation;
+ }
+ }
return 0;
}
static int dib8000_set_frontend(struct dvb_frontend *fe, struct dvb_frontend_parameters *fep)
{
struct dib8000_state *state = fe->demodulator_priv;
+ u8 nbr_pending, exit_condition, index_frontend;
+ s8 index_frontend_success = -1;
int time, ret;
+ int time_slave = FE_CALLBACK_TIME_NEVER;
- fe->dtv_property_cache.delivery_system = SYS_ISDBT;
+ if (state->fe[0]->dtv_property_cache.frequency == 0) {
+ dprintk("dib8000: must at least specify frequency ");
+ return 0;
+ }
- dib8000_set_output_mode(state, OUTMODE_HIGH_Z);
+ if (state->fe[0]->dtv_property_cache.bandwidth_hz == 0) {
+ dprintk("dib8000: no bandwidth specified, set to default ");
+ state->fe[0]->dtv_property_cache.bandwidth_hz = 6000000;
+ }
+
+ for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
+ /* synchronization of the cache */
+ state->fe[index_frontend]->dtv_property_cache.delivery_system = SYS_ISDBT;
+ memcpy(&state->fe[index_frontend]->dtv_property_cache, &fe->dtv_property_cache, sizeof(struct dtv_frontend_properties));
+
+ dib8000_set_output_mode(state->fe[index_frontend], OUTMODE_HIGH_Z);
+ if (state->fe[index_frontend]->ops.tuner_ops.set_params)
+ state->fe[index_frontend]->ops.tuner_ops.set_params(state->fe[index_frontend], fep);
- if (fe->ops.tuner_ops.set_params)
- fe->ops.tuner_ops.set_params(fe, fep);
+ dib8000_set_tune_state(state->fe[index_frontend], CT_AGC_START);
+ }
/* start up the AGC */
- state->tune_state = CT_AGC_START;
do {
- time = dib8000_agc_startup(fe);
+ time = dib8000_agc_startup(state->fe[0]);
+ for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
+ time_slave = dib8000_agc_startup(state->fe[index_frontend]);
+ if (time == FE_CALLBACK_TIME_NEVER)
+ time = time_slave;
+ else if ((time_slave != FE_CALLBACK_TIME_NEVER) && (time_slave > time))
+ time = time_slave;
+ }
if (time != FE_CALLBACK_TIME_NEVER)
msleep(time / 10);
else
break;
- } while (state->tune_state != CT_AGC_STOP);
-
- if (state->fe.dtv_property_cache.frequency == 0) {
- dprintk("dib8000: must at least specify frequency ");
- return 0;
- }
-
- if (state->fe.dtv_property_cache.bandwidth_hz == 0) {
- dprintk("dib8000: no bandwidth specified, set to default ");
- state->fe.dtv_property_cache.bandwidth_hz = 6000000;
- }
+ exit_condition = 1;
+ for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
+ if (dib8000_get_tune_state(state->fe[index_frontend]) != CT_AGC_STOP) {
+ exit_condition = 0;
+ break;
+ }
+ }
+ } while (exit_condition == 0);
+
+ for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++)
+ dib8000_set_tune_state(state->fe[index_frontend], CT_DEMOD_START);
+
+ if ((state->fe[0]->dtv_property_cache.delivery_system != SYS_ISDBT) ||
+ (state->fe[0]->dtv_property_cache.inversion == INVERSION_AUTO) ||
+ (state->fe[0]->dtv_property_cache.transmission_mode == TRANSMISSION_MODE_AUTO) ||
+ (state->fe[0]->dtv_property_cache.guard_interval == GUARD_INTERVAL_AUTO) ||
+ (((state->fe[0]->dtv_property_cache.isdbt_layer_enabled & (1 << 0)) != 0) &&
+ (state->fe[0]->dtv_property_cache.layer[0].segment_count != 0xff) &&
+ (state->fe[0]->dtv_property_cache.layer[0].segment_count != 0) &&
+ ((state->fe[0]->dtv_property_cache.layer[0].modulation == QAM_AUTO) ||
+ (state->fe[0]->dtv_property_cache.layer[0].fec == FEC_AUTO))) ||
+ (((state->fe[0]->dtv_property_cache.isdbt_layer_enabled & (1 << 1)) != 0) &&
+ (state->fe[0]->dtv_property_cache.layer[1].segment_count != 0xff) &&
+ (state->fe[0]->dtv_property_cache.layer[1].segment_count != 0) &&
+ ((state->fe[0]->dtv_property_cache.layer[1].modulation == QAM_AUTO) ||
+ (state->fe[0]->dtv_property_cache.layer[1].fec == FEC_AUTO))) ||
+ (((state->fe[0]->dtv_property_cache.isdbt_layer_enabled & (1 << 2)) != 0) &&
+ (state->fe[0]->dtv_property_cache.layer[2].segment_count != 0xff) &&
+ (state->fe[0]->dtv_property_cache.layer[2].segment_count != 0) &&
+ ((state->fe[0]->dtv_property_cache.layer[2].modulation == QAM_AUTO) ||
+ (state->fe[0]->dtv_property_cache.layer[2].fec == FEC_AUTO))) ||
+ (((state->fe[0]->dtv_property_cache.layer[0].segment_count == 0) ||
+ ((state->fe[0]->dtv_property_cache.isdbt_layer_enabled & (1 << 0)) == 0)) &&
+ ((state->fe[0]->dtv_property_cache.layer[1].segment_count == 0) ||
+ ((state->fe[0]->dtv_property_cache.isdbt_layer_enabled & (2 << 0)) == 0)) &&
+ ((state->fe[0]->dtv_property_cache.layer[2].segment_count == 0) || ((state->fe[0]->dtv_property_cache.isdbt_layer_enabled & (3 << 0)) == 0)))) {
+ int i = 80000;
+ u8 found = 0;
+ u8 tune_failed = 0;
+
+ for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
+ dib8000_set_bandwidth(state->fe[index_frontend], fe->dtv_property_cache.bandwidth_hz / 1000);
+ dib8000_autosearch_start(state->fe[index_frontend]);
+ }
- state->tune_state = CT_DEMOD_START;
-
- if ((state->fe.dtv_property_cache.delivery_system != SYS_ISDBT) ||
- (state->fe.dtv_property_cache.inversion == INVERSION_AUTO) ||
- (state->fe.dtv_property_cache.transmission_mode == TRANSMISSION_MODE_AUTO) ||
- (state->fe.dtv_property_cache.guard_interval == GUARD_INTERVAL_AUTO) ||
- (((state->fe.dtv_property_cache.isdbt_layer_enabled & (1 << 0)) != 0) &&
- (state->fe.dtv_property_cache.layer[0].segment_count != 0xff) &&
- (state->fe.dtv_property_cache.layer[0].segment_count != 0) &&
- ((state->fe.dtv_property_cache.layer[0].modulation == QAM_AUTO) ||
- (state->fe.dtv_property_cache.layer[0].fec == FEC_AUTO))) ||
- (((state->fe.dtv_property_cache.isdbt_layer_enabled & (1 << 1)) != 0) &&
- (state->fe.dtv_property_cache.layer[1].segment_count != 0xff) &&
- (state->fe.dtv_property_cache.layer[1].segment_count != 0) &&
- ((state->fe.dtv_property_cache.layer[1].modulation == QAM_AUTO) ||
- (state->fe.dtv_property_cache.layer[1].fec == FEC_AUTO))) ||
- (((state->fe.dtv_property_cache.isdbt_layer_enabled & (1 << 2)) != 0) &&
- (state->fe.dtv_property_cache.layer[2].segment_count != 0xff) &&
- (state->fe.dtv_property_cache.layer[2].segment_count != 0) &&
- ((state->fe.dtv_property_cache.layer[2].modulation == QAM_AUTO) ||
- (state->fe.dtv_property_cache.layer[2].fec == FEC_AUTO))) ||
- (((state->fe.dtv_property_cache.layer[0].segment_count == 0) ||
- ((state->fe.dtv_property_cache.isdbt_layer_enabled & (1 << 0)) == 0)) &&
- ((state->fe.dtv_property_cache.layer[1].segment_count == 0) ||
- ((state->fe.dtv_property_cache.isdbt_layer_enabled & (2 << 0)) == 0)) &&
- ((state->fe.dtv_property_cache.layer[2].segment_count == 0) || ((state->fe.dtv_property_cache.isdbt_layer_enabled & (3 << 0)) == 0)))) {
- int i = 800, found;
-
- dib8000_set_bandwidth(state, fe->dtv_property_cache.bandwidth_hz / 1000);
- dib8000_autosearch_start(fe);
do {
- msleep(10);
- found = dib8000_autosearch_irq(fe);
- } while (found == 0 && i--);
+ msleep(20);
+ nbr_pending = 0;
+ exit_condition = 0; /* 0: tune pending; 1: tune failed; 2:tune success */
+ for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
+ if (((tune_failed >> index_frontend) & 0x1) == 0) {
+ found = dib8000_autosearch_irq(state->fe[index_frontend]);
+ switch (found) {
+ case 0: /* tune pending */
+ nbr_pending++;
+ break;
+ case 2:
+ dprintk("autosearch succeed on the frontend%i", index_frontend);
+ exit_condition = 2;
+ index_frontend_success = index_frontend;
+ break;
+ default:
+ dprintk("unhandled autosearch result");
+ case 1:
+ dprintk("autosearch failed for the frontend%i", index_frontend);
+ break;
+ }
+ }
+ }
- dprintk("Frequency %d Hz, autosearch returns: %d", fep->frequency, found);
+ /* if all tune are done and no success, exit: tune failed */
+ if ((nbr_pending == 0) && (exit_condition == 0))
+ exit_condition = 1;
+ } while ((exit_condition == 0) && i--);
- if (found == 0 || found == 1)
- return 0; // no channel found
+ if (exit_condition == 1) { /* tune failed */
+ dprintk("tune failed");
+ return 0;
+ }
+
+ dprintk("tune success on frontend%i", index_frontend_success);
dib8000_get_frontend(fe, fep);
}
- ret = dib8000_tune(fe);
+ for (index_frontend = 0, ret = 0; (ret >= 0) && (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++)
+ ret = dib8000_tune(state->fe[index_frontend]);
+
+ /* set output mode and diversity input */
+ dib8000_set_output_mode(state->fe[0], state->cfg.output_mode);
+ for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
+ dib8000_set_output_mode(state->fe[index_frontend], OUTMODE_DIVERSITY);
+ dib8000_set_diversity_in(state->fe[index_frontend-1], 1);
+ }
- /* make this a config parameter */
- dib8000_set_output_mode(state, state->cfg.output_mode);
+ /* turn off the diversity of the last chip */
+ dib8000_set_diversity_in(state->fe[index_frontend-1], 0);
return ret;
}
+static u16 dib8000_read_lock(struct dvb_frontend *fe)
+{
+ struct dib8000_state *state = fe->demodulator_priv;
+
+ return dib8000_read_word(state, 568);
+}
+
static int dib8000_read_status(struct dvb_frontend *fe, fe_status_t * stat)
{
struct dib8000_state *state = fe->demodulator_priv;
- u16 lock = dib8000_read_word(state, 568);
+ u16 lock_slave = 0, lock = dib8000_read_word(state, 568);
+ u8 index_frontend;
+
+ for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++)
+ lock_slave |= dib8000_read_lock(state->fe[index_frontend]);
*stat = 0;
- if ((lock >> 13) & 1)
+ if (((lock >> 13) & 1) || ((lock_slave >> 13) & 1))
*stat |= FE_HAS_SIGNAL;
- if ((lock >> 8) & 1) /* Equal */
+ if (((lock >> 8) & 1) || ((lock_slave >> 8) & 1)) /* Equal */
*stat |= FE_HAS_CARRIER;
- if (((lock >> 1) & 0xf) == 0xf) /* TMCC_SYNC */
+ if ((((lock >> 1) & 0xf) == 0xf) || (((lock_slave >> 1) & 0xf) == 0xf)) /* TMCC_SYNC */
*stat |= FE_HAS_SYNC;
- if (((lock >> 12) & 1) && ((lock >> 5) & 7)) /* FEC MPEG */
+ if ((((lock >> 12) & 1) || ((lock_slave >> 12) & 1)) && ((lock >> 5) & 7)) /* FEC MPEG */
*stat |= FE_HAS_LOCK;
- if ((lock >> 12) & 1) {
+ if (((lock >> 12) & 1) || ((lock_slave >> 12) & 1)) {
lock = dib8000_read_word(state, 554); /* Viterbi Layer A */
if (lock & 0x01)
*stat |= FE_HAS_VITERBI;
@@ -2131,44 +2263,120 @@ static int dib8000_read_unc_blocks(struct dvb_frontend *fe, u32 * unc)
static int dib8000_read_signal_strength(struct dvb_frontend *fe, u16 * strength)
{
struct dib8000_state *state = fe->demodulator_priv;
- u16 val = dib8000_read_word(state, 390);
- *strength = 65535 - val;
+ u8 index_frontend;
+ u16 val;
+
+ *strength = 0;
+ for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
+ state->fe[index_frontend]->ops.read_signal_strength(state->fe[index_frontend], &val);
+ if (val > 65535 - *strength)
+ *strength = 65535;
+ else
+ *strength += val;
+ }
+
+ val = 65535 - dib8000_read_word(state, 390);
+ if (val > 65535 - *strength)
+ *strength = 65535;
+ else
+ *strength += val;
return 0;
}
-static int dib8000_read_snr(struct dvb_frontend *fe, u16 * snr)
+static u32 dib8000_get_snr(struct dvb_frontend *fe)
{
struct dib8000_state *state = fe->demodulator_priv;
+ u32 n, s, exp;
u16 val;
- s32 signal_mant, signal_exp, noise_mant, noise_exp;
- u32 result = 0;
val = dib8000_read_word(state, 542);
- noise_mant = (val >> 6) & 0xff;
- noise_exp = (val & 0x3f);
+ n = (val >> 6) & 0xff;
+ exp = (val & 0x3f);
+ if ((exp & 0x20) != 0)
+ exp -= 0x40;
+ n <<= exp+16;
val = dib8000_read_word(state, 543);
- signal_mant = (val >> 6) & 0xff;
- signal_exp = (val & 0x3f);
+ s = (val >> 6) & 0xff;
+ exp = (val & 0x3f);
+ if ((exp & 0x20) != 0)
+ exp -= 0x40;
+ s <<= exp+16;
+
+ if (n > 0) {
+ u32 t = (s/n) << 16;
+ return t + ((s << 16) - n*t) / n;
+ }
+ return 0xffffffff;
+}
- if ((noise_exp & 0x20) != 0)
- noise_exp -= 0x40;
- if ((signal_exp & 0x20) != 0)
- signal_exp -= 0x40;
+static int dib8000_read_snr(struct dvb_frontend *fe, u16 * snr)
+{
+ struct dib8000_state *state = fe->demodulator_priv;
+ u8 index_frontend;
+ u32 snr_master;
- if (signal_mant != 0)
- result = intlog10(2) * 10 * signal_exp + 10 * intlog10(signal_mant);
- else
- result = intlog10(2) * 10 * signal_exp - 100;
- if (noise_mant != 0)
- result -= intlog10(2) * 10 * noise_exp + 10 * intlog10(noise_mant);
+ snr_master = dib8000_get_snr(fe);
+ for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++)
+ snr_master += dib8000_get_snr(state->fe[index_frontend]);
+
+ if (snr_master != 0) {
+ snr_master = 10*intlog10(snr_master>>16);
+ *snr = snr_master / ((1 << 24) / 10);
+ }
else
- result -= intlog10(2) * 10 * noise_exp - 100;
+ *snr = 0;
- *snr = result / ((1 << 24) / 10);
return 0;
}
+int dib8000_set_slave_frontend(struct dvb_frontend *fe, struct dvb_frontend *fe_slave)
+{
+ struct dib8000_state *state = fe->demodulator_priv;
+ u8 index_frontend = 1;
+
+ while ((index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL))
+ index_frontend++;
+ if (index_frontend < MAX_NUMBER_OF_FRONTENDS) {
+ dprintk("set slave fe %p to index %i", fe_slave, index_frontend);
+ state->fe[index_frontend] = fe_slave;
+ return 0;
+ }
+
+ dprintk("too many slave frontend");
+ return -ENOMEM;
+}
+EXPORT_SYMBOL(dib8000_set_slave_frontend);
+
+int dib8000_remove_slave_frontend(struct dvb_frontend *fe)
+{
+ struct dib8000_state *state = fe->demodulator_priv;
+ u8 index_frontend = 1;
+
+ while ((index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL))
+ index_frontend++;
+ if (index_frontend != 1) {
+ dprintk("remove slave fe %p (index %i)", state->fe[index_frontend-1], index_frontend-1);
+ state->fe[index_frontend] = NULL;
+ return 0;
+ }
+
+ dprintk("no frontend to be removed");
+ return -ENODEV;
+}
+EXPORT_SYMBOL(dib8000_remove_slave_frontend);
+
+struct dvb_frontend *dib8000_get_slave_frontend(struct dvb_frontend *fe, int slave_index)
+{
+ struct dib8000_state *state = fe->demodulator_priv;
+
+ if (slave_index >= MAX_NUMBER_OF_FRONTENDS)
+ return NULL;
+ return state->fe[slave_index];
+}
+EXPORT_SYMBOL(dib8000_get_slave_frontend);
+
+
int dib8000_i2c_enumeration(struct i2c_adapter *host, int no_of_demods, u8 default_addr, u8 first_addr)
{
int k = 0;
@@ -2227,7 +2435,13 @@ static int dib8000_fe_get_tune_settings(struct dvb_frontend *fe, struct dvb_fron
static void dib8000_release(struct dvb_frontend *fe)
{
struct dib8000_state *st = fe->demodulator_priv;
+ u8 index_frontend;
+
+ for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (st->fe[index_frontend] != NULL); index_frontend++)
+ dvb_frontend_detach(st->fe[index_frontend]);
+
dibx000_exit_i2c_master(&st->i2c_master);
+ kfree(st->fe[0]);
kfree(st);
}
@@ -2242,19 +2456,19 @@ EXPORT_SYMBOL(dib8000_get_i2c_master);
int dib8000_pid_filter_ctrl(struct dvb_frontend *fe, u8 onoff)
{
struct dib8000_state *st = fe->demodulator_priv;
- u16 val = dib8000_read_word(st, 299) & 0xffef;
- val |= (onoff & 0x1) << 4;
+ u16 val = dib8000_read_word(st, 299) & 0xffef;
+ val |= (onoff & 0x1) << 4;
- dprintk("pid filter enabled %d", onoff);
- return dib8000_write_word(st, 299, val);
+ dprintk("pid filter enabled %d", onoff);
+ return dib8000_write_word(st, 299, val);
}
EXPORT_SYMBOL(dib8000_pid_filter_ctrl);
int dib8000_pid_filter(struct dvb_frontend *fe, u8 id, u16 pid, u8 onoff)
{
struct dib8000_state *st = fe->demodulator_priv;
- dprintk("Index %x, PID %d, OnOff %d", id, pid, onoff);
- return dib8000_write_word(st, 305 + id, onoff ? (1 << 13) | pid : 0);
+ dprintk("Index %x, PID %d, OnOff %d", id, pid, onoff);
+ return dib8000_write_word(st, 305 + id, onoff ? (1 << 13) | pid : 0);
}
EXPORT_SYMBOL(dib8000_pid_filter);
@@ -2298,6 +2512,9 @@ struct dvb_frontend *dib8000_attach(struct i2c_adapter *i2c_adap, u8 i2c_addr, s
state = kzalloc(sizeof(struct dib8000_state), GFP_KERNEL);
if (state == NULL)
return NULL;
+ fe = kzalloc(sizeof(struct dvb_frontend), GFP_KERNEL);
+ if (fe == NULL)
+ goto error;
memcpy(&state->cfg, cfg, sizeof(struct dib8000_config));
state->i2c.adap = i2c_adap;
@@ -2311,9 +2528,9 @@ struct dvb_frontend *dib8000_attach(struct i2c_adapter *i2c_adap, u8 i2c_addr, s
if ((state->cfg.output_mode != OUTMODE_MPEG2_SERIAL) && (state->cfg.output_mode != OUTMODE_MPEG2_PAR_GATED_CLK))
state->cfg.output_mode = OUTMODE_MPEG2_FIFO;
- fe = &state->fe;
+ state->fe[0] = fe;
fe->demodulator_priv = state;
- memcpy(&state->fe.ops, &dib8000_ops, sizeof(struct dvb_frontend_ops));
+ memcpy(&state->fe[0]->ops, &dib8000_ops, sizeof(struct dvb_frontend_ops));
state->timf_default = cfg->pll->timf;
diff --git a/drivers/media/dvb/frontends/dib8000.h b/drivers/media/dvb/frontends/dib8000.h
index e0a9ded11df..617f9eba3a0 100644
--- a/drivers/media/dvb/frontends/dib8000.h
+++ b/drivers/media/dvb/frontends/dib8000.h
@@ -50,6 +50,9 @@ extern int dib8000_set_tune_state(struct dvb_frontend *fe, enum frontend_tune_st
extern enum frontend_tune_state dib8000_get_tune_state(struct dvb_frontend *fe);
extern void dib8000_pwm_agc_reset(struct dvb_frontend *fe);
extern s32 dib8000_get_adc_power(struct dvb_frontend *fe, u8 mode);
+extern int dib8000_set_slave_frontend(struct dvb_frontend *fe, struct dvb_frontend *fe_slave);
+extern int dib8000_remove_slave_frontend(struct dvb_frontend *fe);
+extern struct dvb_frontend *dib8000_get_slave_frontend(struct dvb_frontend *fe, int slave_index);
#else
static inline struct dvb_frontend *dib8000_attach(struct i2c_adapter *i2c_adap, u8 i2c_addr, struct dib8000_config *cfg)
{
@@ -111,6 +114,23 @@ static inline s32 dib8000_get_adc_power(struct dvb_frontend *fe, u8 mode)
printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
return 0;
}
+static inline int dib8000_set_slave_frontend(struct dvb_frontend *fe, struct dvb_frontend *fe_slave)
+{
+ printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
+ return -ENODEV;
+}
+
+int dib8000_remove_slave_frontend(struct dvb_frontend *fe)
+{
+ printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
+ return -ENODEV;
+}
+
+static inline struct dvb_frontend *dib8000_get_slave_frontend(struct dvb_frontend *fe, int slave_index)
+{
+ printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
+ return NULL;
+}
#endif
#endif
diff --git a/drivers/media/dvb/frontends/dib9000.c b/drivers/media/dvb/frontends/dib9000.c
new file mode 100644
index 00000000000..91518761a2d
--- /dev/null
+++ b/drivers/media/dvb/frontends/dib9000.c
@@ -0,0 +1,2351 @@
+/*
+ * Linux-DVB Driver for DiBcom's DiB9000 and demodulator-family.
+ *
+ * Copyright (C) 2005-10 DiBcom (http://www.dibcom.fr/)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation, version 2.
+ */
+#include <linux/kernel.h>
+#include <linux/i2c.h>
+#include <linux/mutex.h>
+
+#include "dvb_math.h"
+#include "dvb_frontend.h"
+
+#include "dib9000.h"
+#include "dibx000_common.h"
+
+static int debug;
+module_param(debug, int, 0644);
+MODULE_PARM_DESC(debug, "turn on debugging (default: 0)");
+
+#define dprintk(args...) do { if (debug) { printk(KERN_DEBUG "DiB9000: "); printk(args); printk("\n"); } } while (0)
+#define MAX_NUMBER_OF_FRONTENDS 6
+
+struct i2c_device {
+ struct i2c_adapter *i2c_adap;
+ u8 i2c_addr;
+};
+
+/* lock */
+#define DIB_LOCK struct mutex
+#define DibAcquireLock(lock) do { if (mutex_lock_interruptible(lock) < 0) dprintk("could not get the lock"); } while (0)
+#define DibReleaseLock(lock) mutex_unlock(lock)
+#define DibInitLock(lock) mutex_init(lock)
+#define DibFreeLock(lock)
+
+struct dib9000_state {
+ struct i2c_device i2c;
+
+ struct dibx000_i2c_master i2c_master;
+ struct i2c_adapter tuner_adap;
+ struct i2c_adapter component_bus;
+
+ u16 revision;
+ u8 reg_offs;
+
+ enum frontend_tune_state tune_state;
+ u32 status;
+ struct dvb_frontend_parametersContext channel_status;
+
+ u8 fe_id;
+
+#define DIB9000_GPIO_DEFAULT_DIRECTIONS 0xffff
+ u16 gpio_dir;
+#define DIB9000_GPIO_DEFAULT_VALUES 0x0000
+ u16 gpio_val;
+#define DIB9000_GPIO_DEFAULT_PWM_POS 0xffff
+ u16 gpio_pwm_pos;
+
+ union { /* common for all chips */
+ struct {
+ u8 mobile_mode:1;
+ } host;
+
+ struct {
+ struct dib9000_fe_memory_map {
+ u16 addr;
+ u16 size;
+ } fe_mm[18];
+ u8 memcmd;
+
+ DIB_LOCK mbx_if_lock; /* to protect read/write operations */
+ DIB_LOCK mbx_lock; /* to protect the whole mailbox handling */
+
+ DIB_LOCK mem_lock; /* to protect the memory accesses */
+ DIB_LOCK mem_mbx_lock; /* to protect the memory-based mailbox */
+
+#define MBX_MAX_WORDS (256 - 200 - 2)
+#define DIB9000_MSG_CACHE_SIZE 2
+ u16 message_cache[DIB9000_MSG_CACHE_SIZE][MBX_MAX_WORDS];
+ u8 fw_is_running;
+ } risc;
+ } platform;
+
+ union { /* common for all platforms */
+ struct {
+ struct dib9000_config cfg;
+ } d9;
+ } chip;
+
+ struct dvb_frontend *fe[MAX_NUMBER_OF_FRONTENDS];
+ u16 component_bus_speed;
+};
+
+u32 fe_info[44] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0
+};
+
+enum dib9000_power_mode {
+ DIB9000_POWER_ALL = 0,
+
+ DIB9000_POWER_NO,
+ DIB9000_POWER_INTERF_ANALOG_AGC,
+ DIB9000_POWER_COR4_DINTLV_ICIRM_EQUAL_CFROD,
+ DIB9000_POWER_COR4_CRY_ESRAM_MOUT_NUD,
+ DIB9000_POWER_INTERFACE_ONLY,
+};
+
+enum dib9000_out_messages {
+ OUT_MSG_HBM_ACK,
+ OUT_MSG_HOST_BUF_FAIL,
+ OUT_MSG_REQ_VERSION,
+ OUT_MSG_BRIDGE_I2C_W,
+ OUT_MSG_BRIDGE_I2C_R,
+ OUT_MSG_BRIDGE_APB_W,
+ OUT_MSG_BRIDGE_APB_R,
+ OUT_MSG_SCAN_CHANNEL,
+ OUT_MSG_MONIT_DEMOD,
+ OUT_MSG_CONF_GPIO,
+ OUT_MSG_DEBUG_HELP,
+ OUT_MSG_SUBBAND_SEL,
+ OUT_MSG_ENABLE_TIME_SLICE,
+ OUT_MSG_FE_FW_DL,
+ OUT_MSG_FE_CHANNEL_SEARCH,
+ OUT_MSG_FE_CHANNEL_TUNE,
+ OUT_MSG_FE_SLEEP,
+ OUT_MSG_FE_SYNC,
+ OUT_MSG_CTL_MONIT,
+
+ OUT_MSG_CONF_SVC,
+ OUT_MSG_SET_HBM,
+ OUT_MSG_INIT_DEMOD,
+ OUT_MSG_ENABLE_DIVERSITY,
+ OUT_MSG_SET_OUTPUT_MODE,
+ OUT_MSG_SET_PRIORITARY_CHANNEL,
+ OUT_MSG_ACK_FRG,
+ OUT_MSG_INIT_PMU,
+};
+
+enum dib9000_in_messages {
+ IN_MSG_DATA,
+ IN_MSG_FRAME_INFO,
+ IN_MSG_CTL_MONIT,
+ IN_MSG_ACK_FREE_ITEM,
+ IN_MSG_DEBUG_BUF,
+ IN_MSG_MPE_MONITOR,
+ IN_MSG_RAWTS_MONITOR,
+ IN_MSG_END_BRIDGE_I2C_RW,
+ IN_MSG_END_BRIDGE_APB_RW,
+ IN_MSG_VERSION,
+ IN_MSG_END_OF_SCAN,
+ IN_MSG_MONIT_DEMOD,
+ IN_MSG_ERROR,
+ IN_MSG_FE_FW_DL_DONE,
+ IN_MSG_EVENT,
+ IN_MSG_ACK_CHANGE_SVC,
+ IN_MSG_HBM_PROF,
+};
+
+/* memory_access requests */
+#define FE_MM_W_CHANNEL 0
+#define FE_MM_W_FE_INFO 1
+#define FE_MM_RW_SYNC 2
+
+#define FE_SYNC_CHANNEL 1
+#define FE_SYNC_W_GENERIC_MONIT 2
+#define FE_SYNC_COMPONENT_ACCESS 3
+
+#define FE_MM_R_CHANNEL_SEARCH_STATE 3
+#define FE_MM_R_CHANNEL_UNION_CONTEXT 4
+#define FE_MM_R_FE_INFO 5
+#define FE_MM_R_FE_MONITOR 6
+
+#define FE_MM_W_CHANNEL_HEAD 7
+#define FE_MM_W_CHANNEL_UNION 8
+#define FE_MM_W_CHANNEL_CONTEXT 9
+#define FE_MM_R_CHANNEL_UNION 10
+#define FE_MM_R_CHANNEL_CONTEXT 11
+#define FE_MM_R_CHANNEL_TUNE_STATE 12
+
+#define FE_MM_R_GENERIC_MONITORING_SIZE 13
+#define FE_MM_W_GENERIC_MONITORING 14
+#define FE_MM_R_GENERIC_MONITORING 15
+
+#define FE_MM_W_COMPONENT_ACCESS 16
+#define FE_MM_RW_COMPONENT_ACCESS_BUFFER 17
+static int dib9000_risc_apb_access_read(struct dib9000_state *state, u32 address, u16 attribute, const u8 * tx, u32 txlen, u8 * b, u32 len);
+static int dib9000_risc_apb_access_write(struct dib9000_state *state, u32 address, u16 attribute, const u8 * b, u32 len);
+
+static u16 to_fw_output_mode(u16 mode)
+{
+ switch (mode) {
+ case OUTMODE_HIGH_Z:
+ return 0;
+ case OUTMODE_MPEG2_PAR_GATED_CLK:
+ return 4;
+ case OUTMODE_MPEG2_PAR_CONT_CLK:
+ return 8;
+ case OUTMODE_MPEG2_SERIAL:
+ return 16;
+ case OUTMODE_DIVERSITY:
+ return 128;
+ case OUTMODE_MPEG2_FIFO:
+ return 2;
+ case OUTMODE_ANALOG_ADC:
+ return 1;
+ default:
+ return 0;
+ }
+}
+
+static u16 dib9000_read16_attr(struct dib9000_state *state, u16 reg, u8 * b, u32 len, u16 attribute)
+{
+ u32 chunk_size = 126;
+ u32 l;
+ int ret;
+ u8 wb[2] = { reg >> 8, reg & 0xff };
+ struct i2c_msg msg[2] = {
+ {.addr = state->i2c.i2c_addr >> 1, .flags = 0, .buf = wb, .len = 2},
+ {.addr = state->i2c.i2c_addr >> 1, .flags = I2C_M_RD, .buf = b, .len = len},
+ };
+
+ if (state->platform.risc.fw_is_running && (reg < 1024))
+ return dib9000_risc_apb_access_read(state, reg, attribute, NULL, 0, b, len);
+
+ if (attribute & DATA_BUS_ACCESS_MODE_8BIT)
+ wb[0] |= (1 << 5);
+ if (attribute & DATA_BUS_ACCESS_MODE_NO_ADDRESS_INCREMENT)
+ wb[0] |= (1 << 4);
+
+ do {
+ l = len < chunk_size ? len : chunk_size;
+ msg[1].len = l;
+ msg[1].buf = b;
+ ret = i2c_transfer(state->i2c.i2c_adap, msg, 2) != 2 ? -EREMOTEIO : 0;
+ if (ret != 0) {
+ dprintk("i2c read error on %d", reg);
+ return -EREMOTEIO;
+ }
+
+ b += l;
+ len -= l;
+
+ if (!(attribute & DATA_BUS_ACCESS_MODE_NO_ADDRESS_INCREMENT))
+ reg += l / 2;
+ } while ((ret == 0) && len);
+
+ return 0;
+}
+
+static u16 dib9000_i2c_read16(struct i2c_device *i2c, u16 reg)
+{
+ u8 b[2];
+ u8 wb[2] = { reg >> 8, reg & 0xff };
+ struct i2c_msg msg[2] = {
+ {.addr = i2c->i2c_addr >> 1, .flags = 0, .buf = wb, .len = 2},
+ {.addr = i2c->i2c_addr >> 1, .flags = I2C_M_RD, .buf = b, .len = 2},
+ };
+
+ if (i2c_transfer(i2c->i2c_adap, msg, 2) != 2) {
+ dprintk("read register %x error", reg);
+ return 0;
+ }
+
+ return (b[0] << 8) | b[1];
+}
+
+static inline u16 dib9000_read_word(struct dib9000_state *state, u16 reg)
+{
+ u8 b[2];
+ if (dib9000_read16_attr(state, reg, b, 2, 0) != 0)
+ return 0;
+ return (b[0] << 8 | b[1]);
+}
+
+static inline u16 dib9000_read_word_attr(struct dib9000_state *state, u16 reg, u16 attribute)
+{
+ u8 b[2];
+ if (dib9000_read16_attr(state, reg, b, 2, attribute) != 0)
+ return 0;
+ return (b[0] << 8 | b[1]);
+}
+
+#define dib9000_read16_noinc_attr(state, reg, b, len, attribute) dib9000_read16_attr(state, reg, b, len, (attribute) | DATA_BUS_ACCESS_MODE_NO_ADDRESS_INCREMENT)
+
+static u16 dib9000_write16_attr(struct dib9000_state *state, u16 reg, const u8 * buf, u32 len, u16 attribute)
+{
+ u8 b[255];
+ u32 chunk_size = 126;
+ u32 l;
+ int ret;
+
+ struct i2c_msg msg = {
+ .addr = state->i2c.i2c_addr >> 1, .flags = 0, .buf = b, .len = len + 2
+ };
+
+ if (state->platform.risc.fw_is_running && (reg < 1024)) {
+ if (dib9000_risc_apb_access_write
+ (state, reg, DATA_BUS_ACCESS_MODE_16BIT | DATA_BUS_ACCESS_MODE_NO_ADDRESS_INCREMENT | attribute, buf, len) != 0)
+ return -EINVAL;
+ return 0;
+ }
+
+ b[0] = (reg >> 8) & 0xff;
+ b[1] = (reg) & 0xff;
+
+ if (attribute & DATA_BUS_ACCESS_MODE_8BIT)
+ b[0] |= (1 << 5);
+ if (attribute & DATA_BUS_ACCESS_MODE_NO_ADDRESS_INCREMENT)
+ b[0] |= (1 << 4);
+
+ do {
+ l = len < chunk_size ? len : chunk_size;
+ msg.len = l + 2;
+ memcpy(&b[2], buf, l);
+
+ ret = i2c_transfer(state->i2c.i2c_adap, &msg, 1) != 1 ? -EREMOTEIO : 0;
+
+ buf += l;
+ len -= l;
+
+ if (!(attribute & DATA_BUS_ACCESS_MODE_NO_ADDRESS_INCREMENT))
+ reg += l / 2;
+ } while ((ret == 0) && len);
+
+ return ret;
+}
+
+static int dib9000_i2c_write16(struct i2c_device *i2c, u16 reg, u16 val)
+{
+ u8 b[4] = { (reg >> 8) & 0xff, reg & 0xff, (val >> 8) & 0xff, val & 0xff };
+ struct i2c_msg msg = {
+ .addr = i2c->i2c_addr >> 1, .flags = 0, .buf = b, .len = 4
+ };
+
+ return i2c_transfer(i2c->i2c_adap, &msg, 1) != 1 ? -EREMOTEIO : 0;
+}
+
+static inline int dib9000_write_word(struct dib9000_state *state, u16 reg, u16 val)
+{
+ u8 b[2] = { val >> 8, val & 0xff };
+ return dib9000_write16_attr(state, reg, b, 2, 0);
+}
+
+static inline int dib9000_write_word_attr(struct dib9000_state *state, u16 reg, u16 val, u16 attribute)
+{
+ u8 b[2] = { val >> 8, val & 0xff };
+ return dib9000_write16_attr(state, reg, b, 2, attribute);
+}
+
+#define dib9000_write(state, reg, buf, len) dib9000_write16_attr(state, reg, buf, len, 0)
+#define dib9000_write16_noinc(state, reg, buf, len) dib9000_write16_attr(state, reg, buf, len, DATA_BUS_ACCESS_MODE_NO_ADDRESS_INCREMENT)
+#define dib9000_write16_noinc_attr(state, reg, buf, len, attribute) dib9000_write16_attr(state, reg, buf, len, DATA_BUS_ACCESS_MODE_NO_ADDRESS_INCREMENT | (attribute))
+
+#define dib9000_mbx_send(state, id, data, len) dib9000_mbx_send_attr(state, id, data, len, 0)
+#define dib9000_mbx_get_message(state, id, msg, len) dib9000_mbx_get_message_attr(state, id, msg, len, 0)
+
+#define MAC_IRQ (1 << 1)
+#define IRQ_POL_MSK (1 << 4)
+
+#define dib9000_risc_mem_read_chunks(state, b, len) dib9000_read16_attr(state, 1063, b, len, DATA_BUS_ACCESS_MODE_8BIT | DATA_BUS_ACCESS_MODE_NO_ADDRESS_INCREMENT)
+#define dib9000_risc_mem_write_chunks(state, buf, len) dib9000_write16_attr(state, 1063, buf, len, DATA_BUS_ACCESS_MODE_8BIT | DATA_BUS_ACCESS_MODE_NO_ADDRESS_INCREMENT)
+
+static void dib9000_risc_mem_setup_cmd(struct dib9000_state *state, u32 addr, u32 len, u8 reading)
+{
+ u8 b[14] = { 0 };
+
+/* dprintk("%d memcmd: %d %d %d\n", state->fe_id, addr, addr+len, len); */
+/* b[0] = 0 << 7; */
+ b[1] = 1;
+
+/* b[2] = 0; */
+/* b[3] = 0; */
+ b[4] = (u8) (addr >> 8);
+ b[5] = (u8) (addr & 0xff);
+
+/* b[10] = 0; */
+/* b[11] = 0; */
+ b[12] = (u8) (addr >> 8);
+ b[13] = (u8) (addr & 0xff);
+
+ addr += len;
+/* b[6] = 0; */
+/* b[7] = 0; */
+ b[8] = (u8) (addr >> 8);
+ b[9] = (u8) (addr & 0xff);
+
+ dib9000_write(state, 1056, b, 14);
+ if (reading)
+ dib9000_write_word(state, 1056, (1 << 15) | 1);
+ state->platform.risc.memcmd = -1; /* if it was called directly reset it - to force a future setup-call to set it */
+}
+
+static void dib9000_risc_mem_setup(struct dib9000_state *state, u8 cmd)
+{
+ struct dib9000_fe_memory_map *m = &state->platform.risc.fe_mm[cmd & 0x7f];
+ /* decide whether we need to "refresh" the memory controller */
+ if (state->platform.risc.memcmd == cmd && /* same command */
+ !(cmd & 0x80 && m->size < 67)) /* and we do not want to read something with less than 67 bytes looping - working around a bug in the memory controller */
+ return;
+ dib9000_risc_mem_setup_cmd(state, m->addr, m->size, cmd & 0x80);
+ state->platform.risc.memcmd = cmd;
+}
+
+static int dib9000_risc_mem_read(struct dib9000_state *state, u8 cmd, u8 * b, u16 len)
+{
+ if (!state->platform.risc.fw_is_running)
+ return -EIO;
+
+ DibAcquireLock(&state->platform.risc.mem_lock);
+ dib9000_risc_mem_setup(state, cmd | 0x80);
+ dib9000_risc_mem_read_chunks(state, b, len);
+ DibReleaseLock(&state->platform.risc.mem_lock);
+ return 0;
+}
+
+static int dib9000_risc_mem_write(struct dib9000_state *state, u8 cmd, const u8 * b)
+{
+ struct dib9000_fe_memory_map *m = &state->platform.risc.fe_mm[cmd];
+ if (!state->platform.risc.fw_is_running)
+ return -EIO;
+
+ DibAcquireLock(&state->platform.risc.mem_lock);
+ dib9000_risc_mem_setup(state, cmd);
+ dib9000_risc_mem_write_chunks(state, b, m->size);
+ DibReleaseLock(&state->platform.risc.mem_lock);
+ return 0;
+}
+
+static int dib9000_firmware_download(struct dib9000_state *state, u8 risc_id, u16 key, const u8 * code, u32 len)
+{
+ u16 offs;
+
+ if (risc_id == 1)
+ offs = 16;
+ else
+ offs = 0;
+
+ /* config crtl reg */
+ dib9000_write_word(state, 1024 + offs, 0x000f);
+ dib9000_write_word(state, 1025 + offs, 0);
+ dib9000_write_word(state, 1031 + offs, key);
+
+ dprintk("going to download %dB of microcode", len);
+ if (dib9000_write16_noinc(state, 1026 + offs, (u8 *) code, (u16) len) != 0) {
+ dprintk("error while downloading microcode for RISC %c", 'A' + risc_id);
+ return -EIO;
+ }
+
+ dprintk("Microcode for RISC %c loaded", 'A' + risc_id);
+
+ return 0;
+}
+
+static int dib9000_mbx_host_init(struct dib9000_state *state, u8 risc_id)
+{
+ u16 mbox_offs;
+ u16 reset_reg;
+ u16 tries = 1000;
+
+ if (risc_id == 1)
+ mbox_offs = 16;
+ else
+ mbox_offs = 0;
+
+ /* Reset mailbox */
+ dib9000_write_word(state, 1027 + mbox_offs, 0x8000);
+
+ /* Read reset status */
+ do {
+ reset_reg = dib9000_read_word(state, 1027 + mbox_offs);
+ msleep(100);
+ } while ((reset_reg & 0x8000) && --tries);
+
+ if (reset_reg & 0x8000) {
+ dprintk("MBX: init ERROR, no response from RISC %c", 'A' + risc_id);
+ return -EIO;
+ }
+ dprintk("MBX: initialized");
+ return 0;
+}
+
+#define MAX_MAILBOX_TRY 100
+static int dib9000_mbx_send_attr(struct dib9000_state *state, u8 id, u16 * data, u8 len, u16 attr)
+{
+ u8 *d, b[2];
+ u16 tmp;
+ u16 size;
+ u32 i;
+ int ret = 0;
+
+ if (!state->platform.risc.fw_is_running)
+ return -EINVAL;
+
+ DibAcquireLock(&state->platform.risc.mbx_if_lock);
+ tmp = MAX_MAILBOX_TRY;
+ do {
+ size = dib9000_read_word_attr(state, 1043, attr) & 0xff;
+ if ((size + len + 1) > MBX_MAX_WORDS && --tmp) {
+ dprintk("MBX: RISC mbx full, retrying");
+ msleep(100);
+ } else
+ break;
+ } while (1);
+
+ /*dprintk( "MBX: size: %d", size); */
+
+ if (tmp == 0) {
+ ret = -EINVAL;
+ goto out;
+ }
+#ifdef DUMP_MSG
+ dprintk("--> %02x %d ", id, len + 1);
+ for (i = 0; i < len; i++)
+ dprintk("%04x ", data[i]);
+ dprintk("\n");
+#endif
+
+ /* byte-order conversion - works on big (where it is not necessary) or little endian */
+ d = (u8 *) data;
+ for (i = 0; i < len; i++) {
+ tmp = data[i];
+ *d++ = tmp >> 8;
+ *d++ = tmp & 0xff;
+ }
+
+ /* write msg */
+ b[0] = id;
+ b[1] = len + 1;
+ if (dib9000_write16_noinc_attr(state, 1045, b, 2, attr) != 0 || dib9000_write16_noinc_attr(state, 1045, (u8 *) data, len * 2, attr) != 0) {
+ ret = -EIO;
+ goto out;
+ }
+
+ /* update register nb_mes_in_RX */
+ ret = (u8) dib9000_write_word_attr(state, 1043, 1 << 14, attr);
+
+out:
+ DibReleaseLock(&state->platform.risc.mbx_if_lock);
+
+ return ret;
+}
+
+static u8 dib9000_mbx_read(struct dib9000_state *state, u16 * data, u8 risc_id, u16 attr)
+{
+#ifdef DUMP_MSG
+ u16 *d = data;
+#endif
+
+ u16 tmp, i;
+ u8 size;
+ u8 mc_base;
+
+ if (!state->platform.risc.fw_is_running)
+ return 0;
+
+ DibAcquireLock(&state->platform.risc.mbx_if_lock);
+ if (risc_id == 1)
+ mc_base = 16;
+ else
+ mc_base = 0;
+
+ /* Length and type in the first word */
+ *data = dib9000_read_word_attr(state, 1029 + mc_base, attr);
+
+ size = *data & 0xff;
+ if (size <= MBX_MAX_WORDS) {
+ data++;
+ size--; /* Initial word already read */
+
+ dib9000_read16_noinc_attr(state, 1029 + mc_base, (u8 *) data, size * 2, attr);
+
+ /* to word conversion */
+ for (i = 0; i < size; i++) {
+ tmp = *data;
+ *data = (tmp >> 8) | (tmp << 8);
+ data++;
+ }
+
+#ifdef DUMP_MSG
+ dprintk("<-- ");
+ for (i = 0; i < size + 1; i++)
+ dprintk("%04x ", d[i]);
+ dprintk("\n");
+#endif
+ } else {
+ dprintk("MBX: message is too big for message cache (%d), flushing message", size);
+ size--; /* Initial word already read */
+ while (size--)
+ dib9000_read16_noinc_attr(state, 1029 + mc_base, (u8 *) data, 2, attr);
+ }
+ /* Update register nb_mes_in_TX */
+ dib9000_write_word_attr(state, 1028 + mc_base, 1 << 14, attr);
+
+ DibReleaseLock(&state->platform.risc.mbx_if_lock);
+
+ return size + 1;
+}
+
+static int dib9000_risc_debug_buf(struct dib9000_state *state, u16 * data, u8 size)
+{
+ u32 ts = data[1] << 16 | data[0];
+ char *b = (char *)&data[2];
+
+ b[2 * (size - 2) - 1] = '\0'; /* Bullet proof the buffer */
+ if (*b == '~') {
+ b++;
+ dprintk(b);
+ } else
+ dprintk("RISC%d: %d.%04d %s", state->fe_id, ts / 10000, ts % 10000, *b ? b : "<emtpy>");
+ return 1;
+}
+
+static int dib9000_mbx_fetch_to_cache(struct dib9000_state *state, u16 attr)
+{
+ int i;
+ u8 size;
+ u16 *block;
+ /* find a free slot */
+ for (i = 0; i < DIB9000_MSG_CACHE_SIZE; i++) {
+ block = state->platform.risc.message_cache[i];
+ if (*block == 0) {
+ size = dib9000_mbx_read(state, block, 1, attr);
+
+/* dprintk( "MBX: fetched %04x message to cache", *block); */
+
+ switch (*block >> 8) {
+ case IN_MSG_DEBUG_BUF:
+ dib9000_risc_debug_buf(state, block + 1, size); /* debug-messages are going to be printed right away */
+ *block = 0; /* free the block */
+ break;
+#if 0
+ case IN_MSG_DATA: /* FE-TRACE */
+ dib9000_risc_data_process(state, block + 1, size);
+ *block = 0;
+ break;
+#endif
+ default:
+ break;
+ }
+
+ return 1;
+ }
+ }
+ dprintk("MBX: no free cache-slot found for new message...");
+ return -1;
+}
+
+static u8 dib9000_mbx_count(struct dib9000_state *state, u8 risc_id, u16 attr)
+{
+ if (risc_id == 0)
+ return (u8) (dib9000_read_word_attr(state, 1028, attr) >> 10) & 0x1f; /* 5 bit field */
+ else
+ return (u8) (dib9000_read_word_attr(state, 1044, attr) >> 8) & 0x7f; /* 7 bit field */
+}
+
+static int dib9000_mbx_process(struct dib9000_state *state, u16 attr)
+{
+ int ret = 0;
+ u16 tmp;
+
+ if (!state->platform.risc.fw_is_running)
+ return -1;
+
+ DibAcquireLock(&state->platform.risc.mbx_lock);
+
+ if (dib9000_mbx_count(state, 1, attr)) /* 1=RiscB */
+ ret = dib9000_mbx_fetch_to_cache(state, attr);
+
+ tmp = dib9000_read_word_attr(state, 1229, attr); /* Clear the IRQ */
+/* if (tmp) */
+/* dprintk( "cleared IRQ: %x", tmp); */
+ DibReleaseLock(&state->platform.risc.mbx_lock);
+
+ return ret;
+}
+
+static int dib9000_mbx_get_message_attr(struct dib9000_state *state, u16 id, u16 * msg, u8 * size, u16 attr)
+{
+ u8 i;
+ u16 *block;
+ u16 timeout = 30;
+
+ *msg = 0;
+ do {
+ /* dib9000_mbx_get_from_cache(); */
+ for (i = 0; i < DIB9000_MSG_CACHE_SIZE; i++) {
+ block = state->platform.risc.message_cache[i];
+ if ((*block >> 8) == id) {
+ *size = (*block & 0xff) - 1;
+ memcpy(msg, block + 1, (*size) * 2);
+ *block = 0; /* free the block */
+ i = 0; /* signal that we found a message */
+ break;
+ }
+ }
+
+ if (i == 0)
+ break;
+
+ if (dib9000_mbx_process(state, attr) == -1) /* try to fetch one message - if any */
+ return -1;
+
+ } while (--timeout);
+
+ if (timeout == 0) {
+ dprintk("waiting for message %d timed out", id);
+ return -1;
+ }
+
+ return i == 0;
+}
+
+static int dib9000_risc_check_version(struct dib9000_state *state)
+{
+ u8 r[4];
+ u8 size;
+ u16 fw_version = 0;
+
+ if (dib9000_mbx_send(state, OUT_MSG_REQ_VERSION, &fw_version, 1) != 0)
+ return -EIO;
+
+ if (dib9000_mbx_get_message(state, IN_MSG_VERSION, (u16 *) r, &size) < 0)
+ return -EIO;
+
+ fw_version = (r[0] << 8) | r[1];
+ dprintk("RISC: ver: %d.%02d (IC: %d)", fw_version >> 10, fw_version & 0x3ff, (r[2] << 8) | r[3]);
+
+ if ((fw_version >> 10) != 7)
+ return -EINVAL;
+
+ switch (fw_version & 0x3ff) {
+ case 11:
+ case 12:
+ case 14:
+ case 15:
+ case 16:
+ case 17:
+ break;
+ default:
+ dprintk("RISC: invalid firmware version");
+ return -EINVAL;
+ }
+
+ dprintk("RISC: valid firmware version");
+ return 0;
+}
+
+static int dib9000_fw_boot(struct dib9000_state *state, const u8 * codeA, u32 lenA, const u8 * codeB, u32 lenB)
+{
+ /* Reconfig pool mac ram */
+ dib9000_write_word(state, 1225, 0x02); /* A: 8k C, 4 k D - B: 32k C 6 k D - IRAM 96k */
+ dib9000_write_word(state, 1226, 0x05);
+
+ /* Toggles IP crypto to Host APB interface. */
+ dib9000_write_word(state, 1542, 1);
+
+ /* Set jump and no jump in the dma box */
+ dib9000_write_word(state, 1074, 0);
+ dib9000_write_word(state, 1075, 0);
+
+ /* Set MAC as APB Master. */
+ dib9000_write_word(state, 1237, 0);
+
+ /* Reset the RISCs */
+ if (codeA != NULL)
+ dib9000_write_word(state, 1024, 2);
+ else
+ dib9000_write_word(state, 1024, 15);
+ if (codeB != NULL)
+ dib9000_write_word(state, 1040, 2);
+
+ if (codeA != NULL)
+ dib9000_firmware_download(state, 0, 0x1234, codeA, lenA);
+ if (codeB != NULL)
+ dib9000_firmware_download(state, 1, 0x1234, codeB, lenB);
+
+ /* Run the RISCs */
+ if (codeA != NULL)
+ dib9000_write_word(state, 1024, 0);
+ if (codeB != NULL)
+ dib9000_write_word(state, 1040, 0);
+
+ if (codeA != NULL)
+ if (dib9000_mbx_host_init(state, 0) != 0)
+ return -EIO;
+ if (codeB != NULL)
+ if (dib9000_mbx_host_init(state, 1) != 0)
+ return -EIO;
+
+ msleep(100);
+ state->platform.risc.fw_is_running = 1;
+
+ if (dib9000_risc_check_version(state) != 0)
+ return -EINVAL;
+
+ state->platform.risc.memcmd = 0xff;
+ return 0;
+}
+
+static u16 dib9000_identify(struct i2c_device *client)
+{
+ u16 value;
+
+ value = dib9000_i2c_read16(client, 896);
+ if (value != 0x01b3) {
+ dprintk("wrong Vendor ID (0x%x)", value);
+ return 0;
+ }
+
+ value = dib9000_i2c_read16(client, 897);
+ if (value != 0x4000 && value != 0x4001 && value != 0x4002 && value != 0x4003 && value != 0x4004 && value != 0x4005) {
+ dprintk("wrong Device ID (0x%x)", value);
+ return 0;
+ }
+
+ /* protect this driver to be used with 7000PC */
+ if (value == 0x4000 && dib9000_i2c_read16(client, 769) == 0x4000) {
+ dprintk("this driver does not work with DiB7000PC");
+ return 0;
+ }
+
+ switch (value) {
+ case 0x4000:
+ dprintk("found DiB7000MA/PA/MB/PB");
+ break;
+ case 0x4001:
+ dprintk("found DiB7000HC");
+ break;
+ case 0x4002:
+ dprintk("found DiB7000MC");
+ break;
+ case 0x4003:
+ dprintk("found DiB9000A");
+ break;
+ case 0x4004:
+ dprintk("found DiB9000H");
+ break;
+ case 0x4005:
+ dprintk("found DiB9000M");
+ break;
+ }
+
+ return value;
+}
+
+static void dib9000_set_power_mode(struct dib9000_state *state, enum dib9000_power_mode mode)
+{
+ /* by default everything is going to be powered off */
+ u16 reg_903 = 0x3fff, reg_904 = 0xffff, reg_905 = 0xffff, reg_906;
+ u8 offset;
+
+ if (state->revision == 0x4003 || state->revision == 0x4004 || state->revision == 0x4005)
+ offset = 1;
+ else
+ offset = 0;
+
+ reg_906 = dib9000_read_word(state, 906 + offset) | 0x3; /* keep settings for RISC */
+
+ /* now, depending on the requested mode, we power on */
+ switch (mode) {
+ /* power up everything in the demod */
+ case DIB9000_POWER_ALL:
+ reg_903 = 0x0000;
+ reg_904 = 0x0000;
+ reg_905 = 0x0000;
+ reg_906 = 0x0000;
+ break;
+
+ /* just leave power on the control-interfaces: GPIO and (I2C or SDIO or SRAM) */
+ case DIB9000_POWER_INTERFACE_ONLY: /* TODO power up either SDIO or I2C or SRAM */
+ reg_905 &= ~((1 << 7) | (1 << 6) | (1 << 5) | (1 << 2));
+ break;
+
+ case DIB9000_POWER_INTERF_ANALOG_AGC:
+ reg_903 &= ~((1 << 15) | (1 << 14) | (1 << 11) | (1 << 10));
+ reg_905 &= ~((1 << 7) | (1 << 6) | (1 << 5) | (1 << 4) | (1 << 2));
+ reg_906 &= ~((1 << 0));
+ break;
+
+ case DIB9000_POWER_COR4_DINTLV_ICIRM_EQUAL_CFROD:
+ reg_903 = 0x0000;
+ reg_904 = 0x801f;
+ reg_905 = 0x0000;
+ reg_906 &= ~((1 << 0));
+ break;
+
+ case DIB9000_POWER_COR4_CRY_ESRAM_MOUT_NUD:
+ reg_903 = 0x0000;
+ reg_904 = 0x8000;
+ reg_905 = 0x010b;
+ reg_906 &= ~((1 << 0));
+ break;
+ default:
+ case DIB9000_POWER_NO:
+ break;
+ }
+
+ /* always power down unused parts */
+ if (!state->platform.host.mobile_mode)
+ reg_904 |= (1 << 7) | (1 << 6) | (1 << 4) | (1 << 2) | (1 << 1);
+
+ /* P_sdio_select_clk = 0 on MC and after */
+ if (state->revision != 0x4000)
+ reg_906 <<= 1;
+
+ dib9000_write_word(state, 903 + offset, reg_903);
+ dib9000_write_word(state, 904 + offset, reg_904);
+ dib9000_write_word(state, 905 + offset, reg_905);
+ dib9000_write_word(state, 906 + offset, reg_906);
+}
+
+static int dib9000_fw_reset(struct dvb_frontend *fe)
+{
+ struct dib9000_state *state = fe->demodulator_priv;
+
+ dib9000_write_word(state, 1817, 0x0003);
+
+ dib9000_write_word(state, 1227, 1);
+ dib9000_write_word(state, 1227, 0);
+
+ switch ((state->revision = dib9000_identify(&state->i2c))) {
+ case 0x4003:
+ case 0x4004:
+ case 0x4005:
+ state->reg_offs = 1;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ /* reset the i2c-master to use the host interface */
+ dibx000_reset_i2c_master(&state->i2c_master);
+
+ dib9000_set_power_mode(state, DIB9000_POWER_ALL);
+
+ /* unforce divstr regardless whether i2c enumeration was done or not */
+ dib9000_write_word(state, 1794, dib9000_read_word(state, 1794) & ~(1 << 1));
+ dib9000_write_word(state, 1796, 0);
+ dib9000_write_word(state, 1805, 0x805);
+
+ /* restart all parts */
+ dib9000_write_word(state, 898, 0xffff);
+ dib9000_write_word(state, 899, 0xffff);
+ dib9000_write_word(state, 900, 0x0001);
+ dib9000_write_word(state, 901, 0xff19);
+ dib9000_write_word(state, 902, 0x003c);
+
+ dib9000_write_word(state, 898, 0);
+ dib9000_write_word(state, 899, 0);
+ dib9000_write_word(state, 900, 0);
+ dib9000_write_word(state, 901, 0);
+ dib9000_write_word(state, 902, 0);
+
+ dib9000_write_word(state, 911, state->chip.d9.cfg.if_drives);
+
+ dib9000_set_power_mode(state, DIB9000_POWER_INTERFACE_ONLY);
+
+ return 0;
+}
+
+static int dib9000_risc_apb_access_read(struct dib9000_state *state, u32 address, u16 attribute, const u8 * tx, u32 txlen, u8 * b, u32 len)
+{
+ u16 mb[10];
+ u8 i, s;
+
+ if (address >= 1024 || !state->platform.risc.fw_is_running)
+ return -EINVAL;
+
+ /* dprintk( "APB access thru rd fw %d %x", address, attribute); */
+
+ mb[0] = (u16) address;
+ mb[1] = len / 2;
+ dib9000_mbx_send_attr(state, OUT_MSG_BRIDGE_APB_R, mb, 2, attribute);
+ switch (dib9000_mbx_get_message_attr(state, IN_MSG_END_BRIDGE_APB_RW, mb, &s, attribute)) {
+ case 1:
+ s--;
+ for (i = 0; i < s; i++) {
+ b[i * 2] = (mb[i + 1] >> 8) & 0xff;
+ b[i * 2 + 1] = (mb[i + 1]) & 0xff;
+ }
+ return 0;
+ default:
+ return -EIO;
+ }
+ return -EIO;
+}
+
+static int dib9000_risc_apb_access_write(struct dib9000_state *state, u32 address, u16 attribute, const u8 * b, u32 len)
+{
+ u16 mb[10];
+ u8 s, i;
+
+ if (address >= 1024 || !state->platform.risc.fw_is_running)
+ return -EINVAL;
+
+ /* dprintk( "APB access thru wr fw %d %x", address, attribute); */
+
+ mb[0] = (unsigned short)address;
+ for (i = 0; i < len && i < 20; i += 2)
+ mb[1 + (i / 2)] = (b[i] << 8 | b[i + 1]);
+
+ dib9000_mbx_send_attr(state, OUT_MSG_BRIDGE_APB_W, mb, 1 + len / 2, attribute);
+ return dib9000_mbx_get_message_attr(state, IN_MSG_END_BRIDGE_APB_RW, mb, &s, attribute) == 1 ? 0 : -EINVAL;
+}
+
+static int dib9000_fw_memmbx_sync(struct dib9000_state *state, u8 i)
+{
+ u8 index_loop = 10;
+
+ if (!state->platform.risc.fw_is_running)
+ return 0;
+ dib9000_risc_mem_write(state, FE_MM_RW_SYNC, &i);
+ do {
+ dib9000_risc_mem_read(state, FE_MM_RW_SYNC, &i, 1);
+ } while (i && index_loop--);
+
+ if (index_loop > 0)
+ return 0;
+ return -EIO;
+}
+
+static int dib9000_fw_init(struct dib9000_state *state)
+{
+ struct dibGPIOFunction *f;
+ u16 b[40] = { 0 };
+ u8 i;
+ u8 size;
+
+ if (dib9000_fw_boot(state, NULL, 0, state->chip.d9.cfg.microcode_B_fe_buffer, state->chip.d9.cfg.microcode_B_fe_size) != 0)
+ return -EIO;
+
+ /* initialize the firmware */
+ for (i = 0; i < ARRAY_SIZE(state->chip.d9.cfg.gpio_function); i++) {
+ f = &state->chip.d9.cfg.gpio_function[i];
+ if (f->mask) {
+ switch (f->function) {
+ case BOARD_GPIO_FUNCTION_COMPONENT_ON:
+ b[0] = (u16) f->mask;
+ b[1] = (u16) f->direction;
+ b[2] = (u16) f->value;
+ break;
+ case BOARD_GPIO_FUNCTION_COMPONENT_OFF:
+ b[3] = (u16) f->mask;
+ b[4] = (u16) f->direction;
+ b[5] = (u16) f->value;
+ break;
+ }
+ }
+ }
+ if (dib9000_mbx_send(state, OUT_MSG_CONF_GPIO, b, 15) != 0)
+ return -EIO;
+
+ /* subband */
+ b[0] = state->chip.d9.cfg.subband.size; /* type == 0 -> GPIO - PWM not yet supported */
+ for (i = 0; i < state->chip.d9.cfg.subband.size; i++) {
+ b[1 + i * 4] = state->chip.d9.cfg.subband.subband[i].f_mhz;
+ b[2 + i * 4] = (u16) state->chip.d9.cfg.subband.subband[i].gpio.mask;
+ b[3 + i * 4] = (u16) state->chip.d9.cfg.subband.subband[i].gpio.direction;
+ b[4 + i * 4] = (u16) state->chip.d9.cfg.subband.subband[i].gpio.value;
+ }
+ b[1 + i * 4] = 0; /* fe_id */
+ if (dib9000_mbx_send(state, OUT_MSG_SUBBAND_SEL, b, 2 + 4 * i) != 0)
+ return -EIO;
+
+ /* 0 - id, 1 - no_of_frontends */
+ b[0] = (0 << 8) | 1;
+ /* 0 = i2c-address demod, 0 = tuner */
+ b[1] = (0 << 8) | (0);
+ b[2] = (u16) (((state->chip.d9.cfg.xtal_clock_khz * 1000) >> 16) & 0xffff);
+ b[3] = (u16) (((state->chip.d9.cfg.xtal_clock_khz * 1000)) & 0xffff);
+ b[4] = (u16) ((state->chip.d9.cfg.vcxo_timer >> 16) & 0xffff);
+ b[5] = (u16) ((state->chip.d9.cfg.vcxo_timer) & 0xffff);
+ b[6] = (u16) ((state->chip.d9.cfg.timing_frequency >> 16) & 0xffff);
+ b[7] = (u16) ((state->chip.d9.cfg.timing_frequency) & 0xffff);
+ b[29] = state->chip.d9.cfg.if_drives;
+ if (dib9000_mbx_send(state, OUT_MSG_INIT_DEMOD, b, ARRAY_SIZE(b)) != 0)
+ return -EIO;
+
+ if (dib9000_mbx_send(state, OUT_MSG_FE_FW_DL, NULL, 0) != 0)
+ return -EIO;
+
+ if (dib9000_mbx_get_message(state, IN_MSG_FE_FW_DL_DONE, b, &size) < 0)
+ return -EIO;
+
+ if (size > ARRAY_SIZE(b)) {
+ dprintk("error : firmware returned %dbytes needed but the used buffer has only %dbytes\n Firmware init ABORTED", size,
+ (int)ARRAY_SIZE(b));
+ return -EINVAL;
+ }
+
+ for (i = 0; i < size; i += 2) {
+ state->platform.risc.fe_mm[i / 2].addr = b[i + 0];
+ state->platform.risc.fe_mm[i / 2].size = b[i + 1];
+ }
+
+ return 0;
+}
+
+static void dib9000_fw_set_channel_head(struct dib9000_state *state, struct dvb_frontend_parameters *ch)
+{
+ u8 b[9];
+ u32 freq = state->fe[0]->dtv_property_cache.frequency / 1000;
+ if (state->fe_id % 2)
+ freq += 101;
+
+ b[0] = (u8) ((freq >> 0) & 0xff);
+ b[1] = (u8) ((freq >> 8) & 0xff);
+ b[2] = (u8) ((freq >> 16) & 0xff);
+ b[3] = (u8) ((freq >> 24) & 0xff);
+ b[4] = (u8) ((state->fe[0]->dtv_property_cache.bandwidth_hz / 1000 >> 0) & 0xff);
+ b[5] = (u8) ((state->fe[0]->dtv_property_cache.bandwidth_hz / 1000 >> 8) & 0xff);
+ b[6] = (u8) ((state->fe[0]->dtv_property_cache.bandwidth_hz / 1000 >> 16) & 0xff);
+ b[7] = (u8) ((state->fe[0]->dtv_property_cache.bandwidth_hz / 1000 >> 24) & 0xff);
+ b[8] = 0x80; /* do not wait for CELL ID when doing autosearch */
+ if (state->fe[0]->dtv_property_cache.delivery_system == SYS_DVBT)
+ b[8] |= 1;
+ dib9000_risc_mem_write(state, FE_MM_W_CHANNEL_HEAD, b);
+}
+
+static int dib9000_fw_get_channel(struct dvb_frontend *fe, struct dvb_frontend_parameters *channel)
+{
+ struct dib9000_state *state = fe->demodulator_priv;
+ struct dibDVBTChannel {
+ s8 spectrum_inversion;
+
+ s8 nfft;
+ s8 guard;
+ s8 constellation;
+
+ s8 hrch;
+ s8 alpha;
+ s8 code_rate_hp;
+ s8 code_rate_lp;
+ s8 select_hp;
+
+ s8 intlv_native;
+ };
+ struct dibDVBTChannel ch;
+ int ret = 0;
+
+ DibAcquireLock(&state->platform.risc.mem_mbx_lock);
+ if (dib9000_fw_memmbx_sync(state, FE_SYNC_CHANNEL) < 0) {
+ goto error;
+ ret = -EIO;
+ }
+
+ dib9000_risc_mem_read(state, FE_MM_R_CHANNEL_UNION, (u8 *) &ch, sizeof(struct dibDVBTChannel));
+
+ switch (ch.spectrum_inversion & 0x7) {
+ case 1:
+ state->fe[0]->dtv_property_cache.inversion = INVERSION_ON;
+ break;
+ case 0:
+ state->fe[0]->dtv_property_cache.inversion = INVERSION_OFF;
+ break;
+ default:
+ case -1:
+ state->fe[0]->dtv_property_cache.inversion = INVERSION_AUTO;
+ break;
+ }
+ switch (ch.nfft) {
+ case 0:
+ state->fe[0]->dtv_property_cache.transmission_mode = TRANSMISSION_MODE_2K;
+ break;
+ case 2:
+ state->fe[0]->dtv_property_cache.transmission_mode = TRANSMISSION_MODE_4K;
+ break;
+ case 1:
+ state->fe[0]->dtv_property_cache.transmission_mode = TRANSMISSION_MODE_8K;
+ break;
+ default:
+ case -1:
+ state->fe[0]->dtv_property_cache.transmission_mode = TRANSMISSION_MODE_AUTO;
+ break;
+ }
+ switch (ch.guard) {
+ case 0:
+ state->fe[0]->dtv_property_cache.guard_interval = GUARD_INTERVAL_1_32;
+ break;
+ case 1:
+ state->fe[0]->dtv_property_cache.guard_interval = GUARD_INTERVAL_1_16;
+ break;
+ case 2:
+ state->fe[0]->dtv_property_cache.guard_interval = GUARD_INTERVAL_1_8;
+ break;
+ case 3:
+ state->fe[0]->dtv_property_cache.guard_interval = GUARD_INTERVAL_1_4;
+ break;
+ default:
+ case -1:
+ state->fe[0]->dtv_property_cache.guard_interval = GUARD_INTERVAL_AUTO;
+ break;
+ }
+ switch (ch.constellation) {
+ case 2:
+ state->fe[0]->dtv_property_cache.modulation = QAM_64;
+ break;
+ case 1:
+ state->fe[0]->dtv_property_cache.modulation = QAM_16;
+ break;
+ case 0:
+ state->fe[0]->dtv_property_cache.modulation = QPSK;
+ break;
+ default:
+ case -1:
+ state->fe[0]->dtv_property_cache.modulation = QAM_AUTO;
+ break;
+ }
+ switch (ch.hrch) {
+ case 0:
+ state->fe[0]->dtv_property_cache.hierarchy = HIERARCHY_NONE;
+ break;
+ case 1:
+ state->fe[0]->dtv_property_cache.hierarchy = HIERARCHY_1;
+ break;
+ default:
+ case -1:
+ state->fe[0]->dtv_property_cache.hierarchy = HIERARCHY_AUTO;
+ break;
+ }
+ switch (ch.code_rate_hp) {
+ case 1:
+ state->fe[0]->dtv_property_cache.code_rate_HP = FEC_1_2;
+ break;
+ case 2:
+ state->fe[0]->dtv_property_cache.code_rate_HP = FEC_2_3;
+ break;
+ case 3:
+ state->fe[0]->dtv_property_cache.code_rate_HP = FEC_3_4;
+ break;
+ case 5:
+ state->fe[0]->dtv_property_cache.code_rate_HP = FEC_5_6;
+ break;
+ case 7:
+ state->fe[0]->dtv_property_cache.code_rate_HP = FEC_7_8;
+ break;
+ default:
+ case -1:
+ state->fe[0]->dtv_property_cache.code_rate_HP = FEC_AUTO;
+ break;
+ }
+ switch (ch.code_rate_lp) {
+ case 1:
+ state->fe[0]->dtv_property_cache.code_rate_LP = FEC_1_2;
+ break;
+ case 2:
+ state->fe[0]->dtv_property_cache.code_rate_LP = FEC_2_3;
+ break;
+ case 3:
+ state->fe[0]->dtv_property_cache.code_rate_LP = FEC_3_4;
+ break;
+ case 5:
+ state->fe[0]->dtv_property_cache.code_rate_LP = FEC_5_6;
+ break;
+ case 7:
+ state->fe[0]->dtv_property_cache.code_rate_LP = FEC_7_8;
+ break;
+ default:
+ case -1:
+ state->fe[0]->dtv_property_cache.code_rate_LP = FEC_AUTO;
+ break;
+ }
+
+error:
+ DibReleaseLock(&state->platform.risc.mem_mbx_lock);
+ return ret;
+}
+
+static int dib9000_fw_set_channel_union(struct dvb_frontend *fe, struct dvb_frontend_parameters *channel)
+{
+ struct dib9000_state *state = fe->demodulator_priv;
+ struct dibDVBTChannel {
+ s8 spectrum_inversion;
+
+ s8 nfft;
+ s8 guard;
+ s8 constellation;
+
+ s8 hrch;
+ s8 alpha;
+ s8 code_rate_hp;
+ s8 code_rate_lp;
+ s8 select_hp;
+
+ s8 intlv_native;
+ };
+ struct dibDVBTChannel ch;
+
+ switch (state->fe[0]->dtv_property_cache.inversion) {
+ case INVERSION_ON:
+ ch.spectrum_inversion = 1;
+ break;
+ case INVERSION_OFF:
+ ch.spectrum_inversion = 0;
+ break;
+ default:
+ case INVERSION_AUTO:
+ ch.spectrum_inversion = -1;
+ break;
+ }
+ switch (state->fe[0]->dtv_property_cache.transmission_mode) {
+ case TRANSMISSION_MODE_2K:
+ ch.nfft = 0;
+ break;
+ case TRANSMISSION_MODE_4K:
+ ch.nfft = 2;
+ break;
+ case TRANSMISSION_MODE_8K:
+ ch.nfft = 1;
+ break;
+ default:
+ case TRANSMISSION_MODE_AUTO:
+ ch.nfft = 1;
+ break;
+ }
+ switch (state->fe[0]->dtv_property_cache.guard_interval) {
+ case GUARD_INTERVAL_1_32:
+ ch.guard = 0;
+ break;
+ case GUARD_INTERVAL_1_16:
+ ch.guard = 1;
+ break;
+ case GUARD_INTERVAL_1_8:
+ ch.guard = 2;
+ break;
+ case GUARD_INTERVAL_1_4:
+ ch.guard = 3;
+ break;
+ default:
+ case GUARD_INTERVAL_AUTO:
+ ch.guard = -1;
+ break;
+ }
+ switch (state->fe[0]->dtv_property_cache.modulation) {
+ case QAM_64:
+ ch.constellation = 2;
+ break;
+ case QAM_16:
+ ch.constellation = 1;
+ break;
+ case QPSK:
+ ch.constellation = 0;
+ break;
+ default:
+ case QAM_AUTO:
+ ch.constellation = -1;
+ break;
+ }
+ switch (state->fe[0]->dtv_property_cache.hierarchy) {
+ case HIERARCHY_NONE:
+ ch.hrch = 0;
+ break;
+ case HIERARCHY_1:
+ case HIERARCHY_2:
+ case HIERARCHY_4:
+ ch.hrch = 1;
+ break;
+ default:
+ case HIERARCHY_AUTO:
+ ch.hrch = -1;
+ break;
+ }
+ ch.alpha = 1;
+ switch (state->fe[0]->dtv_property_cache.code_rate_HP) {
+ case FEC_1_2:
+ ch.code_rate_hp = 1;
+ break;
+ case FEC_2_3:
+ ch.code_rate_hp = 2;
+ break;
+ case FEC_3_4:
+ ch.code_rate_hp = 3;
+ break;
+ case FEC_5_6:
+ ch.code_rate_hp = 5;
+ break;
+ case FEC_7_8:
+ ch.code_rate_hp = 7;
+ break;
+ default:
+ case FEC_AUTO:
+ ch.code_rate_hp = -1;
+ break;
+ }
+ switch (state->fe[0]->dtv_property_cache.code_rate_LP) {
+ case FEC_1_2:
+ ch.code_rate_lp = 1;
+ break;
+ case FEC_2_3:
+ ch.code_rate_lp = 2;
+ break;
+ case FEC_3_4:
+ ch.code_rate_lp = 3;
+ break;
+ case FEC_5_6:
+ ch.code_rate_lp = 5;
+ break;
+ case FEC_7_8:
+ ch.code_rate_lp = 7;
+ break;
+ default:
+ case FEC_AUTO:
+ ch.code_rate_lp = -1;
+ break;
+ }
+ ch.select_hp = 1;
+ ch.intlv_native = 1;
+
+ dib9000_risc_mem_write(state, FE_MM_W_CHANNEL_UNION, (u8 *) &ch);
+
+ return 0;
+}
+
+static int dib9000_fw_tune(struct dvb_frontend *fe, struct dvb_frontend_parameters *ch)
+{
+ struct dib9000_state *state = fe->demodulator_priv;
+ int ret = 10, search = state->channel_status.status == CHANNEL_STATUS_PARAMETERS_UNKNOWN;
+ s8 i;
+
+ switch (state->tune_state) {
+ case CT_DEMOD_START:
+ dib9000_fw_set_channel_head(state, ch);
+
+ /* write the channel context - a channel is initialized to 0, so it is OK */
+ dib9000_risc_mem_write(state, FE_MM_W_CHANNEL_CONTEXT, (u8 *) fe_info);
+ dib9000_risc_mem_write(state, FE_MM_W_FE_INFO, (u8 *) fe_info);
+
+ if (search)
+ dib9000_mbx_send(state, OUT_MSG_FE_CHANNEL_SEARCH, NULL, 0);
+ else {
+ dib9000_fw_set_channel_union(fe, ch);
+ dib9000_mbx_send(state, OUT_MSG_FE_CHANNEL_TUNE, NULL, 0);
+ }
+ state->tune_state = CT_DEMOD_STEP_1;
+ break;
+ case CT_DEMOD_STEP_1:
+ if (search)
+ dib9000_risc_mem_read(state, FE_MM_R_CHANNEL_SEARCH_STATE, (u8 *) &i, 1);
+ else
+ dib9000_risc_mem_read(state, FE_MM_R_CHANNEL_TUNE_STATE, (u8 *) &i, 1);
+ switch (i) { /* something happened */
+ case 0:
+ break;
+ case -2: /* tps locks are "slower" than MPEG locks -> even in autosearch data is OK here */
+ if (search)
+ state->status = FE_STATUS_DEMOD_SUCCESS;
+ else {
+ state->tune_state = CT_DEMOD_STOP;
+ state->status = FE_STATUS_LOCKED;
+ }
+ break;
+ default:
+ state->status = FE_STATUS_TUNE_FAILED;
+ state->tune_state = CT_DEMOD_STOP;
+ break;
+ }
+ break;
+ default:
+ ret = FE_CALLBACK_TIME_NEVER;
+ break;
+ }
+
+ return ret;
+}
+
+static int dib9000_fw_set_diversity_in(struct dvb_frontend *fe, int onoff)
+{
+ struct dib9000_state *state = fe->demodulator_priv;
+ u16 mode = (u16) onoff;
+ return dib9000_mbx_send(state, OUT_MSG_ENABLE_DIVERSITY, &mode, 1);
+}
+
+static int dib9000_fw_set_output_mode(struct dvb_frontend *fe, int mode)
+{
+ struct dib9000_state *state = fe->demodulator_priv;
+ u16 outreg, smo_mode;
+
+ dprintk("setting output mode for demod %p to %d", fe, mode);
+
+ switch (mode) {
+ case OUTMODE_MPEG2_PAR_GATED_CLK:
+ outreg = (1 << 10); /* 0x0400 */
+ break;
+ case OUTMODE_MPEG2_PAR_CONT_CLK:
+ outreg = (1 << 10) | (1 << 6); /* 0x0440 */
+ break;
+ case OUTMODE_MPEG2_SERIAL:
+ outreg = (1 << 10) | (2 << 6) | (0 << 1); /* 0x0482 */
+ break;
+ case OUTMODE_DIVERSITY:
+ outreg = (1 << 10) | (4 << 6); /* 0x0500 */
+ break;
+ case OUTMODE_MPEG2_FIFO:
+ outreg = (1 << 10) | (5 << 6);
+ break;
+ case OUTMODE_HIGH_Z:
+ outreg = 0;
+ break;
+ default:
+ dprintk("Unhandled output_mode passed to be set for demod %p", &state->fe[0]);
+ return -EINVAL;
+ }
+
+ dib9000_write_word(state, 1795, outreg);
+
+ switch (mode) {
+ case OUTMODE_MPEG2_PAR_GATED_CLK:
+ case OUTMODE_MPEG2_PAR_CONT_CLK:
+ case OUTMODE_MPEG2_SERIAL:
+ case OUTMODE_MPEG2_FIFO:
+ smo_mode = (dib9000_read_word(state, 295) & 0x0010) | (1 << 1);
+ if (state->chip.d9.cfg.output_mpeg2_in_188_bytes)
+ smo_mode |= (1 << 5);
+ dib9000_write_word(state, 295, smo_mode);
+ break;
+ }
+
+ outreg = to_fw_output_mode(mode);
+ return dib9000_mbx_send(state, OUT_MSG_SET_OUTPUT_MODE, &outreg, 1);
+}
+
+static int dib9000_tuner_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg msg[], int num)
+{
+ struct dib9000_state *state = i2c_get_adapdata(i2c_adap);
+ u16 i, len, t, index_msg;
+
+ for (index_msg = 0; index_msg < num; index_msg++) {
+ if (msg[index_msg].flags & I2C_M_RD) { /* read */
+ len = msg[index_msg].len;
+ if (len > 16)
+ len = 16;
+
+ if (dib9000_read_word(state, 790) != 0)
+ dprintk("TunerITF: read busy");
+
+ dib9000_write_word(state, 784, (u16) (msg[index_msg].addr));
+ dib9000_write_word(state, 787, (len / 2) - 1);
+ dib9000_write_word(state, 786, 1); /* start read */
+
+ i = 1000;
+ while (dib9000_read_word(state, 790) != (len / 2) && i)
+ i--;
+
+ if (i == 0)
+ dprintk("TunerITF: read failed");
+
+ for (i = 0; i < len; i += 2) {
+ t = dib9000_read_word(state, 785);
+ msg[index_msg].buf[i] = (t >> 8) & 0xff;
+ msg[index_msg].buf[i + 1] = (t) & 0xff;
+ }
+ if (dib9000_read_word(state, 790) != 0)
+ dprintk("TunerITF: read more data than expected");
+ } else {
+ i = 1000;
+ while (dib9000_read_word(state, 789) && i)
+ i--;
+ if (i == 0)
+ dprintk("TunerITF: write busy");
+
+ len = msg[index_msg].len;
+ if (len > 16)
+ len = 16;
+
+ for (i = 0; i < len; i += 2)
+ dib9000_write_word(state, 785, (msg[index_msg].buf[i] << 8) | msg[index_msg].buf[i + 1]);
+ dib9000_write_word(state, 784, (u16) msg[index_msg].addr);
+ dib9000_write_word(state, 787, (len / 2) - 1);
+ dib9000_write_word(state, 786, 0); /* start write */
+
+ i = 1000;
+ while (dib9000_read_word(state, 791) > 0 && i)
+ i--;
+ if (i == 0)
+ dprintk("TunerITF: write failed");
+ }
+ }
+ return num;
+}
+
+int dib9000_fw_set_component_bus_speed(struct dvb_frontend *fe, u16 speed)
+{
+ struct dib9000_state *state = fe->demodulator_priv;
+
+ state->component_bus_speed = speed;
+ return 0;
+}
+EXPORT_SYMBOL(dib9000_fw_set_component_bus_speed);
+
+static int dib9000_fw_component_bus_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg msg[], int num)
+{
+ struct dib9000_state *state = i2c_get_adapdata(i2c_adap);
+ u8 type = 0; /* I2C */
+ u8 port = DIBX000_I2C_INTERFACE_GPIO_3_4;
+ u16 scl = state->component_bus_speed; /* SCL frequency */
+ struct dib9000_fe_memory_map *m = &state->platform.risc.fe_mm[FE_MM_RW_COMPONENT_ACCESS_BUFFER];
+ u8 p[13] = { 0 };
+
+ p[0] = type;
+ p[1] = port;
+ p[2] = msg[0].addr << 1;
+
+ p[3] = (u8) scl & 0xff; /* scl */
+ p[4] = (u8) (scl >> 8);
+
+ p[7] = 0;
+ p[8] = 0;
+
+ p[9] = (u8) (msg[0].len);
+ p[10] = (u8) (msg[0].len >> 8);
+ if ((num > 1) && (msg[1].flags & I2C_M_RD)) {
+ p[11] = (u8) (msg[1].len);
+ p[12] = (u8) (msg[1].len >> 8);
+ } else {
+ p[11] = 0;
+ p[12] = 0;
+ }
+
+ DibAcquireLock(&state->platform.risc.mem_mbx_lock);
+
+ dib9000_risc_mem_write(state, FE_MM_W_COMPONENT_ACCESS, p);
+
+ { /* write-part */
+ dib9000_risc_mem_setup_cmd(state, m->addr, msg[0].len, 0);
+ dib9000_risc_mem_write_chunks(state, msg[0].buf, msg[0].len);
+ }
+
+ /* do the transaction */
+ if (dib9000_fw_memmbx_sync(state, FE_SYNC_COMPONENT_ACCESS) < 0) {
+ DibReleaseLock(&state->platform.risc.mem_mbx_lock);
+ return 0;
+ }
+
+ /* read back any possible result */
+ if ((num > 1) && (msg[1].flags & I2C_M_RD))
+ dib9000_risc_mem_read(state, FE_MM_RW_COMPONENT_ACCESS_BUFFER, msg[1].buf, msg[1].len);
+
+ DibReleaseLock(&state->platform.risc.mem_mbx_lock);
+
+ return num;
+}
+
+static u32 dib9000_i2c_func(struct i2c_adapter *adapter)
+{
+ return I2C_FUNC_I2C;
+}
+
+static struct i2c_algorithm dib9000_tuner_algo = {
+ .master_xfer = dib9000_tuner_xfer,
+ .functionality = dib9000_i2c_func,
+};
+
+static struct i2c_algorithm dib9000_component_bus_algo = {
+ .master_xfer = dib9000_fw_component_bus_xfer,
+ .functionality = dib9000_i2c_func,
+};
+
+struct i2c_adapter *dib9000_get_tuner_interface(struct dvb_frontend *fe)
+{
+ struct dib9000_state *st = fe->demodulator_priv;
+ return &st->tuner_adap;
+}
+EXPORT_SYMBOL(dib9000_get_tuner_interface);
+
+struct i2c_adapter *dib9000_get_component_bus_interface(struct dvb_frontend *fe)
+{
+ struct dib9000_state *st = fe->demodulator_priv;
+ return &st->component_bus;
+}
+EXPORT_SYMBOL(dib9000_get_component_bus_interface);
+
+struct i2c_adapter *dib9000_get_i2c_master(struct dvb_frontend *fe, enum dibx000_i2c_interface intf, int gating)
+{
+ struct dib9000_state *st = fe->demodulator_priv;
+ return dibx000_get_i2c_adapter(&st->i2c_master, intf, gating);
+}
+EXPORT_SYMBOL(dib9000_get_i2c_master);
+
+int dib9000_set_i2c_adapter(struct dvb_frontend *fe, struct i2c_adapter *i2c)
+{
+ struct dib9000_state *st = fe->demodulator_priv;
+
+ st->i2c.i2c_adap = i2c;
+ return 0;
+}
+EXPORT_SYMBOL(dib9000_set_i2c_adapter);
+
+static int dib9000_cfg_gpio(struct dib9000_state *st, u8 num, u8 dir, u8 val)
+{
+ st->gpio_dir = dib9000_read_word(st, 773);
+ st->gpio_dir &= ~(1 << num); /* reset the direction bit */
+ st->gpio_dir |= (dir & 0x1) << num; /* set the new direction */
+ dib9000_write_word(st, 773, st->gpio_dir);
+
+ st->gpio_val = dib9000_read_word(st, 774);
+ st->gpio_val &= ~(1 << num); /* reset the direction bit */
+ st->gpio_val |= (val & 0x01) << num; /* set the new value */
+ dib9000_write_word(st, 774, st->gpio_val);
+
+ dprintk("gpio dir: %04x: gpio val: %04x", st->gpio_dir, st->gpio_val);
+
+ return 0;
+}
+
+int dib9000_set_gpio(struct dvb_frontend *fe, u8 num, u8 dir, u8 val)
+{
+ struct dib9000_state *state = fe->demodulator_priv;
+ return dib9000_cfg_gpio(state, num, dir, val);
+}
+EXPORT_SYMBOL(dib9000_set_gpio);
+
+int dib9000_fw_pid_filter_ctrl(struct dvb_frontend *fe, u8 onoff)
+{
+ struct dib9000_state *state = fe->demodulator_priv;
+ u16 val = dib9000_read_word(state, 294 + 1) & 0xffef;
+ val |= (onoff & 0x1) << 4;
+
+ dprintk("PID filter enabled %d", onoff);
+ return dib9000_write_word(state, 294 + 1, val);
+}
+EXPORT_SYMBOL(dib9000_fw_pid_filter_ctrl);
+
+int dib9000_fw_pid_filter(struct dvb_frontend *fe, u8 id, u16 pid, u8 onoff)
+{
+ struct dib9000_state *state = fe->demodulator_priv;
+ dprintk("Index %x, PID %d, OnOff %d", id, pid, onoff);
+ return dib9000_write_word(state, 300 + 1 + id, onoff ? (1 << 13) | pid : 0);
+}
+EXPORT_SYMBOL(dib9000_fw_pid_filter);
+
+int dib9000_firmware_post_pll_init(struct dvb_frontend *fe)
+{
+ struct dib9000_state *state = fe->demodulator_priv;
+ return dib9000_fw_init(state);
+}
+EXPORT_SYMBOL(dib9000_firmware_post_pll_init);
+
+static void dib9000_release(struct dvb_frontend *demod)
+{
+ struct dib9000_state *st = demod->demodulator_priv;
+ u8 index_frontend;
+
+ for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (st->fe[index_frontend] != NULL); index_frontend++)
+ dvb_frontend_detach(st->fe[index_frontend]);
+
+ DibFreeLock(&state->platform.risc.mbx_if_lock);
+ DibFreeLock(&state->platform.risc.mbx_lock);
+ DibFreeLock(&state->platform.risc.mem_lock);
+ DibFreeLock(&state->platform.risc.mem_mbx_lock);
+ dibx000_exit_i2c_master(&st->i2c_master);
+
+ i2c_del_adapter(&st->tuner_adap);
+ i2c_del_adapter(&st->component_bus);
+ kfree(st->fe[0]);
+ kfree(st);
+}
+
+static int dib9000_wakeup(struct dvb_frontend *fe)
+{
+ return 0;
+}
+
+static int dib9000_sleep(struct dvb_frontend *fe)
+{
+ struct dib9000_state *state = fe->demodulator_priv;
+ u8 index_frontend;
+ int ret;
+
+ for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
+ ret = state->fe[index_frontend]->ops.sleep(state->fe[index_frontend]);
+ if (ret < 0)
+ return ret;
+ }
+ return dib9000_mbx_send(state, OUT_MSG_FE_SLEEP, NULL, 0);
+}
+
+static int dib9000_fe_get_tune_settings(struct dvb_frontend *fe, struct dvb_frontend_tune_settings *tune)
+{
+ tune->min_delay_ms = 1000;
+ return 0;
+}
+
+static int dib9000_get_frontend(struct dvb_frontend *fe, struct dvb_frontend_parameters *fep)
+{
+ struct dib9000_state *state = fe->demodulator_priv;
+ u8 index_frontend, sub_index_frontend;
+ fe_status_t stat;
+ int ret;
+
+ for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
+ state->fe[index_frontend]->ops.read_status(state->fe[index_frontend], &stat);
+ if (stat & FE_HAS_SYNC) {
+ dprintk("TPS lock on the slave%i", index_frontend);
+
+ /* synchronize the cache with the other frontends */
+ state->fe[index_frontend]->ops.get_frontend(state->fe[index_frontend], fep);
+ for (sub_index_frontend = 0; (sub_index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[sub_index_frontend] != NULL);
+ sub_index_frontend++) {
+ if (sub_index_frontend != index_frontend) {
+ state->fe[sub_index_frontend]->dtv_property_cache.modulation =
+ state->fe[index_frontend]->dtv_property_cache.modulation;
+ state->fe[sub_index_frontend]->dtv_property_cache.inversion =
+ state->fe[index_frontend]->dtv_property_cache.inversion;
+ state->fe[sub_index_frontend]->dtv_property_cache.transmission_mode =
+ state->fe[index_frontend]->dtv_property_cache.transmission_mode;
+ state->fe[sub_index_frontend]->dtv_property_cache.guard_interval =
+ state->fe[index_frontend]->dtv_property_cache.guard_interval;
+ state->fe[sub_index_frontend]->dtv_property_cache.hierarchy =
+ state->fe[index_frontend]->dtv_property_cache.hierarchy;
+ state->fe[sub_index_frontend]->dtv_property_cache.code_rate_HP =
+ state->fe[index_frontend]->dtv_property_cache.code_rate_HP;
+ state->fe[sub_index_frontend]->dtv_property_cache.code_rate_LP =
+ state->fe[index_frontend]->dtv_property_cache.code_rate_LP;
+ state->fe[sub_index_frontend]->dtv_property_cache.rolloff =
+ state->fe[index_frontend]->dtv_property_cache.rolloff;
+ }
+ }
+ return 0;
+ }
+ }
+
+ /* get the channel from master chip */
+ ret = dib9000_fw_get_channel(fe, fep);
+ if (ret != 0)
+ return ret;
+
+ /* synchronize the cache with the other frontends */
+ for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
+ state->fe[index_frontend]->dtv_property_cache.inversion = fe->dtv_property_cache.inversion;
+ state->fe[index_frontend]->dtv_property_cache.transmission_mode = fe->dtv_property_cache.transmission_mode;
+ state->fe[index_frontend]->dtv_property_cache.guard_interval = fe->dtv_property_cache.guard_interval;
+ state->fe[index_frontend]->dtv_property_cache.modulation = fe->dtv_property_cache.modulation;
+ state->fe[index_frontend]->dtv_property_cache.hierarchy = fe->dtv_property_cache.hierarchy;
+ state->fe[index_frontend]->dtv_property_cache.code_rate_HP = fe->dtv_property_cache.code_rate_HP;
+ state->fe[index_frontend]->dtv_property_cache.code_rate_LP = fe->dtv_property_cache.code_rate_LP;
+ state->fe[index_frontend]->dtv_property_cache.rolloff = fe->dtv_property_cache.rolloff;
+ }
+
+ return 0;
+}
+
+static int dib9000_set_tune_state(struct dvb_frontend *fe, enum frontend_tune_state tune_state)
+{
+ struct dib9000_state *state = fe->demodulator_priv;
+ state->tune_state = tune_state;
+ if (tune_state == CT_DEMOD_START)
+ state->status = FE_STATUS_TUNE_PENDING;
+
+ return 0;
+}
+
+static u32 dib9000_get_status(struct dvb_frontend *fe)
+{
+ struct dib9000_state *state = fe->demodulator_priv;
+ return state->status;
+}
+
+static int dib9000_set_channel_status(struct dvb_frontend *fe, struct dvb_frontend_parametersContext *channel_status)
+{
+ struct dib9000_state *state = fe->demodulator_priv;
+
+ memcpy(&state->channel_status, channel_status, sizeof(struct dvb_frontend_parametersContext));
+ return 0;
+}
+
+static int dib9000_set_frontend(struct dvb_frontend *fe, struct dvb_frontend_parameters *fep)
+{
+ struct dib9000_state *state = fe->demodulator_priv;
+ int sleep_time, sleep_time_slave;
+ u32 frontend_status;
+ u8 nbr_pending, exit_condition, index_frontend, index_frontend_success;
+ struct dvb_frontend_parametersContext channel_status;
+
+ /* check that the correct parameters are set */
+ if (state->fe[0]->dtv_property_cache.frequency == 0) {
+ dprintk("dib9000: must specify frequency ");
+ return 0;
+ }
+
+ if (state->fe[0]->dtv_property_cache.bandwidth_hz == 0) {
+ dprintk("dib9000: must specify bandwidth ");
+ return 0;
+ }
+ fe->dtv_property_cache.delivery_system = SYS_DVBT;
+
+ /* set the master status */
+ if (fep->u.ofdm.transmission_mode == TRANSMISSION_MODE_AUTO ||
+ fep->u.ofdm.guard_interval == GUARD_INTERVAL_AUTO || fep->u.ofdm.constellation == QAM_AUTO || fep->u.ofdm.code_rate_HP == FEC_AUTO) {
+ /* no channel specified, autosearch the channel */
+ state->channel_status.status = CHANNEL_STATUS_PARAMETERS_UNKNOWN;
+ } else
+ state->channel_status.status = CHANNEL_STATUS_PARAMETERS_SET;
+
+ /* set mode and status for the different frontends */
+ for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
+ dib9000_fw_set_diversity_in(state->fe[index_frontend], 1);
+
+ /* synchronization of the cache */
+ memcpy(&state->fe[index_frontend]->dtv_property_cache, &fe->dtv_property_cache, sizeof(struct dtv_frontend_properties));
+
+ state->fe[index_frontend]->dtv_property_cache.delivery_system = SYS_DVBT;
+ dib9000_fw_set_output_mode(state->fe[index_frontend], OUTMODE_HIGH_Z);
+
+ dib9000_set_channel_status(state->fe[index_frontend], &state->channel_status);
+ dib9000_set_tune_state(state->fe[index_frontend], CT_DEMOD_START);
+ }
+
+ /* actual tune */
+ exit_condition = 0; /* 0: tune pending; 1: tune failed; 2:tune success */
+ index_frontend_success = 0;
+ do {
+ sleep_time = dib9000_fw_tune(state->fe[0], NULL);
+ for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
+ sleep_time_slave = dib9000_fw_tune(state->fe[index_frontend], NULL);
+ if (sleep_time == FE_CALLBACK_TIME_NEVER)
+ sleep_time = sleep_time_slave;
+ else if ((sleep_time_slave != FE_CALLBACK_TIME_NEVER) && (sleep_time_slave > sleep_time))
+ sleep_time = sleep_time_slave;
+ }
+ if (sleep_time != FE_CALLBACK_TIME_NEVER)
+ msleep(sleep_time / 10);
+ else
+ break;
+
+ nbr_pending = 0;
+ exit_condition = 0;
+ index_frontend_success = 0;
+ for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
+ frontend_status = -dib9000_get_status(state->fe[index_frontend]);
+ if (frontend_status > -FE_STATUS_TUNE_PENDING) {
+ exit_condition = 2; /* tune success */
+ index_frontend_success = index_frontend;
+ break;
+ }
+ if (frontend_status == -FE_STATUS_TUNE_PENDING)
+ nbr_pending++; /* some frontends are still tuning */
+ }
+ if ((exit_condition != 2) && (nbr_pending == 0))
+ exit_condition = 1; /* if all tune are done and no success, exit: tune failed */
+
+ } while (exit_condition == 0);
+
+ /* check the tune result */
+ if (exit_condition == 1) { /* tune failed */
+ dprintk("tune failed");
+ return 0;
+ }
+
+ dprintk("tune success on frontend%i", index_frontend_success);
+
+ /* synchronize all the channel cache */
+ dib9000_get_frontend(state->fe[0], fep);
+
+ /* retune the other frontends with the found channel */
+ channel_status.status = CHANNEL_STATUS_PARAMETERS_SET;
+ for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
+ /* only retune the frontends which was not tuned success */
+ if (index_frontend != index_frontend_success) {
+ dib9000_set_channel_status(state->fe[index_frontend], &channel_status);
+ dib9000_set_tune_state(state->fe[index_frontend], CT_DEMOD_START);
+ }
+ }
+ do {
+ sleep_time = FE_CALLBACK_TIME_NEVER;
+ for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
+ if (index_frontend != index_frontend_success) {
+ sleep_time_slave = dib9000_fw_tune(state->fe[index_frontend], NULL);
+ if (sleep_time == FE_CALLBACK_TIME_NEVER)
+ sleep_time = sleep_time_slave;
+ else if ((sleep_time_slave != FE_CALLBACK_TIME_NEVER) && (sleep_time_slave > sleep_time))
+ sleep_time = sleep_time_slave;
+ }
+ }
+ if (sleep_time != FE_CALLBACK_TIME_NEVER)
+ msleep(sleep_time / 10);
+ else
+ break;
+
+ nbr_pending = 0;
+ for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
+ if (index_frontend != index_frontend_success) {
+ frontend_status = -dib9000_get_status(state->fe[index_frontend]);
+ if ((index_frontend != index_frontend_success) && (frontend_status == -FE_STATUS_TUNE_PENDING))
+ nbr_pending++; /* some frontends are still tuning */
+ }
+ }
+ } while (nbr_pending != 0);
+
+ /* set the output mode */
+ dib9000_fw_set_output_mode(state->fe[0], state->chip.d9.cfg.output_mode);
+ for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++)
+ dib9000_fw_set_output_mode(state->fe[index_frontend], OUTMODE_DIVERSITY);
+
+ /* turn off the diversity for the last frontend */
+ dib9000_fw_set_diversity_in(state->fe[index_frontend - 1], 0);
+
+ return 0;
+}
+
+static u16 dib9000_read_lock(struct dvb_frontend *fe)
+{
+ struct dib9000_state *state = fe->demodulator_priv;
+
+ return dib9000_read_word(state, 535);
+}
+
+static int dib9000_read_status(struct dvb_frontend *fe, fe_status_t * stat)
+{
+ struct dib9000_state *state = fe->demodulator_priv;
+ u8 index_frontend;
+ u16 lock = 0, lock_slave = 0;
+
+ for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++)
+ lock_slave |= dib9000_read_lock(state->fe[index_frontend]);
+
+ lock = dib9000_read_word(state, 535);
+
+ *stat = 0;
+
+ if ((lock & 0x8000) || (lock_slave & 0x8000))
+ *stat |= FE_HAS_SIGNAL;
+ if ((lock & 0x3000) || (lock_slave & 0x3000))
+ *stat |= FE_HAS_CARRIER;
+ if ((lock & 0x0100) || (lock_slave & 0x0100))
+ *stat |= FE_HAS_VITERBI;
+ if (((lock & 0x0038) == 0x38) || ((lock_slave & 0x0038) == 0x38))
+ *stat |= FE_HAS_SYNC;
+ if ((lock & 0x0008) || (lock_slave & 0x0008))
+ *stat |= FE_HAS_LOCK;
+
+ return 0;
+}
+
+static int dib9000_read_ber(struct dvb_frontend *fe, u32 * ber)
+{
+ struct dib9000_state *state = fe->demodulator_priv;
+ u16 c[16];
+
+ DibAcquireLock(&state->platform.risc.mem_mbx_lock);
+ if (dib9000_fw_memmbx_sync(state, FE_SYNC_CHANNEL) < 0)
+ return -EIO;
+ dib9000_risc_mem_read(state, FE_MM_R_FE_MONITOR, (u8 *) c, sizeof(c));
+ DibReleaseLock(&state->platform.risc.mem_mbx_lock);
+
+ *ber = c[10] << 16 | c[11];
+ return 0;
+}
+
+static int dib9000_read_signal_strength(struct dvb_frontend *fe, u16 * strength)
+{
+ struct dib9000_state *state = fe->demodulator_priv;
+ u8 index_frontend;
+ u16 c[16];
+ u16 val;
+
+ *strength = 0;
+ for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
+ state->fe[index_frontend]->ops.read_signal_strength(state->fe[index_frontend], &val);
+ if (val > 65535 - *strength)
+ *strength = 65535;
+ else
+ *strength += val;
+ }
+
+ DibAcquireLock(&state->platform.risc.mem_mbx_lock);
+ if (dib9000_fw_memmbx_sync(state, FE_SYNC_CHANNEL) < 0)
+ return -EIO;
+ dib9000_risc_mem_read(state, FE_MM_R_FE_MONITOR, (u8 *) c, sizeof(c));
+ DibReleaseLock(&state->platform.risc.mem_mbx_lock);
+
+ val = 65535 - c[4];
+ if (val > 65535 - *strength)
+ *strength = 65535;
+ else
+ *strength += val;
+ return 0;
+}
+
+static u32 dib9000_get_snr(struct dvb_frontend *fe)
+{
+ struct dib9000_state *state = fe->demodulator_priv;
+ u16 c[16];
+ u32 n, s, exp;
+ u16 val;
+
+ DibAcquireLock(&state->platform.risc.mem_mbx_lock);
+ if (dib9000_fw_memmbx_sync(state, FE_SYNC_CHANNEL) < 0)
+ return -EIO;
+ dib9000_risc_mem_read(state, FE_MM_R_FE_MONITOR, (u8 *) c, sizeof(c));
+ DibReleaseLock(&state->platform.risc.mem_mbx_lock);
+
+ val = c[7];
+ n = (val >> 4) & 0xff;
+ exp = ((val & 0xf) << 2);
+ val = c[8];
+ exp += ((val >> 14) & 0x3);
+ if ((exp & 0x20) != 0)
+ exp -= 0x40;
+ n <<= exp + 16;
+
+ s = (val >> 6) & 0xFF;
+ exp = (val & 0x3F);
+ if ((exp & 0x20) != 0)
+ exp -= 0x40;
+ s <<= exp + 16;
+
+ if (n > 0) {
+ u32 t = (s / n) << 16;
+ return t + ((s << 16) - n * t) / n;
+ }
+ return 0xffffffff;
+}
+
+static int dib9000_read_snr(struct dvb_frontend *fe, u16 * snr)
+{
+ struct dib9000_state *state = fe->demodulator_priv;
+ u8 index_frontend;
+ u32 snr_master;
+
+ snr_master = dib9000_get_snr(fe);
+ for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++)
+ snr_master += dib9000_get_snr(state->fe[index_frontend]);
+
+ if ((snr_master >> 16) != 0) {
+ snr_master = 10 * intlog10(snr_master >> 16);
+ *snr = snr_master / ((1 << 24) / 10);
+ } else
+ *snr = 0;
+
+ return 0;
+}
+
+static int dib9000_read_unc_blocks(struct dvb_frontend *fe, u32 * unc)
+{
+ struct dib9000_state *state = fe->demodulator_priv;
+ u16 c[16];
+
+ DibAcquireLock(&state->platform.risc.mem_mbx_lock);
+ if (dib9000_fw_memmbx_sync(state, FE_SYNC_CHANNEL) < 0)
+ return -EIO;
+ dib9000_risc_mem_read(state, FE_MM_R_FE_MONITOR, (u8 *) c, sizeof(c));
+ DibReleaseLock(&state->platform.risc.mem_mbx_lock);
+
+ *unc = c[12];
+ return 0;
+}
+
+int dib9000_i2c_enumeration(struct i2c_adapter *i2c, int no_of_demods, u8 default_addr, u8 first_addr)
+{
+ int k = 0;
+ u8 new_addr = 0;
+ struct i2c_device client = {.i2c_adap = i2c };
+
+ client.i2c_addr = default_addr + 16;
+ dib9000_i2c_write16(&client, 1796, 0x0);
+
+ for (k = no_of_demods - 1; k >= 0; k--) {
+ /* designated i2c address */
+ new_addr = first_addr + (k << 1);
+ client.i2c_addr = default_addr;
+
+ dib9000_i2c_write16(&client, 1817, 3);
+ dib9000_i2c_write16(&client, 1796, 0);
+ dib9000_i2c_write16(&client, 1227, 1);
+ dib9000_i2c_write16(&client, 1227, 0);
+
+ client.i2c_addr = new_addr;
+ dib9000_i2c_write16(&client, 1817, 3);
+ dib9000_i2c_write16(&client, 1796, 0);
+ dib9000_i2c_write16(&client, 1227, 1);
+ dib9000_i2c_write16(&client, 1227, 0);
+
+ if (dib9000_identify(&client) == 0) {
+ client.i2c_addr = default_addr;
+ if (dib9000_identify(&client) == 0) {
+ dprintk("DiB9000 #%d: not identified", k);
+ return -EIO;
+ }
+ }
+
+ dib9000_i2c_write16(&client, 1795, (1 << 10) | (4 << 6));
+ dib9000_i2c_write16(&client, 1794, (new_addr << 2) | 2);
+
+ dprintk("IC %d initialized (to i2c_address 0x%x)", k, new_addr);
+ }
+
+ for (k = 0; k < no_of_demods; k++) {
+ new_addr = first_addr | (k << 1);
+ client.i2c_addr = new_addr;
+
+ dib9000_i2c_write16(&client, 1794, (new_addr << 2));
+ dib9000_i2c_write16(&client, 1795, 0);
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL(dib9000_i2c_enumeration);
+
+int dib9000_set_slave_frontend(struct dvb_frontend *fe, struct dvb_frontend *fe_slave)
+{
+ struct dib9000_state *state = fe->demodulator_priv;
+ u8 index_frontend = 1;
+
+ while ((index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL))
+ index_frontend++;
+ if (index_frontend < MAX_NUMBER_OF_FRONTENDS) {
+ dprintk("set slave fe %p to index %i", fe_slave, index_frontend);
+ state->fe[index_frontend] = fe_slave;
+ return 0;
+ }
+
+ dprintk("too many slave frontend");
+ return -ENOMEM;
+}
+EXPORT_SYMBOL(dib9000_set_slave_frontend);
+
+int dib9000_remove_slave_frontend(struct dvb_frontend *fe)
+{
+ struct dib9000_state *state = fe->demodulator_priv;
+ u8 index_frontend = 1;
+
+ while ((index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL))
+ index_frontend++;
+ if (index_frontend != 1) {
+ dprintk("remove slave fe %p (index %i)", state->fe[index_frontend - 1], index_frontend - 1);
+ state->fe[index_frontend] = NULL;
+ return 0;
+ }
+
+ dprintk("no frontend to be removed");
+ return -ENODEV;
+}
+EXPORT_SYMBOL(dib9000_remove_slave_frontend);
+
+struct dvb_frontend *dib9000_get_slave_frontend(struct dvb_frontend *fe, int slave_index)
+{
+ struct dib9000_state *state = fe->demodulator_priv;
+
+ if (slave_index >= MAX_NUMBER_OF_FRONTENDS)
+ return NULL;
+ return state->fe[slave_index];
+}
+EXPORT_SYMBOL(dib9000_get_slave_frontend);
+
+static struct dvb_frontend_ops dib9000_ops;
+struct dvb_frontend *dib9000_attach(struct i2c_adapter *i2c_adap, u8 i2c_addr, const struct dib9000_config *cfg)
+{
+ struct dvb_frontend *fe;
+ struct dib9000_state *st;
+ st = kzalloc(sizeof(struct dib9000_state), GFP_KERNEL);
+ if (st == NULL)
+ return NULL;
+ fe = kzalloc(sizeof(struct dvb_frontend), GFP_KERNEL);
+ if (fe == NULL)
+ return NULL;
+
+ memcpy(&st->chip.d9.cfg, cfg, sizeof(struct dib9000_config));
+ st->i2c.i2c_adap = i2c_adap;
+ st->i2c.i2c_addr = i2c_addr;
+
+ st->gpio_dir = DIB9000_GPIO_DEFAULT_DIRECTIONS;
+ st->gpio_val = DIB9000_GPIO_DEFAULT_VALUES;
+ st->gpio_pwm_pos = DIB9000_GPIO_DEFAULT_PWM_POS;
+
+ DibInitLock(&st->platform.risc.mbx_if_lock);
+ DibInitLock(&st->platform.risc.mbx_lock);
+ DibInitLock(&st->platform.risc.mem_lock);
+ DibInitLock(&st->platform.risc.mem_mbx_lock);
+
+ st->fe[0] = fe;
+ fe->demodulator_priv = st;
+ memcpy(&st->fe[0]->ops, &dib9000_ops, sizeof(struct dvb_frontend_ops));
+
+ /* Ensure the output mode remains at the previous default if it's
+ * not specifically set by the caller.
+ */
+ if ((st->chip.d9.cfg.output_mode != OUTMODE_MPEG2_SERIAL) && (st->chip.d9.cfg.output_mode != OUTMODE_MPEG2_PAR_GATED_CLK))
+ st->chip.d9.cfg.output_mode = OUTMODE_MPEG2_FIFO;
+
+ if (dib9000_identify(&st->i2c) == 0)
+ goto error;
+
+ dibx000_init_i2c_master(&st->i2c_master, DIB7000MC, st->i2c.i2c_adap, st->i2c.i2c_addr);
+
+ st->tuner_adap.dev.parent = i2c_adap->dev.parent;
+ strncpy(st->tuner_adap.name, "DIB9000_FW TUNER ACCESS", sizeof(st->tuner_adap.name));
+ st->tuner_adap.algo = &dib9000_tuner_algo;
+ st->tuner_adap.algo_data = NULL;
+ i2c_set_adapdata(&st->tuner_adap, st);
+ if (i2c_add_adapter(&st->tuner_adap) < 0)
+ goto error;
+
+ st->component_bus.dev.parent = i2c_adap->dev.parent;
+ strncpy(st->component_bus.name, "DIB9000_FW COMPONENT BUS ACCESS", sizeof(st->component_bus.name));
+ st->component_bus.algo = &dib9000_component_bus_algo;
+ st->component_bus.algo_data = NULL;
+ st->component_bus_speed = 340;
+ i2c_set_adapdata(&st->component_bus, st);
+ if (i2c_add_adapter(&st->component_bus) < 0)
+ goto component_bus_add_error;
+
+ dib9000_fw_reset(fe);
+
+ return fe;
+
+component_bus_add_error:
+ i2c_del_adapter(&st->tuner_adap);
+error:
+ kfree(st);
+ return NULL;
+}
+EXPORT_SYMBOL(dib9000_attach);
+
+static struct dvb_frontend_ops dib9000_ops = {
+ .info = {
+ .name = "DiBcom 9000",
+ .type = FE_OFDM,
+ .frequency_min = 44250000,
+ .frequency_max = 867250000,
+ .frequency_stepsize = 62500,
+ .caps = FE_CAN_INVERSION_AUTO |
+ FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
+ FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
+ FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
+ FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_RECOVER | FE_CAN_HIERARCHY_AUTO,
+ },
+
+ .release = dib9000_release,
+
+ .init = dib9000_wakeup,
+ .sleep = dib9000_sleep,
+
+ .set_frontend = dib9000_set_frontend,
+ .get_tune_settings = dib9000_fe_get_tune_settings,
+ .get_frontend = dib9000_get_frontend,
+
+ .read_status = dib9000_read_status,
+ .read_ber = dib9000_read_ber,
+ .read_signal_strength = dib9000_read_signal_strength,
+ .read_snr = dib9000_read_snr,
+ .read_ucblocks = dib9000_read_unc_blocks,
+};
+
+MODULE_AUTHOR("Patrick Boettcher <pboettcher@dibcom.fr>");
+MODULE_AUTHOR("Olivier Grenie <ogrenie@dibcom.fr>");
+MODULE_DESCRIPTION("Driver for the DiBcom 9000 COFDM demodulator");
+MODULE_LICENSE("GPL");
diff --git a/drivers/media/dvb/frontends/dib9000.h b/drivers/media/dvb/frontends/dib9000.h
new file mode 100644
index 00000000000..b5781a48034
--- /dev/null
+++ b/drivers/media/dvb/frontends/dib9000.h
@@ -0,0 +1,131 @@
+#ifndef DIB9000_H
+#define DIB9000_H
+
+#include "dibx000_common.h"
+
+struct dib9000_config {
+ u8 dvbt_mode;
+ u8 output_mpeg2_in_188_bytes;
+ u8 hostbus_diversity;
+ struct dibx000_bandwidth_config *bw;
+
+ u16 if_drives;
+
+ u32 timing_frequency;
+ u32 xtal_clock_khz;
+ u32 vcxo_timer;
+ u32 demod_clock_khz;
+
+ const u8 *microcode_B_fe_buffer;
+ u32 microcode_B_fe_size;
+
+ struct dibGPIOFunction gpio_function[2];
+ struct dibSubbandSelection subband;
+
+ u8 output_mode;
+};
+
+#define DEFAULT_DIB9000_I2C_ADDRESS 18
+
+#if defined(CONFIG_DVB_DIB9000) || (defined(CONFIG_DVB_DIB9000_MODULE) && defined(MODULE))
+extern struct dvb_frontend *dib9000_attach(struct i2c_adapter *i2c_adap, u8 i2c_addr, const struct dib9000_config *cfg);
+extern int dib9000_i2c_enumeration(struct i2c_adapter *host, int no_of_demods, u8 default_addr, u8 first_addr);
+extern struct i2c_adapter *dib9000_get_tuner_interface(struct dvb_frontend *fe);
+extern struct i2c_adapter *dib9000_get_i2c_master(struct dvb_frontend *fe, enum dibx000_i2c_interface intf, int gating);
+extern int dib9000_set_gpio(struct dvb_frontend *fe, u8 num, u8 dir, u8 val);
+extern int dib9000_fw_pid_filter_ctrl(struct dvb_frontend *fe, u8 onoff);
+extern int dib9000_fw_pid_filter(struct dvb_frontend *fe, u8 id, u16 pid, u8 onoff);
+extern int dib9000_firmware_post_pll_init(struct dvb_frontend *fe);
+extern int dib9000_set_slave_frontend(struct dvb_frontend *fe, struct dvb_frontend *fe_slave);
+extern int dib9000_remove_slave_frontend(struct dvb_frontend *fe);
+extern struct dvb_frontend *dib9000_get_slave_frontend(struct dvb_frontend *fe, int slave_index);
+extern struct i2c_adapter *dib9000_get_component_bus_interface(struct dvb_frontend *fe);
+extern int dib9000_set_i2c_adapter(struct dvb_frontend *fe, struct i2c_adapter *i2c);
+extern int dib9000_fw_set_component_bus_speed(struct dvb_frontend *fe, u16 speed);
+#else
+static inline struct dvb_frontend *dib9000_attach(struct i2c_adapter *i2c_adap, u8 i2c_addr, struct dib9000_config *cfg)
+{
+ printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
+ return NULL;
+}
+
+static inline struct i2c_adapter *dib9000_get_i2c_master(struct dvb_frontend *fe, enum dibx000_i2c_interface intf, int gating)
+{
+ printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
+ return NULL;
+}
+
+static inline int dib9000_i2c_enumeration(struct i2c_adapter *host, int no_of_demods, u8 default_addr, u8 first_addr)
+{
+ printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
+ return -ENODEV;
+}
+
+static inline struct i2c_adapter *dib9000_get_tuner_interface(struct dvb_frontend *fe)
+{
+ printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
+ return NULL;
+}
+
+static inline int dib9000_set_gpio(struct dvb_frontend *fe, u8 num, u8 dir, u8 val)
+{
+ printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
+ return -ENODEV;
+}
+
+static inline int dib9000_fw_pid_filter_ctrl(struct dvb_frontend *fe, u8 onoff)
+{
+ printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
+ return -ENODEV;
+}
+
+static inline int dib9000_fw_pid_filter(struct dvb_frontend *fe, u8 id, u16 pid, u8 onoff)
+{
+ printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
+ return -ENODEV;
+}
+
+static inline int dib9000_firmware_post_pll_init(struct dvb_frontend *fe)
+{
+ printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
+ return -ENODEV;
+}
+
+static inline int dib9000_set_slave_frontend(struct dvb_frontend *fe, struct dvb_frontend *fe_slave)
+{
+ printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
+ return -ENODEV;
+}
+
+int dib9000_remove_slave_frontend(struct dvb_frontend *fe)
+{
+ printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
+ return -ENODEV;
+}
+
+static inline struct dvb_frontend *dib9000_get_slave_frontend(struct dvb_frontend *fe, int slave_index)
+{
+ printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
+ return NULL;
+}
+
+static inline struct i2c_adapter *dib9000_get_component_bus_interface(struct dvb_frontend *fe)
+{
+ printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
+ return NULL;
+}
+
+static inline int dib9000_set_i2c_adapter(struct dvb_frontend *fe, struct i2c_adapter *i2c)
+{
+ printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
+ return -ENODEV;
+}
+
+static inline int dib9000_fw_set_component_bus_speed(struct dvb_frontend *fe, u16 speed)
+{
+ printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
+ return -ENODEV;
+}
+#endif
+
+#endif
diff --git a/drivers/media/dvb/frontends/dibx000_common.c b/drivers/media/dvb/frontends/dibx000_common.c
index 2311c0a3406..f6938f97feb 100644
--- a/drivers/media/dvb/frontends/dibx000_common.c
+++ b/drivers/media/dvb/frontends/dibx000_common.c
@@ -17,9 +17,145 @@ static int dibx000_write_word(struct dibx000_i2c_master *mst, u16 reg, u16 val)
struct i2c_msg msg = {
.addr = mst->i2c_addr,.flags = 0,.buf = b,.len = 4
};
+
return i2c_transfer(mst->i2c_adap, &msg, 1) != 1 ? -EREMOTEIO : 0;
}
+static u16 dibx000_read_word(struct dibx000_i2c_master *mst, u16 reg)
+{
+ u8 wb[2] = { reg >> 8, reg & 0xff };
+ u8 rb[2];
+ struct i2c_msg msg[2] = {
+ {.addr = mst->i2c_addr, .flags = 0, .buf = wb, .len = 2},
+ {.addr = mst->i2c_addr, .flags = I2C_M_RD, .buf = rb, .len = 2},
+ };
+
+ if (i2c_transfer(mst->i2c_adap, msg, 2) != 2)
+ dprintk("i2c read error on %d", reg);
+
+ return (rb[0] << 8) | rb[1];
+}
+
+static int dibx000_is_i2c_done(struct dibx000_i2c_master *mst)
+{
+ int i = 100;
+ u16 status;
+
+ while (((status = dibx000_read_word(mst, mst->base_reg + 2)) & 0x0100) == 0 && --i > 0)
+ ;
+
+ /* i2c timed out */
+ if (i == 0)
+ return -EREMOTEIO;
+
+ /* no acknowledge */
+ if ((status & 0x0080) == 0)
+ return -EREMOTEIO;
+
+ return 0;
+}
+
+static int dibx000_master_i2c_write(struct dibx000_i2c_master *mst, struct i2c_msg *msg, u8 stop)
+{
+ u16 data;
+ u16 da;
+ u16 i;
+ u16 txlen = msg->len, len;
+ const u8 *b = msg->buf;
+
+ while (txlen) {
+ dibx000_read_word(mst, mst->base_reg + 2);
+
+ len = txlen > 8 ? 8 : txlen;
+ for (i = 0; i < len; i += 2) {
+ data = *b++ << 8;
+ if (i+1 < len)
+ data |= *b++;
+ dibx000_write_word(mst, mst->base_reg, data);
+ }
+ da = (((u8) (msg->addr)) << 9) |
+ (1 << 8) |
+ (1 << 7) |
+ (0 << 6) |
+ (0 << 5) |
+ ((len & 0x7) << 2) |
+ (0 << 1) |
+ (0 << 0);
+
+ if (txlen == msg->len)
+ da |= 1 << 5; /* start */
+
+ if (txlen-len == 0 && stop)
+ da |= 1 << 6; /* stop */
+
+ dibx000_write_word(mst, mst->base_reg+1, da);
+
+ if (dibx000_is_i2c_done(mst) != 0)
+ return -EREMOTEIO;
+ txlen -= len;
+ }
+
+ return 0;
+}
+
+static int dibx000_master_i2c_read(struct dibx000_i2c_master *mst, struct i2c_msg *msg)
+{
+ u16 da;
+ u8 *b = msg->buf;
+ u16 rxlen = msg->len, len;
+
+ while (rxlen) {
+ len = rxlen > 8 ? 8 : rxlen;
+ da = (((u8) (msg->addr)) << 9) |
+ (1 << 8) |
+ (1 << 7) |
+ (0 << 6) |
+ (0 << 5) |
+ ((len & 0x7) << 2) |
+ (1 << 1) |
+ (0 << 0);
+
+ if (rxlen == msg->len)
+ da |= 1 << 5; /* start */
+
+ if (rxlen-len == 0)
+ da |= 1 << 6; /* stop */
+ dibx000_write_word(mst, mst->base_reg+1, da);
+
+ if (dibx000_is_i2c_done(mst) != 0)
+ return -EREMOTEIO;
+
+ rxlen -= len;
+
+ while (len) {
+ da = dibx000_read_word(mst, mst->base_reg);
+ *b++ = (da >> 8) & 0xff;
+ len--;
+ if (len >= 1) {
+ *b++ = da & 0xff;
+ len--;
+ }
+ }
+ }
+
+ return 0;
+}
+
+int dibx000_i2c_set_speed(struct i2c_adapter *i2c_adap, u16 speed)
+{
+ struct dibx000_i2c_master *mst = i2c_get_adapdata(i2c_adap);
+
+ if (mst->device_rev < DIB7000MC && speed < 235)
+ speed = 235;
+ return dibx000_write_word(mst, mst->base_reg + 3, (u16)(60000 / speed));
+
+}
+EXPORT_SYMBOL(dibx000_i2c_set_speed);
+
+static u32 dibx000_i2c_func(struct i2c_adapter *adapter)
+{
+ return I2C_FUNC_I2C;
+}
static int dibx000_i2c_select_interface(struct dibx000_i2c_master *mst,
enum dibx000_i2c_interface intf)
@@ -32,6 +168,60 @@ static int dibx000_i2c_select_interface(struct dibx000_i2c_master *mst,
return 0;
}
+static int dibx000_i2c_master_xfer_gpio12(struct i2c_adapter *i2c_adap, struct i2c_msg msg[], int num)
+{
+ struct dibx000_i2c_master *mst = i2c_get_adapdata(i2c_adap);
+ int msg_index;
+ int ret = 0;
+
+ dibx000_i2c_select_interface(mst, DIBX000_I2C_INTERFACE_GPIO_1_2);
+ for (msg_index = 0; msg_index < num; msg_index++) {
+ if (msg[msg_index].flags & I2C_M_RD) {
+ ret = dibx000_master_i2c_read(mst, &msg[msg_index]);
+ if (ret != 0)
+ return 0;
+ } else {
+ ret = dibx000_master_i2c_write(mst, &msg[msg_index], 1);
+ if (ret != 0)
+ return 0;
+ }
+ }
+
+ return num;
+}
+
+static int dibx000_i2c_master_xfer_gpio34(struct i2c_adapter *i2c_adap, struct i2c_msg msg[], int num)
+{
+ struct dibx000_i2c_master *mst = i2c_get_adapdata(i2c_adap);
+ int msg_index;
+ int ret = 0;
+
+ dibx000_i2c_select_interface(mst, DIBX000_I2C_INTERFACE_GPIO_3_4);
+ for (msg_index = 0; msg_index < num; msg_index++) {
+ if (msg[msg_index].flags & I2C_M_RD) {
+ ret = dibx000_master_i2c_read(mst, &msg[msg_index]);
+ if (ret != 0)
+ return 0;
+ } else {
+ ret = dibx000_master_i2c_write(mst, &msg[msg_index], 1);
+ if (ret != 0)
+ return 0;
+ }
+ }
+
+ return num;
+}
+
+static struct i2c_algorithm dibx000_i2c_master_gpio12_xfer_algo = {
+ .master_xfer = dibx000_i2c_master_xfer_gpio12,
+ .functionality = dibx000_i2c_func,
+};
+
+static struct i2c_algorithm dibx000_i2c_master_gpio34_xfer_algo = {
+ .master_xfer = dibx000_i2c_master_xfer_gpio34,
+ .functionality = dibx000_i2c_func,
+};
+
static int dibx000_i2c_gate_ctrl(struct dibx000_i2c_master *mst, u8 tx[4],
u8 addr, int onoff)
{
@@ -54,11 +244,37 @@ static int dibx000_i2c_gate_ctrl(struct dibx000_i2c_master *mst, u8 tx[4],
return 0;
}
-static u32 dibx000_i2c_func(struct i2c_adapter *adapter)
+static int dibx000_i2c_gated_gpio67_xfer(struct i2c_adapter *i2c_adap,
+ struct i2c_msg msg[], int num)
{
- return I2C_FUNC_I2C;
+ struct dibx000_i2c_master *mst = i2c_get_adapdata(i2c_adap);
+ struct i2c_msg m[2 + num];
+ u8 tx_open[4], tx_close[4];
+
+ memset(m, 0, sizeof(struct i2c_msg) * (2 + num));
+
+ dibx000_i2c_select_interface(mst, DIBX000_I2C_INTERFACE_GPIO_6_7);
+
+ dibx000_i2c_gate_ctrl(mst, tx_open, msg[0].addr, 1);
+ m[0].addr = mst->i2c_addr;
+ m[0].buf = tx_open;
+ m[0].len = 4;
+
+ memcpy(&m[1], msg, sizeof(struct i2c_msg) * num);
+
+ dibx000_i2c_gate_ctrl(mst, tx_close, 0, 0);
+ m[num + 1].addr = mst->i2c_addr;
+ m[num + 1].buf = tx_close;
+ m[num + 1].len = 4;
+
+ return i2c_transfer(mst->i2c_adap, m, 2 + num) == 2 + num ? num : -EIO;
}
+static struct i2c_algorithm dibx000_i2c_gated_gpio67_algo = {
+ .master_xfer = dibx000_i2c_gated_gpio67_xfer,
+ .functionality = dibx000_i2c_func,
+};
+
static int dibx000_i2c_gated_tuner_xfer(struct i2c_adapter *i2c_adap,
struct i2c_msg msg[], int num)
{
@@ -91,8 +307,8 @@ static struct i2c_algorithm dibx000_i2c_gated_tuner_algo = {
};
struct i2c_adapter *dibx000_get_i2c_adapter(struct dibx000_i2c_master *mst,
- enum dibx000_i2c_interface intf,
- int gating)
+ enum dibx000_i2c_interface intf,
+ int gating)
{
struct i2c_adapter *i2c = NULL;
@@ -101,6 +317,18 @@ struct i2c_adapter *dibx000_get_i2c_adapter(struct dibx000_i2c_master *mst,
if (gating)
i2c = &mst->gated_tuner_i2c_adap;
break;
+ case DIBX000_I2C_INTERFACE_GPIO_1_2:
+ if (!gating)
+ i2c = &mst->master_i2c_adap_gpio12;
+ break;
+ case DIBX000_I2C_INTERFACE_GPIO_3_4:
+ if (!gating)
+ i2c = &mst->master_i2c_adap_gpio34;
+ break;
+ case DIBX000_I2C_INTERFACE_GPIO_6_7:
+ if (gating)
+ i2c = &mst->master_i2c_adap_gpio67;
+ break;
default:
printk(KERN_ERR "DiBX000: incorrect I2C interface selected\n");
break;
@@ -126,8 +354,8 @@ void dibx000_reset_i2c_master(struct dibx000_i2c_master *mst)
EXPORT_SYMBOL(dibx000_reset_i2c_master);
static int i2c_adapter_init(struct i2c_adapter *i2c_adap,
- struct i2c_algorithm *algo, const char *name,
- struct dibx000_i2c_master *mst)
+ struct i2c_algorithm *algo, const char *name,
+ struct dibx000_i2c_master *mst)
{
strncpy(i2c_adap->name, name, sizeof(i2c_adap->name));
i2c_adap->algo = algo;
@@ -139,7 +367,7 @@ static int i2c_adapter_init(struct i2c_adapter *i2c_adap,
}
int dibx000_init_i2c_master(struct dibx000_i2c_master *mst, u16 device_rev,
- struct i2c_adapter *i2c_adap, u8 i2c_addr)
+ struct i2c_adapter *i2c_adap, u8 i2c_addr)
{
u8 tx[4];
struct i2c_msg m = {.addr = i2c_addr >> 1,.buf = tx,.len = 4 };
@@ -153,11 +381,33 @@ int dibx000_init_i2c_master(struct dibx000_i2c_master *mst, u16 device_rev,
else
mst->base_reg = 768;
+ mst->gated_tuner_i2c_adap.dev.parent = mst->i2c_adap->dev.parent;
+ if (i2c_adapter_init
+ (&mst->gated_tuner_i2c_adap, &dibx000_i2c_gated_tuner_algo,
+ "DiBX000 tuner I2C bus", mst) != 0)
+ printk(KERN_ERR
+ "DiBX000: could not initialize the tuner i2c_adapter\n");
+
+ mst->master_i2c_adap_gpio12.dev.parent = mst->i2c_adap->dev.parent;
+ if (i2c_adapter_init
+ (&mst->master_i2c_adap_gpio12, &dibx000_i2c_master_gpio12_xfer_algo,
+ "DiBX000 master GPIO12 I2C bus", mst) != 0)
+ printk(KERN_ERR
+ "DiBX000: could not initialize the master i2c_adapter\n");
+
+ mst->master_i2c_adap_gpio34.dev.parent = mst->i2c_adap->dev.parent;
+ if (i2c_adapter_init
+ (&mst->master_i2c_adap_gpio34, &dibx000_i2c_master_gpio34_xfer_algo,
+ "DiBX000 master GPIO34 I2C bus", mst) != 0)
+ printk(KERN_ERR
+ "DiBX000: could not initialize the master i2c_adapter\n");
+
+ mst->master_i2c_adap_gpio67.dev.parent = mst->i2c_adap->dev.parent;
if (i2c_adapter_init
- (&mst->gated_tuner_i2c_adap, &dibx000_i2c_gated_tuner_algo,
- "DiBX000 tuner I2C bus", mst) != 0)
+ (&mst->master_i2c_adap_gpio67, &dibx000_i2c_gated_gpio67_algo,
+ "DiBX000 master GPIO67 I2C bus", mst) != 0)
printk(KERN_ERR
- "DiBX000: could not initialize the tuner i2c_adapter\n");
+ "DiBX000: could not initialize the master i2c_adapter\n");
/* initialize the i2c-master by closing the gate */
dibx000_i2c_gate_ctrl(mst, tx, 0, 0);
@@ -170,16 +420,19 @@ EXPORT_SYMBOL(dibx000_init_i2c_master);
void dibx000_exit_i2c_master(struct dibx000_i2c_master *mst)
{
i2c_del_adapter(&mst->gated_tuner_i2c_adap);
+ i2c_del_adapter(&mst->master_i2c_adap_gpio12);
+ i2c_del_adapter(&mst->master_i2c_adap_gpio34);
+ i2c_del_adapter(&mst->master_i2c_adap_gpio67);
}
EXPORT_SYMBOL(dibx000_exit_i2c_master);
u32 systime(void)
{
- struct timespec t;
+ struct timespec t;
- t = current_kernel_time();
- return (t.tv_sec * 10000) + (t.tv_nsec / 100000);
+ t = current_kernel_time();
+ return (t.tv_sec * 10000) + (t.tv_nsec / 100000);
}
EXPORT_SYMBOL(systime);
diff --git a/drivers/media/dvb/frontends/dibx000_common.h b/drivers/media/dvb/frontends/dibx000_common.h
index 4f5d141a308..977d343369a 100644
--- a/drivers/media/dvb/frontends/dibx000_common.h
+++ b/drivers/media/dvb/frontends/dibx000_common.h
@@ -4,7 +4,8 @@
enum dibx000_i2c_interface {
DIBX000_I2C_INTERFACE_TUNER = 0,
DIBX000_I2C_INTERFACE_GPIO_1_2 = 1,
- DIBX000_I2C_INTERFACE_GPIO_3_4 = 2
+ DIBX000_I2C_INTERFACE_GPIO_3_4 = 2,
+ DIBX000_I2C_INTERFACE_GPIO_6_7 = 3
};
struct dibx000_i2c_master {
@@ -17,8 +18,11 @@ struct dibx000_i2c_master {
enum dibx000_i2c_interface selected_interface;
-// struct i2c_adapter tuner_i2c_adap;
+/* struct i2c_adapter tuner_i2c_adap; */
struct i2c_adapter gated_tuner_i2c_adap;
+ struct i2c_adapter master_i2c_adap_gpio12;
+ struct i2c_adapter master_i2c_adap_gpio34;
+ struct i2c_adapter master_i2c_adap_gpio67;
struct i2c_adapter *i2c_adap;
u8 i2c_addr;
@@ -27,14 +31,15 @@ struct dibx000_i2c_master {
};
extern int dibx000_init_i2c_master(struct dibx000_i2c_master *mst,
- u16 device_rev, struct i2c_adapter *i2c_adap,
- u8 i2c_addr);
+ u16 device_rev, struct i2c_adapter *i2c_adap,
+ u8 i2c_addr);
extern struct i2c_adapter *dibx000_get_i2c_adapter(struct dibx000_i2c_master
- *mst,
- enum dibx000_i2c_interface
- intf, int gating);
+ *mst,
+ enum dibx000_i2c_interface
+ intf, int gating);
extern void dibx000_exit_i2c_master(struct dibx000_i2c_master *mst);
extern void dibx000_reset_i2c_master(struct dibx000_i2c_master *mst);
+extern int dibx000_i2c_set_speed(struct i2c_adapter *i2c_adap, u16 speed);
extern u32 systime(void);
@@ -42,7 +47,7 @@ extern u32 systime(void);
#define BAND_UHF 0x02
#define BAND_VHF 0x04
#define BAND_SBAND 0x08
-#define BAND_FM 0x10
+#define BAND_FM 0x10
#define BAND_CBAND 0x20
#define BAND_OF_FREQUENCY(freq_kHz) ((freq_kHz) <= 170000 ? BAND_CBAND : \
@@ -135,9 +140,9 @@ enum dibx000_adc_states {
DIBX000_VBG_DISABLE,
};
-#define BANDWIDTH_TO_KHZ(v) ( (v) == BANDWIDTH_8_MHZ ? 8000 : \
- (v) == BANDWIDTH_7_MHZ ? 7000 : \
- (v) == BANDWIDTH_6_MHZ ? 6000 : 8000 )
+#define BANDWIDTH_TO_KHZ(v) ((v) == BANDWIDTH_8_MHZ ? 8000 : \
+ (v) == BANDWIDTH_7_MHZ ? 7000 : \
+ (v) == BANDWIDTH_6_MHZ ? 6000 : 8000)
#define BANDWIDTH_TO_INDEX(v) ( \
(v) == 8000 ? BANDWIDTH_8_MHZ : \
@@ -153,53 +158,57 @@ enum dibx000_adc_states {
#define OUTMODE_MPEG2_FIFO 5
#define OUTMODE_ANALOG_ADC 6
+#define INPUT_MODE_OFF 0x11
+#define INPUT_MODE_DIVERSITY 0x12
+#define INPUT_MODE_MPEG 0x13
+
enum frontend_tune_state {
- CT_TUNER_START = 10,
- CT_TUNER_STEP_0,
- CT_TUNER_STEP_1,
- CT_TUNER_STEP_2,
- CT_TUNER_STEP_3,
- CT_TUNER_STEP_4,
- CT_TUNER_STEP_5,
- CT_TUNER_STEP_6,
- CT_TUNER_STEP_7,
- CT_TUNER_STOP,
-
- CT_AGC_START = 20,
- CT_AGC_STEP_0,
- CT_AGC_STEP_1,
- CT_AGC_STEP_2,
- CT_AGC_STEP_3,
- CT_AGC_STEP_4,
- CT_AGC_STOP,
+ CT_TUNER_START = 10,
+ CT_TUNER_STEP_0,
+ CT_TUNER_STEP_1,
+ CT_TUNER_STEP_2,
+ CT_TUNER_STEP_3,
+ CT_TUNER_STEP_4,
+ CT_TUNER_STEP_5,
+ CT_TUNER_STEP_6,
+ CT_TUNER_STEP_7,
+ CT_TUNER_STOP,
+
+ CT_AGC_START = 20,
+ CT_AGC_STEP_0,
+ CT_AGC_STEP_1,
+ CT_AGC_STEP_2,
+ CT_AGC_STEP_3,
+ CT_AGC_STEP_4,
+ CT_AGC_STOP,
CT_DEMOD_START = 30,
- CT_DEMOD_STEP_1,
- CT_DEMOD_STEP_2,
- CT_DEMOD_STEP_3,
- CT_DEMOD_STEP_4,
- CT_DEMOD_STEP_5,
- CT_DEMOD_STEP_6,
- CT_DEMOD_STEP_7,
- CT_DEMOD_STEP_8,
- CT_DEMOD_STEP_9,
- CT_DEMOD_STEP_10,
- CT_DEMOD_SEARCH_NEXT = 41,
- CT_DEMOD_STEP_LOCKED,
- CT_DEMOD_STOP,
-
- CT_DONE = 100,
- CT_SHUTDOWN,
+ CT_DEMOD_STEP_1,
+ CT_DEMOD_STEP_2,
+ CT_DEMOD_STEP_3,
+ CT_DEMOD_STEP_4,
+ CT_DEMOD_STEP_5,
+ CT_DEMOD_STEP_6,
+ CT_DEMOD_STEP_7,
+ CT_DEMOD_STEP_8,
+ CT_DEMOD_STEP_9,
+ CT_DEMOD_STEP_10,
+ CT_DEMOD_SEARCH_NEXT = 41,
+ CT_DEMOD_STEP_LOCKED,
+ CT_DEMOD_STOP,
+
+ CT_DONE = 100,
+ CT_SHUTDOWN,
};
struct dvb_frontend_parametersContext {
#define CHANNEL_STATUS_PARAMETERS_UNKNOWN 0x01
#define CHANNEL_STATUS_PARAMETERS_SET 0x02
- u8 status;
- u32 tune_time_estimation[2];
- s32 tps_available;
- u16 tps[9];
+ u8 status;
+ u32 tune_time_estimation[2];
+ s32 tps_available;
+ u16 tps[9];
};
#define FE_STATUS_TUNE_FAILED 0
@@ -216,4 +225,49 @@ struct dvb_frontend_parametersContext {
#define ABS(x) ((x < 0) ? (-x) : (x))
+#define DATA_BUS_ACCESS_MODE_8BIT 0x01
+#define DATA_BUS_ACCESS_MODE_16BIT 0x02
+#define DATA_BUS_ACCESS_MODE_NO_ADDRESS_INCREMENT 0x10
+
+struct dibGPIOFunction {
+#define BOARD_GPIO_COMPONENT_BUS_ADAPTER 1
+#define BOARD_GPIO_COMPONENT_DEMOD 2
+ u8 component;
+
+#define BOARD_GPIO_FUNCTION_BOARD_ON 1
+#define BOARD_GPIO_FUNCTION_BOARD_OFF 2
+#define BOARD_GPIO_FUNCTION_COMPONENT_ON 3
+#define BOARD_GPIO_FUNCTION_COMPONENT_OFF 4
+#define BOARD_GPIO_FUNCTION_SUBBAND_PWM 5
+#define BOARD_GPIO_FUNCTION_SUBBAND_GPIO 6
+ u8 function;
+
+/* mask, direction and value are used specify which GPIO to change GPIO0
+ * is LSB and possible GPIO31 is MSB. The same bit-position as in the
+ * mask is used for the direction and the value. Direction == 1 is OUT,
+ * 0 == IN. For direction "OUT" value is either 1 or 0, for direction IN
+ * value has no meaning.
+ *
+ * In case of BOARD_GPIO_FUNCTION_PWM mask is giving the GPIO to be
+ * used to do the PWM. Direction gives the PWModulator to be used.
+ * Value gives the PWM value in device-dependent scale.
+ */
+ u32 mask;
+ u32 direction;
+ u32 value;
+};
+
+#define MAX_NB_SUBBANDS 8
+struct dibSubbandSelection {
+ u8 size; /* Actual number of subbands. */
+ struct {
+ u16 f_mhz;
+ struct dibGPIOFunction gpio;
+ } subband[MAX_NB_SUBBANDS];
+};
+
+#define DEMOD_TIMF_SET 0x00
+#define DEMOD_TIMF_GET 0x01
+#define DEMOD_TIMF_UPDATE 0x02
+
#endif
diff --git a/drivers/media/dvb/frontends/drx397xD.c b/drivers/media/dvb/frontends/drx397xD.c
index a05007c8098..536f02b1733 100644
--- a/drivers/media/dvb/frontends/drx397xD.c
+++ b/drivers/media/dvb/frontends/drx397xD.c
@@ -1097,7 +1097,7 @@ static int drx397x_init(struct dvb_frontend *fe)
s->config.ifagc.w0A = 0x3ff;
s->config.ifagc.w0C = 0x388;
- /* for signal strenght calculations */
+ /* for signal strength calculations */
s->config.ss76 = 820;
s->config.ss78 = 2200;
s->config.ss7A = 150;
diff --git a/drivers/media/dvb/frontends/ds3000.c b/drivers/media/dvb/frontends/ds3000.c
index fc61d9230db..90bf573308b 100644
--- a/drivers/media/dvb/frontends/ds3000.c
+++ b/drivers/media/dvb/frontends/ds3000.c
@@ -229,31 +229,11 @@ static u8 ds3000_dvbs2_init_tab[] = {
0xb8, 0x00,
};
-/* DS3000 doesn't need some parameters as input and auto-detects them */
-/* save input from the application of those parameters */
-struct ds3000_tuning {
- u32 frequency;
- u32 symbol_rate;
- fe_spectral_inversion_t inversion;
- enum fe_code_rate fec;
-
- /* input values */
- u8 inversion_val;
- fe_modulation_t delivery;
- u8 rolloff;
-};
-
struct ds3000_state {
struct i2c_adapter *i2c;
const struct ds3000_config *config;
-
struct dvb_frontend frontend;
-
- struct ds3000_tuning dcur;
- struct ds3000_tuning dnxt;
-
u8 skip_fw_load;
-
/* previous uncorrected block counter for DVB-S2 */
u16 prevUCBS2;
};
@@ -305,7 +285,7 @@ static int ds3000_writeFW(struct ds3000_state *state, int reg,
struct i2c_msg msg;
u8 *buf;
- buf = kmalloc(3, GFP_KERNEL);
+ buf = kmalloc(33, GFP_KERNEL);
if (buf == NULL) {
printk(KERN_ERR "Unable to kmalloc\n");
ret = -ENOMEM;
@@ -317,10 +297,10 @@ static int ds3000_writeFW(struct ds3000_state *state, int reg,
msg.addr = state->config->demod_address;
msg.flags = 0;
msg.buf = buf;
- msg.len = 3;
+ msg.len = 33;
- for (i = 0; i < len; i += 2) {
- memcpy(buf + 1, data + i, 2);
+ for (i = 0; i < len; i += 32) {
+ memcpy(buf + 1, data + i, 32);
dprintk("%s: write reg 0x%02x, len = %d\n", __func__, reg, len);
@@ -401,45 +381,6 @@ static int ds3000_tuner_readreg(struct ds3000_state *state, u8 reg)
return b1[0];
}
-static int ds3000_set_inversion(struct ds3000_state *state,
- fe_spectral_inversion_t inversion)
-{
- dprintk("%s(%d)\n", __func__, inversion);
-
- switch (inversion) {
- case INVERSION_OFF:
- case INVERSION_ON:
- case INVERSION_AUTO:
- break;
- default:
- return -EINVAL;
- }
-
- state->dnxt.inversion = inversion;
-
- return 0;
-}
-
-static int ds3000_set_symbolrate(struct ds3000_state *state, u32 rate)
-{
- int ret = 0;
-
- dprintk("%s()\n", __func__);
-
- dprintk("%s() symbol_rate = %d\n", __func__, state->dnxt.symbol_rate);
-
- /* check if symbol rate is within limits */
- if ((state->dnxt.symbol_rate >
- state->frontend.ops.info.symbol_rate_max) ||
- (state->dnxt.symbol_rate <
- state->frontend.ops.info.symbol_rate_min))
- ret = -EOPNOTSUPP;
-
- state->dnxt.symbol_rate = rate;
-
- return ret;
-}
-
static int ds3000_load_firmware(struct dvb_frontend *fe,
const struct firmware *fw);
@@ -509,23 +450,31 @@ static int ds3000_load_firmware(struct dvb_frontend *fe,
return 0;
}
-static void ds3000_dump_registers(struct dvb_frontend *fe)
+static int ds3000_set_voltage(struct dvb_frontend *fe, fe_sec_voltage_t voltage)
{
struct ds3000_state *state = fe->demodulator_priv;
- int x, y, reg = 0, val;
-
- for (y = 0; y < 16; y++) {
- dprintk("%s: %02x: ", __func__, y);
- for (x = 0; x < 16; x++) {
- reg = (y << 4) + x;
- val = ds3000_readreg(state, reg);
- if (x != 15)
- dprintk("%02x ", val);
- else
- dprintk("%02x\n", val);
- }
+ u8 data;
+
+ dprintk("%s(%d)\n", __func__, voltage);
+
+ data = ds3000_readreg(state, 0xa2);
+ data |= 0x03; /* bit0 V/H, bit1 off/on */
+
+ switch (voltage) {
+ case SEC_VOLTAGE_18:
+ data &= ~0x03;
+ break;
+ case SEC_VOLTAGE_13:
+ data &= ~0x03;
+ data |= 0x01;
+ break;
+ case SEC_VOLTAGE_OFF:
+ break;
}
- dprintk("%s: -- DS3000 DUMP DONE --\n", __func__);
+
+ ds3000_writereg(state, 0xa2, data);
+
+ return 0;
}
static int ds3000_read_status(struct dvb_frontend *fe, fe_status_t* status)
@@ -562,16 +511,6 @@ static int ds3000_read_status(struct dvb_frontend *fe, fe_status_t* status)
return 0;
}
-#define FE_IS_TUNED (FE_HAS_SIGNAL + FE_HAS_LOCK)
-static int ds3000_is_tuned(struct dvb_frontend *fe)
-{
- fe_status_t tunerstat;
-
- ds3000_read_status(fe, &tunerstat);
-
- return ((tunerstat & FE_IS_TUNED) == FE_IS_TUNED);
-}
-
/* read DS3000 BER value */
static int ds3000_read_ber(struct dvb_frontend *fe, u32* ber)
{
@@ -792,13 +731,6 @@ static int ds3000_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
return 0;
}
-/* Overwrite the current tuning params, we are about to tune */
-static void ds3000_clone_params(struct dvb_frontend *fe)
-{
- struct ds3000_state *state = fe->demodulator_priv;
- memcpy(&state->dcur, &state->dnxt, sizeof(state->dcur));
-}
-
static int ds3000_set_tone(struct dvb_frontend *fe, fe_sec_tone_mode_t tone)
{
struct ds3000_state *state = fe->demodulator_priv;
@@ -1016,287 +948,298 @@ static int ds3000_get_property(struct dvb_frontend *fe,
return 0;
}
-static int ds3000_tune(struct dvb_frontend *fe,
+static int ds3000_set_carrier_offset(struct dvb_frontend *fe,
+ s32 carrier_offset_khz)
+{
+ struct ds3000_state *state = fe->demodulator_priv;
+ s32 tmp;
+
+ tmp = carrier_offset_khz;
+ tmp *= 65536;
+ tmp = (2 * tmp + DS3000_SAMPLE_RATE) / (2 * DS3000_SAMPLE_RATE);
+
+ if (tmp < 0)
+ tmp += 65536;
+
+ ds3000_writereg(state, 0x5f, tmp >> 8);
+ ds3000_writereg(state, 0x5e, tmp & 0xff);
+
+ return 0;
+}
+
+static int ds3000_set_frontend(struct dvb_frontend *fe,
struct dvb_frontend_parameters *p)
{
struct ds3000_state *state = fe->demodulator_priv;
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
- int ret = 0, retune, i;
- u8 status, mlpf, mlpf_new, mlpf_max, mlpf_min, nlpf;
+ int i;
+ fe_status_t status;
+ u8 mlpf, mlpf_new, mlpf_max, mlpf_min, nlpf, div4;
+ s32 offset_khz;
u16 value, ndiv;
u32 f3db;
dprintk("%s() ", __func__);
- /* Load the firmware if required */
- ret = ds3000_firmware_ondemand(fe);
- if (ret != 0) {
- printk(KERN_ERR "%s: Unable initialise the firmware\n",
- __func__);
- return ret;
+ if (state->config->set_ts_params)
+ state->config->set_ts_params(fe, 0);
+ /* Tune */
+ /* unknown */
+ ds3000_tuner_writereg(state, 0x07, 0x02);
+ ds3000_tuner_writereg(state, 0x10, 0x00);
+ ds3000_tuner_writereg(state, 0x60, 0x79);
+ ds3000_tuner_writereg(state, 0x08, 0x01);
+ ds3000_tuner_writereg(state, 0x00, 0x01);
+ div4 = 0;
+
+ /* calculate and set freq divider */
+ if (p->frequency < 1146000) {
+ ds3000_tuner_writereg(state, 0x10, 0x11);
+ div4 = 1;
+ ndiv = ((p->frequency * (6 + 8) * 4) +
+ (DS3000_XTAL_FREQ / 2)) /
+ DS3000_XTAL_FREQ - 1024;
+ } else {
+ ds3000_tuner_writereg(state, 0x10, 0x01);
+ ndiv = ((p->frequency * (6 + 8) * 2) +
+ (DS3000_XTAL_FREQ / 2)) /
+ DS3000_XTAL_FREQ - 1024;
}
- state->dnxt.delivery = c->modulation;
- state->dnxt.frequency = c->frequency;
- state->dnxt.rolloff = 2; /* fixme */
- state->dnxt.fec = c->fec_inner;
+ ds3000_tuner_writereg(state, 0x01, (ndiv & 0x0f00) >> 8);
+ ds3000_tuner_writereg(state, 0x02, ndiv & 0x00ff);
+
+ /* set pll */
+ ds3000_tuner_writereg(state, 0x03, 0x06);
+ ds3000_tuner_writereg(state, 0x51, 0x0f);
+ ds3000_tuner_writereg(state, 0x51, 0x1f);
+ ds3000_tuner_writereg(state, 0x50, 0x10);
+ ds3000_tuner_writereg(state, 0x50, 0x00);
+ msleep(5);
+
+ /* unknown */
+ ds3000_tuner_writereg(state, 0x51, 0x17);
+ ds3000_tuner_writereg(state, 0x51, 0x1f);
+ ds3000_tuner_writereg(state, 0x50, 0x08);
+ ds3000_tuner_writereg(state, 0x50, 0x00);
+ msleep(5);
+
+ value = ds3000_tuner_readreg(state, 0x3d);
+ value &= 0x0f;
+ if ((value > 4) && (value < 15)) {
+ value -= 3;
+ if (value < 4)
+ value = 4;
+ value = ((value << 3) | 0x01) & 0x79;
+ }
- ret = ds3000_set_inversion(state, p->inversion);
- if (ret != 0)
- return ret;
+ ds3000_tuner_writereg(state, 0x60, value);
+ ds3000_tuner_writereg(state, 0x51, 0x17);
+ ds3000_tuner_writereg(state, 0x51, 0x1f);
+ ds3000_tuner_writereg(state, 0x50, 0x08);
+ ds3000_tuner_writereg(state, 0x50, 0x00);
+
+ /* set low-pass filter period */
+ ds3000_tuner_writereg(state, 0x04, 0x2e);
+ ds3000_tuner_writereg(state, 0x51, 0x1b);
+ ds3000_tuner_writereg(state, 0x51, 0x1f);
+ ds3000_tuner_writereg(state, 0x50, 0x04);
+ ds3000_tuner_writereg(state, 0x50, 0x00);
+ msleep(5);
+
+ f3db = ((c->symbol_rate / 1000) << 2) / 5 + 2000;
+ if ((c->symbol_rate / 1000) < 5000)
+ f3db += 3000;
+ if (f3db < 7000)
+ f3db = 7000;
+ if (f3db > 40000)
+ f3db = 40000;
+
+ /* set low-pass filter baseband */
+ value = ds3000_tuner_readreg(state, 0x26);
+ mlpf = 0x2e * 207 / ((value << 1) + 151);
+ mlpf_max = mlpf * 135 / 100;
+ mlpf_min = mlpf * 78 / 100;
+ if (mlpf_max > 63)
+ mlpf_max = 63;
+
+ /* rounded to the closest integer */
+ nlpf = ((mlpf * f3db * 1000) + (2766 * DS3000_XTAL_FREQ / 2))
+ / (2766 * DS3000_XTAL_FREQ);
+ if (nlpf > 23)
+ nlpf = 23;
+ if (nlpf < 1)
+ nlpf = 1;
+
+ /* rounded to the closest integer */
+ mlpf_new = ((DS3000_XTAL_FREQ * nlpf * 2766) +
+ (1000 * f3db / 2)) / (1000 * f3db);
+
+ if (mlpf_new < mlpf_min) {
+ nlpf++;
+ mlpf_new = ((DS3000_XTAL_FREQ * nlpf * 2766) +
+ (1000 * f3db / 2)) / (1000 * f3db);
+ }
- ret = ds3000_set_symbolrate(state, c->symbol_rate);
- if (ret != 0)
- return ret;
+ if (mlpf_new > mlpf_max)
+ mlpf_new = mlpf_max;
+
+ ds3000_tuner_writereg(state, 0x04, mlpf_new);
+ ds3000_tuner_writereg(state, 0x06, nlpf);
+ ds3000_tuner_writereg(state, 0x51, 0x1b);
+ ds3000_tuner_writereg(state, 0x51, 0x1f);
+ ds3000_tuner_writereg(state, 0x50, 0x04);
+ ds3000_tuner_writereg(state, 0x50, 0x00);
+ msleep(5);
+
+ /* unknown */
+ ds3000_tuner_writereg(state, 0x51, 0x1e);
+ ds3000_tuner_writereg(state, 0x51, 0x1f);
+ ds3000_tuner_writereg(state, 0x50, 0x01);
+ ds3000_tuner_writereg(state, 0x50, 0x00);
+ msleep(60);
+
+ offset_khz = (ndiv - ndiv % 2 + 1024) * DS3000_XTAL_FREQ
+ / (6 + 8) / (div4 + 1) / 2 - p->frequency;
+
+ /* ds3000 global reset */
+ ds3000_writereg(state, 0x07, 0x80);
+ ds3000_writereg(state, 0x07, 0x00);
+ /* ds3000 build-in uC reset */
+ ds3000_writereg(state, 0xb2, 0x01);
+ /* ds3000 software reset */
+ ds3000_writereg(state, 0x00, 0x01);
- /* discard the 'current' tuning parameters and prepare to tune */
- ds3000_clone_params(fe);
-
- retune = 1; /* try 1 times */
- dprintk("%s: retune = %d\n", __func__, retune);
- dprintk("%s: frequency = %d\n", __func__, state->dcur.frequency);
- dprintk("%s: symbol_rate = %d\n", __func__, state->dcur.symbol_rate);
- dprintk("%s: FEC = %d \n", __func__,
- state->dcur.fec);
- dprintk("%s: Inversion = %d\n", __func__, state->dcur.inversion);
-
- do {
- /* Reset status register */
- status = 0;
- /* Tune */
- /* TS2020 init */
- ds3000_tuner_writereg(state, 0x42, 0x73);
- ds3000_tuner_writereg(state, 0x05, 0x01);
- ds3000_tuner_writereg(state, 0x62, 0xf5);
- /* unknown */
- ds3000_tuner_writereg(state, 0x07, 0x02);
- ds3000_tuner_writereg(state, 0x10, 0x00);
- ds3000_tuner_writereg(state, 0x60, 0x79);
- ds3000_tuner_writereg(state, 0x08, 0x01);
- ds3000_tuner_writereg(state, 0x00, 0x01);
- /* calculate and set freq divider */
- if (state->dcur.frequency < 1146000) {
- ds3000_tuner_writereg(state, 0x10, 0x11);
- ndiv = ((state->dcur.frequency * (6 + 8) * 4) +
- (DS3000_XTAL_FREQ / 2)) /
- DS3000_XTAL_FREQ - 1024;
- } else {
- ds3000_tuner_writereg(state, 0x10, 0x01);
- ndiv = ((state->dcur.frequency * (6 + 8) * 2) +
- (DS3000_XTAL_FREQ / 2)) /
- DS3000_XTAL_FREQ - 1024;
- }
+ switch (c->delivery_system) {
+ case SYS_DVBS:
+ /* initialise the demod in DVB-S mode */
+ for (i = 0; i < sizeof(ds3000_dvbs_init_tab); i += 2)
+ ds3000_writereg(state,
+ ds3000_dvbs_init_tab[i],
+ ds3000_dvbs_init_tab[i + 1]);
+ value = ds3000_readreg(state, 0xfe);
+ value &= 0xc0;
+ value |= 0x1b;
+ ds3000_writereg(state, 0xfe, value);
+ break;
+ case SYS_DVBS2:
+ /* initialise the demod in DVB-S2 mode */
+ for (i = 0; i < sizeof(ds3000_dvbs2_init_tab); i += 2)
+ ds3000_writereg(state,
+ ds3000_dvbs2_init_tab[i],
+ ds3000_dvbs2_init_tab[i + 1]);
+ ds3000_writereg(state, 0xfe, 0x98);
+ break;
+ default:
+ return 1;
+ }
- ds3000_tuner_writereg(state, 0x01, (ndiv & 0x0f00) >> 8);
- ds3000_tuner_writereg(state, 0x02, ndiv & 0x00ff);
-
- /* set pll */
- ds3000_tuner_writereg(state, 0x03, 0x06);
- ds3000_tuner_writereg(state, 0x51, 0x0f);
- ds3000_tuner_writereg(state, 0x51, 0x1f);
- ds3000_tuner_writereg(state, 0x50, 0x10);
- ds3000_tuner_writereg(state, 0x50, 0x00);
- msleep(5);
-
- /* unknown */
- ds3000_tuner_writereg(state, 0x51, 0x17);
- ds3000_tuner_writereg(state, 0x51, 0x1f);
- ds3000_tuner_writereg(state, 0x50, 0x08);
- ds3000_tuner_writereg(state, 0x50, 0x00);
- msleep(5);
-
- value = ds3000_tuner_readreg(state, 0x3d);
- value &= 0x0f;
- if ((value > 4) && (value < 15)) {
- value -= 3;
- if (value < 4)
- value = 4;
- value = ((value << 3) | 0x01) & 0x79;
- }
+ /* enable 27MHz clock output */
+ ds3000_writereg(state, 0x29, 0x80);
+ /* enable ac coupling */
+ ds3000_writereg(state, 0x25, 0x8a);
+
+ /* enhance symbol rate performance */
+ if ((c->symbol_rate / 1000) <= 5000) {
+ value = 29777 / (c->symbol_rate / 1000) + 1;
+ if (value % 2 != 0)
+ value++;
+ ds3000_writereg(state, 0xc3, 0x0d);
+ ds3000_writereg(state, 0xc8, value);
+ ds3000_writereg(state, 0xc4, 0x10);
+ ds3000_writereg(state, 0xc7, 0x0e);
+ } else if ((c->symbol_rate / 1000) <= 10000) {
+ value = 92166 / (c->symbol_rate / 1000) + 1;
+ if (value % 2 != 0)
+ value++;
+ ds3000_writereg(state, 0xc3, 0x07);
+ ds3000_writereg(state, 0xc8, value);
+ ds3000_writereg(state, 0xc4, 0x09);
+ ds3000_writereg(state, 0xc7, 0x12);
+ } else if ((c->symbol_rate / 1000) <= 20000) {
+ value = 64516 / (c->symbol_rate / 1000) + 1;
+ ds3000_writereg(state, 0xc3, value);
+ ds3000_writereg(state, 0xc8, 0x0e);
+ ds3000_writereg(state, 0xc4, 0x07);
+ ds3000_writereg(state, 0xc7, 0x18);
+ } else {
+ value = 129032 / (c->symbol_rate / 1000) + 1;
+ ds3000_writereg(state, 0xc3, value);
+ ds3000_writereg(state, 0xc8, 0x0a);
+ ds3000_writereg(state, 0xc4, 0x05);
+ ds3000_writereg(state, 0xc7, 0x24);
+ }
- ds3000_tuner_writereg(state, 0x60, value);
- ds3000_tuner_writereg(state, 0x51, 0x17);
- ds3000_tuner_writereg(state, 0x51, 0x1f);
- ds3000_tuner_writereg(state, 0x50, 0x08);
- ds3000_tuner_writereg(state, 0x50, 0x00);
-
- /* set low-pass filter period */
- ds3000_tuner_writereg(state, 0x04, 0x2e);
- ds3000_tuner_writereg(state, 0x51, 0x1b);
- ds3000_tuner_writereg(state, 0x51, 0x1f);
- ds3000_tuner_writereg(state, 0x50, 0x04);
- ds3000_tuner_writereg(state, 0x50, 0x00);
- msleep(5);
-
- f3db = ((state->dcur.symbol_rate / 1000) << 2) / 5 + 2000;
- if ((state->dcur.symbol_rate / 1000) < 5000)
- f3db += 3000;
- if (f3db < 7000)
- f3db = 7000;
- if (f3db > 40000)
- f3db = 40000;
-
- /* set low-pass filter baseband */
- value = ds3000_tuner_readreg(state, 0x26);
- mlpf = 0x2e * 207 / ((value << 1) + 151);
- mlpf_max = mlpf * 135 / 100;
- mlpf_min = mlpf * 78 / 100;
- if (mlpf_max > 63)
- mlpf_max = 63;
-
- /* rounded to the closest integer */
- nlpf = ((mlpf * f3db * 1000) + (2766 * DS3000_XTAL_FREQ / 2))
- / (2766 * DS3000_XTAL_FREQ);
- if (nlpf > 23)
- nlpf = 23;
- if (nlpf < 1)
- nlpf = 1;
-
- /* rounded to the closest integer */
- mlpf_new = ((DS3000_XTAL_FREQ * nlpf * 2766) +
- (1000 * f3db / 2)) / (1000 * f3db);
+ /* normalized symbol rate rounded to the closest integer */
+ value = (((c->symbol_rate / 1000) << 16) +
+ (DS3000_SAMPLE_RATE / 2)) / DS3000_SAMPLE_RATE;
+ ds3000_writereg(state, 0x61, value & 0x00ff);
+ ds3000_writereg(state, 0x62, (value & 0xff00) >> 8);
- if (mlpf_new < mlpf_min) {
- nlpf++;
- mlpf_new = ((DS3000_XTAL_FREQ * nlpf * 2766) +
- (1000 * f3db / 2)) / (1000 * f3db);
- }
+ /* co-channel interference cancellation disabled */
+ ds3000_writereg(state, 0x56, 0x00);
+
+ /* equalizer disabled */
+ ds3000_writereg(state, 0x76, 0x00);
- if (mlpf_new > mlpf_max)
- mlpf_new = mlpf_max;
-
- ds3000_tuner_writereg(state, 0x04, mlpf_new);
- ds3000_tuner_writereg(state, 0x06, nlpf);
- ds3000_tuner_writereg(state, 0x51, 0x1b);
- ds3000_tuner_writereg(state, 0x51, 0x1f);
- ds3000_tuner_writereg(state, 0x50, 0x04);
- ds3000_tuner_writereg(state, 0x50, 0x00);
- msleep(5);
-
- /* unknown */
- ds3000_tuner_writereg(state, 0x51, 0x1e);
- ds3000_tuner_writereg(state, 0x51, 0x1f);
- ds3000_tuner_writereg(state, 0x50, 0x01);
- ds3000_tuner_writereg(state, 0x50, 0x00);
- msleep(60);
-
- /* ds3000 global reset */
- ds3000_writereg(state, 0x07, 0x80);
- ds3000_writereg(state, 0x07, 0x00);
- /* ds3000 build-in uC reset */
- ds3000_writereg(state, 0xb2, 0x01);
- /* ds3000 software reset */
- ds3000_writereg(state, 0x00, 0x01);
+ /*ds3000_writereg(state, 0x08, 0x03);
+ ds3000_writereg(state, 0xfd, 0x22);
+ ds3000_writereg(state, 0x08, 0x07);
+ ds3000_writereg(state, 0xfd, 0x42);
+ ds3000_writereg(state, 0x08, 0x07);*/
+ if (state->config->ci_mode) {
switch (c->delivery_system) {
case SYS_DVBS:
- /* initialise the demod in DVB-S mode */
- for (i = 0; i < sizeof(ds3000_dvbs_init_tab); i += 2)
- ds3000_writereg(state,
- ds3000_dvbs_init_tab[i],
- ds3000_dvbs_init_tab[i + 1]);
- value = ds3000_readreg(state, 0xfe);
- value &= 0xc0;
- value |= 0x1b;
- ds3000_writereg(state, 0xfe, value);
- break;
+ default:
+ ds3000_writereg(state, 0xfd, 0x80);
+ break;
case SYS_DVBS2:
- /* initialise the demod in DVB-S2 mode */
- for (i = 0; i < sizeof(ds3000_dvbs2_init_tab); i += 2)
- ds3000_writereg(state,
- ds3000_dvbs2_init_tab[i],
- ds3000_dvbs2_init_tab[i + 1]);
- ds3000_writereg(state, 0xfe, 0x54);
+ ds3000_writereg(state, 0xfd, 0x01);
break;
- default:
- return 1;
}
+ }
- /* enable 27MHz clock output */
- ds3000_writereg(state, 0x29, 0x80);
- /* enable ac coupling */
- ds3000_writereg(state, 0x25, 0x8a);
-
- /* enhance symbol rate performance */
- if ((state->dcur.symbol_rate / 1000) <= 5000) {
- value = 29777 / (state->dcur.symbol_rate / 1000) + 1;
- if (value % 2 != 0)
- value++;
- ds3000_writereg(state, 0xc3, 0x0d);
- ds3000_writereg(state, 0xc8, value);
- ds3000_writereg(state, 0xc4, 0x10);
- ds3000_writereg(state, 0xc7, 0x0e);
- } else if ((state->dcur.symbol_rate / 1000) <= 10000) {
- value = 92166 / (state->dcur.symbol_rate / 1000) + 1;
- if (value % 2 != 0)
- value++;
- ds3000_writereg(state, 0xc3, 0x07);
- ds3000_writereg(state, 0xc8, value);
- ds3000_writereg(state, 0xc4, 0x09);
- ds3000_writereg(state, 0xc7, 0x12);
- } else if ((state->dcur.symbol_rate / 1000) <= 20000) {
- value = 64516 / (state->dcur.symbol_rate / 1000) + 1;
- ds3000_writereg(state, 0xc3, value);
- ds3000_writereg(state, 0xc8, 0x0e);
- ds3000_writereg(state, 0xc4, 0x07);
- ds3000_writereg(state, 0xc7, 0x18);
- } else {
- value = 129032 / (state->dcur.symbol_rate / 1000) + 1;
- ds3000_writereg(state, 0xc3, value);
- ds3000_writereg(state, 0xc8, 0x0a);
- ds3000_writereg(state, 0xc4, 0x05);
- ds3000_writereg(state, 0xc7, 0x24);
- }
+ /* ds3000 out of software reset */
+ ds3000_writereg(state, 0x00, 0x00);
+ /* start ds3000 build-in uC */
+ ds3000_writereg(state, 0xb2, 0x00);
- /* normalized symbol rate rounded to the closest integer */
- value = (((state->dcur.symbol_rate / 1000) << 16) +
- (DS3000_SAMPLE_RATE / 2)) / DS3000_SAMPLE_RATE;
- ds3000_writereg(state, 0x61, value & 0x00ff);
- ds3000_writereg(state, 0x62, (value & 0xff00) >> 8);
-
- /* co-channel interference cancellation disabled */
- ds3000_writereg(state, 0x56, 0x00);
-
- /* equalizer disabled */
- ds3000_writereg(state, 0x76, 0x00);
-
- /*ds3000_writereg(state, 0x08, 0x03);
- ds3000_writereg(state, 0xfd, 0x22);
- ds3000_writereg(state, 0x08, 0x07);
- ds3000_writereg(state, 0xfd, 0x42);
- ds3000_writereg(state, 0x08, 0x07);*/
-
- /* ds3000 out of software reset */
- ds3000_writereg(state, 0x00, 0x00);
- /* start ds3000 build-in uC */
- ds3000_writereg(state, 0xb2, 0x00);
-
- /* TODO: calculate and set carrier offset */
-
- /* wait before retrying */
- for (i = 0; i < 30 ; i++) {
- if (ds3000_is_tuned(fe)) {
- dprintk("%s: Tuned\n", __func__);
- ds3000_dump_registers(fe);
- goto tuned;
- }
- msleep(1);
- }
+ ds3000_set_carrier_offset(fe, offset_khz);
- dprintk("%s: Not tuned\n", __func__);
- ds3000_dump_registers(fe);
+ for (i = 0; i < 30 ; i++) {
+ ds3000_read_status(fe, &status);
+ if (status && FE_HAS_LOCK)
+ break;
- } while (--retune);
+ msleep(10);
+ }
-tuned:
- return ret;
+ return 0;
+}
+
+static int ds3000_tune(struct dvb_frontend *fe,
+ struct dvb_frontend_parameters *p,
+ unsigned int mode_flags,
+ unsigned int *delay,
+ fe_status_t *status)
+{
+ if (p) {
+ int ret = ds3000_set_frontend(fe, p);
+ if (ret)
+ return ret;
+ }
+
+ *delay = HZ / 5;
+
+ return ds3000_read_status(fe, status);
}
static enum dvbfe_algo ds3000_get_algo(struct dvb_frontend *fe)
{
dprintk("%s()\n", __func__);
- return DVBFE_ALGO_SW;
+ return DVBFE_ALGO_HW;
}
/*
@@ -1306,7 +1249,25 @@ static enum dvbfe_algo ds3000_get_algo(struct dvb_frontend *fe)
*/
static int ds3000_initfe(struct dvb_frontend *fe)
{
+ struct ds3000_state *state = fe->demodulator_priv;
+ int ret;
+
dprintk("%s()\n", __func__);
+ /* hard reset */
+ ds3000_writereg(state, 0x08, 0x01 | ds3000_readreg(state, 0x08));
+ msleep(1);
+
+ /* TS2020 init */
+ ds3000_tuner_writereg(state, 0x42, 0x73);
+ ds3000_tuner_writereg(state, 0x05, 0x01);
+ ds3000_tuner_writereg(state, 0x62, 0xf5);
+ /* Load the firmware if required */
+ ret = ds3000_firmware_ondemand(fe);
+ if (ret != 0) {
+ printk(KERN_ERR "%s: Unable initialize firmware\n", __func__);
+ return ret;
+ }
+
return 0;
}
@@ -1345,6 +1306,7 @@ static struct dvb_frontend_ops ds3000_ops = {
.read_signal_strength = ds3000_read_signal_strength,
.read_snr = ds3000_read_snr,
.read_ucblocks = ds3000_read_ucblocks,
+ .set_voltage = ds3000_set_voltage,
.set_tone = ds3000_set_tone,
.diseqc_send_master_cmd = ds3000_send_diseqc_msg,
.diseqc_send_burst = ds3000_diseqc_send_burst,
@@ -1352,7 +1314,8 @@ static struct dvb_frontend_ops ds3000_ops = {
.set_property = ds3000_set_property,
.get_property = ds3000_get_property,
- .set_frontend = ds3000_tune,
+ .set_frontend = ds3000_set_frontend,
+ .tune = ds3000_tune,
};
module_param(debug, int, 0644);
diff --git a/drivers/media/dvb/frontends/ds3000.h b/drivers/media/dvb/frontends/ds3000.h
index 67f67038740..1b736888ea3 100644
--- a/drivers/media/dvb/frontends/ds3000.h
+++ b/drivers/media/dvb/frontends/ds3000.h
@@ -27,6 +27,9 @@
struct ds3000_config {
/* the demodulator's i2c address */
u8 demod_address;
+ u8 ci_mode;
+ /* Set device param to start dma */
+ int (*set_ts_params)(struct dvb_frontend *fe, int is_punctured);
};
#if defined(CONFIG_DVB_DS3000) || \
diff --git a/drivers/media/dvb/frontends/dvb-pll.c b/drivers/media/dvb/frontends/dvb-pll.c
index 4d4d0bb5920..62a65efdf8d 100644
--- a/drivers/media/dvb/frontends/dvb-pll.c
+++ b/drivers/media/dvb/frontends/dvb-pll.c
@@ -64,6 +64,7 @@ struct dvb_pll_desc {
void (*set)(struct dvb_frontend *fe, u8 *buf,
const struct dvb_frontend_parameters *params);
u8 *initdata;
+ u8 *initdata2;
u8 *sleepdata;
int count;
struct {
@@ -321,26 +322,73 @@ static struct dvb_pll_desc dvb_pll_philips_sd1878_tda8261 = {
static void opera1_bw(struct dvb_frontend *fe, u8 *buf,
const struct dvb_frontend_parameters *params)
{
- if (params->u.ofdm.bandwidth == BANDWIDTH_8_MHZ)
- buf[2] |= 0x08;
+ struct dvb_pll_priv *priv = fe->tuner_priv;
+ u32 b_w = (params->u.qpsk.symbol_rate * 27) / 32000;
+ struct i2c_msg msg = {
+ .addr = priv->pll_i2c_address,
+ .flags = 0,
+ .buf = buf,
+ .len = 4
+ };
+ int result;
+ u8 lpf;
+
+ if (fe->ops.i2c_gate_ctrl)
+ fe->ops.i2c_gate_ctrl(fe, 1);
+
+ result = i2c_transfer(priv->i2c, &msg, 1);
+ if (result != 1)
+ printk(KERN_ERR "%s: i2c_transfer failed:%d",
+ __func__, result);
+
+ if (b_w <= 10000)
+ lpf = 0xc;
+ else if (b_w <= 12000)
+ lpf = 0x2;
+ else if (b_w <= 14000)
+ lpf = 0xa;
+ else if (b_w <= 16000)
+ lpf = 0x6;
+ else if (b_w <= 18000)
+ lpf = 0xe;
+ else if (b_w <= 20000)
+ lpf = 0x1;
+ else if (b_w <= 22000)
+ lpf = 0x9;
+ else if (b_w <= 24000)
+ lpf = 0x5;
+ else if (b_w <= 26000)
+ lpf = 0xd;
+ else if (b_w <= 28000)
+ lpf = 0x3;
+ else
+ lpf = 0xb;
+ buf[2] ^= 0x1c; /* Flip bits 3-5 */
+ /* Set lpf */
+ buf[2] |= ((lpf >> 2) & 0x3) << 3;
+ buf[3] |= (lpf & 0x3) << 2;
+
+ return;
}
static struct dvb_pll_desc dvb_pll_opera1 = {
.name = "Opera Tuner",
.min = 900000,
.max = 2250000,
+ .initdata = (u8[]){ 4, 0x08, 0xe5, 0xe1, 0x00 },
+ .initdata2 = (u8[]){ 4, 0x08, 0xe5, 0xe5, 0x00 },
.iffreq= 0,
.set = opera1_bw,
.count = 8,
.entries = {
- { 1064000, 500, 0xe5, 0xc6 },
- { 1169000, 500, 0xe5, 0xe6 },
- { 1299000, 500, 0xe5, 0x24 },
- { 1444000, 500, 0xe5, 0x44 },
- { 1606000, 500, 0xe5, 0x64 },
- { 1777000, 500, 0xe5, 0x84 },
- { 1941000, 500, 0xe5, 0xa4 },
- { 2250000, 500, 0xe5, 0xc4 },
+ { 1064000, 500, 0xf9, 0xc2 },
+ { 1169000, 500, 0xf9, 0xe2 },
+ { 1299000, 500, 0xf9, 0x20 },
+ { 1444000, 500, 0xf9, 0x40 },
+ { 1606000, 500, 0xf9, 0x60 },
+ { 1777000, 500, 0xf9, 0x80 },
+ { 1941000, 500, 0xf9, 0xa0 },
+ { 2250000, 500, 0xf9, 0xc0 },
}
};
@@ -648,8 +696,17 @@ static int dvb_pll_init(struct dvb_frontend *fe)
int result;
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 1);
- if ((result = i2c_transfer(priv->i2c, &msg, 1)) != 1) {
+ result = i2c_transfer(priv->i2c, &msg, 1);
+ if (result != 1)
return result;
+ if (priv->pll_desc->initdata2) {
+ msg.buf = priv->pll_desc->initdata2 + 1;
+ msg.len = priv->pll_desc->initdata2[0];
+ if (fe->ops.i2c_gate_ctrl)
+ fe->ops.i2c_gate_ctrl(fe, 1);
+ result = i2c_transfer(priv->i2c, &msg, 1);
+ if (result != 1)
+ return result;
}
return 0;
}
diff --git a/drivers/media/dvb/frontends/mb86a16.c b/drivers/media/dvb/frontends/mb86a16.c
index 33b63235b86..c283112051b 100644
--- a/drivers/media/dvb/frontends/mb86a16.c
+++ b/drivers/media/dvb/frontends/mb86a16.c
@@ -1630,7 +1630,7 @@ static enum dvbfe_search mb86a16_search(struct dvb_frontend *fe,
state->srate = p->u.qpsk.symbol_rate / 1000;
if (!mb86a16_set_fe(state)) {
- dprintk(verbose, MB86A16_ERROR, 1, "Succesfully acquired LOCK");
+ dprintk(verbose, MB86A16_ERROR, 1, "Successfully acquired LOCK");
return DVBFE_ALGO_SEARCH_SUCCESS;
}
diff --git a/drivers/media/dvb/frontends/mb86a20s.c b/drivers/media/dvb/frontends/mb86a20s.c
index cc4acd2f920..0f867a5055f 100644
--- a/drivers/media/dvb/frontends/mb86a20s.c
+++ b/drivers/media/dvb/frontends/mb86a20s.c
@@ -406,7 +406,7 @@ err:
printk(KERN_INFO "mb86a20s: Init failed. Will try again later\n");
} else {
state->need_init = false;
- dprintk("Initialization succeded.\n");
+ dprintk("Initialization succeeded.\n");
}
return rc;
}
diff --git a/drivers/media/dvb/frontends/mt312.c b/drivers/media/dvb/frontends/mt312.c
index 472907d4346..83e6f1a1b70 100644
--- a/drivers/media/dvb/frontends/mt312.c
+++ b/drivers/media/dvb/frontends/mt312.c
@@ -670,7 +670,7 @@ static int mt312_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
if (ret < 0)
goto error;
- /* preserve this bit to not accidently shutdown ADC */
+ /* preserve this bit to not accidentally shutdown ADC */
val &= 0x80;
break;
}
diff --git a/drivers/media/dvb/frontends/s5h1420.c b/drivers/media/dvb/frontends/s5h1420.c
index e87b747ea99..17f8cdf8afe 100644
--- a/drivers/media/dvb/frontends/s5h1420.c
+++ b/drivers/media/dvb/frontends/s5h1420.c
@@ -225,7 +225,7 @@ static int s5h1420_recv_slave_reply (struct dvb_frontend* fe,
unsigned long timeout;
int result = 0;
- /* setup for DISEQC recieve */
+ /* setup for DISEQC receive */
val = s5h1420_readreg(state, 0x3b);
s5h1420_writereg(state, 0x3b, 0x82); /* FIXME: guess - do we need to set DIS_RDY(0x08) in receive mode? */
msleep(15);
diff --git a/drivers/media/dvb/frontends/stb6100.c b/drivers/media/dvb/frontends/stb6100.c
index 64673b8b64a..bc1a8af4f6e 100644
--- a/drivers/media/dvb/frontends/stb6100.c
+++ b/drivers/media/dvb/frontends/stb6100.c
@@ -360,7 +360,7 @@ static int stb6100_set_frequency(struct dvb_frontend *fe, u32 frequency)
else
odiv = 0;
- /* VCO enabled, seach clock off as per LL3.7, 3.4.1 */
+ /* VCO enabled, search clock off as per LL3.7, 3.4.1 */
regs[STB6100_VCO] = 0xe0 | (odiv << STB6100_VCO_ODIV_SHIFT);
/* OSM */
diff --git a/drivers/media/dvb/frontends/stv0288.c b/drivers/media/dvb/frontends/stv0288.c
index 63db8fd2754..e3fe17fd96f 100644
--- a/drivers/media/dvb/frontends/stv0288.c
+++ b/drivers/media/dvb/frontends/stv0288.c
@@ -367,8 +367,11 @@ static int stv0288_read_status(struct dvb_frontend *fe, fe_status_t *status)
dprintk("%s : FE_READ_STATUS : VSTATUS: 0x%02x\n", __func__, sync);
*status = 0;
-
- if ((sync & 0x08) == 0x08) {
+ if (sync & 0x80)
+ *status |= FE_HAS_CARRIER | FE_HAS_SIGNAL;
+ if (sync & 0x10)
+ *status |= FE_HAS_VITERBI;
+ if (sync & 0x08) {
*status |= FE_HAS_LOCK;
dprintk("stv0288 has locked\n");
}
diff --git a/drivers/media/dvb/frontends/stv0297.c b/drivers/media/dvb/frontends/stv0297.c
index 4fd7479bb62..84d88f33275 100644
--- a/drivers/media/dvb/frontends/stv0297.c
+++ b/drivers/media/dvb/frontends/stv0297.c
@@ -435,7 +435,7 @@ static int stv0297_set_frontend(struct dvb_frontend *fe, struct dvb_frontend_par
return -EINVAL;
}
- // determine inversion dependant parameters
+ // determine inversion dependent parameters
inversion = p->inversion;
if (state->config->invert)
inversion = (inversion == INVERSION_ON) ? INVERSION_OFF : INVERSION_ON;
diff --git a/drivers/media/dvb/frontends/stv0367.c b/drivers/media/dvb/frontends/stv0367.c
new file mode 100644
index 00000000000..e57ab53e2e2
--- /dev/null
+++ b/drivers/media/dvb/frontends/stv0367.c
@@ -0,0 +1,3459 @@
+/*
+ * stv0367.c
+ *
+ * Driver for ST STV0367 DVB-T & DVB-C demodulator IC.
+ *
+ * Copyright (C) ST Microelectronics.
+ * Copyright (C) 2010,2011 NetUP Inc.
+ * Copyright (C) 2010,2011 Igor M. Liplianin <liplianin@netup.ru>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ *
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/string.h>
+#include <linux/slab.h>
+#include <linux/i2c.h>
+
+#include "stv0367.h"
+#include "stv0367_regs.h"
+#include "stv0367_priv.h"
+
+static int stvdebug;
+module_param_named(debug, stvdebug, int, 0644);
+
+static int i2cdebug;
+module_param_named(i2c_debug, i2cdebug, int, 0644);
+
+#define dprintk(args...) \
+ do { \
+ if (stvdebug) \
+ printk(KERN_DEBUG args); \
+ } while (0)
+ /* DVB-C */
+
+struct stv0367cab_state {
+ enum stv0367_cab_signal_type state;
+ u32 mclk;
+ u32 adc_clk;
+ s32 search_range;
+ s32 derot_offset;
+ /* results */
+ int locked; /* channel found */
+ u32 freq_khz; /* found frequency (in kHz) */
+ u32 symbol_rate; /* found symbol rate (in Bds) */
+ enum stv0367cab_mod modulation; /* modulation */
+ fe_spectral_inversion_t spect_inv; /* Spectrum Inversion */
+};
+
+struct stv0367ter_state {
+ /* DVB-T */
+ enum stv0367_ter_signal_type state;
+ enum stv0367_ter_if_iq_mode if_iq_mode;
+ enum stv0367_ter_mode mode;/* mode 2K or 8K */
+ fe_guard_interval_t guard;
+ enum stv0367_ter_hierarchy hierarchy;
+ u32 frequency;
+ fe_spectral_inversion_t sense; /* current search spectrum */
+ u8 force; /* force mode/guard */
+ u8 bw; /* channel width 6, 7 or 8 in MHz */
+ u8 pBW; /* channel width used during previous lock */
+ u32 pBER;
+ u32 pPER;
+ u32 ucblocks;
+ s8 echo_pos; /* echo position */
+ u8 first_lock;
+ u8 unlock_counter;
+ u32 agc_val;
+};
+
+struct stv0367_state {
+ struct dvb_frontend fe;
+ struct i2c_adapter *i2c;
+ /* config settings */
+ const struct stv0367_config *config;
+ u8 chip_id;
+ /* DVB-C */
+ struct stv0367cab_state *cab_state;
+ /* DVB-T */
+ struct stv0367ter_state *ter_state;
+};
+
+struct st_register {
+ u16 addr;
+ u8 value;
+};
+
+/* values for STV4100 XTAL=30M int clk=53.125M*/
+static struct st_register def0367ter[STV0367TER_NBREGS] = {
+ {R367TER_ID, 0x60},
+ {R367TER_I2CRPT, 0xa0},
+ /* {R367TER_I2CRPT, 0x22},*/
+ {R367TER_TOPCTRL, 0x00},/* for xc5000; was 0x02 */
+ {R367TER_IOCFG0, 0x40},
+ {R367TER_DAC0R, 0x00},
+ {R367TER_IOCFG1, 0x00},
+ {R367TER_DAC1R, 0x00},
+ {R367TER_IOCFG2, 0x62},
+ {R367TER_SDFR, 0x00},
+ {R367TER_STATUS, 0xf8},
+ {R367TER_AUX_CLK, 0x0a},
+ {R367TER_FREESYS1, 0x00},
+ {R367TER_FREESYS2, 0x00},
+ {R367TER_FREESYS3, 0x00},
+ {R367TER_GPIO_CFG, 0x55},
+ {R367TER_GPIO_CMD, 0x00},
+ {R367TER_AGC2MAX, 0xff},
+ {R367TER_AGC2MIN, 0x00},
+ {R367TER_AGC1MAX, 0xff},
+ {R367TER_AGC1MIN, 0x00},
+ {R367TER_AGCR, 0xbc},
+ {R367TER_AGC2TH, 0x00},
+ {R367TER_AGC12C, 0x00},
+ {R367TER_AGCCTRL1, 0x85},
+ {R367TER_AGCCTRL2, 0x1f},
+ {R367TER_AGC1VAL1, 0x00},
+ {R367TER_AGC1VAL2, 0x00},
+ {R367TER_AGC2VAL1, 0x6f},
+ {R367TER_AGC2VAL2, 0x05},
+ {R367TER_AGC2PGA, 0x00},
+ {R367TER_OVF_RATE1, 0x00},
+ {R367TER_OVF_RATE2, 0x00},
+ {R367TER_GAIN_SRC1, 0xaa},/* for xc5000; was 0x2b */
+ {R367TER_GAIN_SRC2, 0xd6},/* for xc5000; was 0x04 */
+ {R367TER_INC_DEROT1, 0x55},
+ {R367TER_INC_DEROT2, 0x55},
+ {R367TER_PPM_CPAMP_DIR, 0x2c},
+ {R367TER_PPM_CPAMP_INV, 0x00},
+ {R367TER_FREESTFE_1, 0x00},
+ {R367TER_FREESTFE_2, 0x1c},
+ {R367TER_DCOFFSET, 0x00},
+ {R367TER_EN_PROCESS, 0x05},
+ {R367TER_SDI_SMOOTHER, 0x80},
+ {R367TER_FE_LOOP_OPEN, 0x1c},
+ {R367TER_FREQOFF1, 0x00},
+ {R367TER_FREQOFF2, 0x00},
+ {R367TER_FREQOFF3, 0x00},
+ {R367TER_TIMOFF1, 0x00},
+ {R367TER_TIMOFF2, 0x00},
+ {R367TER_EPQ, 0x02},
+ {R367TER_EPQAUTO, 0x01},
+ {R367TER_SYR_UPDATE, 0xf5},
+ {R367TER_CHPFREE, 0x00},
+ {R367TER_PPM_STATE_MAC, 0x23},
+ {R367TER_INR_THRESHOLD, 0xff},
+ {R367TER_EPQ_TPS_ID_CELL, 0xf9},
+ {R367TER_EPQ_CFG, 0x00},
+ {R367TER_EPQ_STATUS, 0x01},
+ {R367TER_AUTORELOCK, 0x81},
+ {R367TER_BER_THR_VMSB, 0x00},
+ {R367TER_BER_THR_MSB, 0x00},
+ {R367TER_BER_THR_LSB, 0x00},
+ {R367TER_CCD, 0x83},
+ {R367TER_SPECTR_CFG, 0x00},
+ {R367TER_CHC_DUMMY, 0x18},
+ {R367TER_INC_CTL, 0x88},
+ {R367TER_INCTHRES_COR1, 0xb4},
+ {R367TER_INCTHRES_COR2, 0x96},
+ {R367TER_INCTHRES_DET1, 0x0e},
+ {R367TER_INCTHRES_DET2, 0x11},
+ {R367TER_IIR_CELLNB, 0x8d},
+ {R367TER_IIRCX_COEFF1_MSB, 0x00},
+ {R367TER_IIRCX_COEFF1_LSB, 0x00},
+ {R367TER_IIRCX_COEFF2_MSB, 0x09},
+ {R367TER_IIRCX_COEFF2_LSB, 0x18},
+ {R367TER_IIRCX_COEFF3_MSB, 0x14},
+ {R367TER_IIRCX_COEFF3_LSB, 0x9c},
+ {R367TER_IIRCX_COEFF4_MSB, 0x00},
+ {R367TER_IIRCX_COEFF4_LSB, 0x00},
+ {R367TER_IIRCX_COEFF5_MSB, 0x36},
+ {R367TER_IIRCX_COEFF5_LSB, 0x42},
+ {R367TER_FEPATH_CFG, 0x00},
+ {R367TER_PMC1_FUNC, 0x65},
+ {R367TER_PMC1_FOR, 0x00},
+ {R367TER_PMC2_FUNC, 0x00},
+ {R367TER_STATUS_ERR_DA, 0xe0},
+ {R367TER_DIG_AGC_R, 0xfe},
+ {R367TER_COMAGC_TARMSB, 0x0b},
+ {R367TER_COM_AGC_TAR_ENMODE, 0x41},
+ {R367TER_COM_AGC_CFG, 0x3e},
+ {R367TER_COM_AGC_GAIN1, 0x39},
+ {R367TER_AUT_AGC_TARGETMSB, 0x0b},
+ {R367TER_LOCK_DET_MSB, 0x01},
+ {R367TER_AGCTAR_LOCK_LSBS, 0x40},
+ {R367TER_AUT_GAIN_EN, 0xf4},
+ {R367TER_AUT_CFG, 0xf0},
+ {R367TER_LOCKN, 0x23},
+ {R367TER_INT_X_3, 0x00},
+ {R367TER_INT_X_2, 0x03},
+ {R367TER_INT_X_1, 0x8d},
+ {R367TER_INT_X_0, 0xa0},
+ {R367TER_MIN_ERRX_MSB, 0x00},
+ {R367TER_COR_CTL, 0x23},
+ {R367TER_COR_STAT, 0xf6},
+ {R367TER_COR_INTEN, 0x00},
+ {R367TER_COR_INTSTAT, 0x3f},
+ {R367TER_COR_MODEGUARD, 0x03},
+ {R367TER_AGC_CTL, 0x08},
+ {R367TER_AGC_MANUAL1, 0x00},
+ {R367TER_AGC_MANUAL2, 0x00},
+ {R367TER_AGC_TARG, 0x16},
+ {R367TER_AGC_GAIN1, 0x53},
+ {R367TER_AGC_GAIN2, 0x1d},
+ {R367TER_RESERVED_1, 0x00},
+ {R367TER_RESERVED_2, 0x00},
+ {R367TER_RESERVED_3, 0x00},
+ {R367TER_CAS_CTL, 0x44},
+ {R367TER_CAS_FREQ, 0xb3},
+ {R367TER_CAS_DAGCGAIN, 0x12},
+ {R367TER_SYR_CTL, 0x04},
+ {R367TER_SYR_STAT, 0x10},
+ {R367TER_SYR_NCO1, 0x00},
+ {R367TER_SYR_NCO2, 0x00},
+ {R367TER_SYR_OFFSET1, 0x00},
+ {R367TER_SYR_OFFSET2, 0x00},
+ {R367TER_FFT_CTL, 0x00},
+ {R367TER_SCR_CTL, 0x70},
+ {R367TER_PPM_CTL1, 0xf8},
+ {R367TER_TRL_CTL, 0x14},/* for xc5000; was 0xac */
+ {R367TER_TRL_NOMRATE1, 0xae},/* for xc5000; was 0x1e */
+ {R367TER_TRL_NOMRATE2, 0x56},/* for xc5000; was 0x58 */
+ {R367TER_TRL_TIME1, 0x1d},
+ {R367TER_TRL_TIME2, 0xfc},
+ {R367TER_CRL_CTL, 0x24},
+ {R367TER_CRL_FREQ1, 0xad},
+ {R367TER_CRL_FREQ2, 0x9d},
+ {R367TER_CRL_FREQ3, 0xff},
+ {R367TER_CHC_CTL, 0x01},
+ {R367TER_CHC_SNR, 0xf0},
+ {R367TER_BDI_CTL, 0x00},
+ {R367TER_DMP_CTL, 0x00},
+ {R367TER_TPS_RCVD1, 0x30},
+ {R367TER_TPS_RCVD2, 0x02},
+ {R367TER_TPS_RCVD3, 0x01},
+ {R367TER_TPS_RCVD4, 0x00},
+ {R367TER_TPS_ID_CELL1, 0x00},
+ {R367TER_TPS_ID_CELL2, 0x00},
+ {R367TER_TPS_RCVD5_SET1, 0x02},
+ {R367TER_TPS_SET2, 0x02},
+ {R367TER_TPS_SET3, 0x01},
+ {R367TER_TPS_CTL, 0x00},
+ {R367TER_CTL_FFTOSNUM, 0x34},
+ {R367TER_TESTSELECT, 0x09},
+ {R367TER_MSC_REV, 0x0a},
+ {R367TER_PIR_CTL, 0x00},
+ {R367TER_SNR_CARRIER1, 0xa1},
+ {R367TER_SNR_CARRIER2, 0x9a},
+ {R367TER_PPM_CPAMP, 0x2c},
+ {R367TER_TSM_AP0, 0x00},
+ {R367TER_TSM_AP1, 0x00},
+ {R367TER_TSM_AP2 , 0x00},
+ {R367TER_TSM_AP3, 0x00},
+ {R367TER_TSM_AP4, 0x00},
+ {R367TER_TSM_AP5, 0x00},
+ {R367TER_TSM_AP6, 0x00},
+ {R367TER_TSM_AP7, 0x00},
+ {R367TER_TSTRES, 0x00},
+ {R367TER_ANACTRL, 0x0D},/* PLL stoped, restart at init!!! */
+ {R367TER_TSTBUS, 0x00},
+ {R367TER_TSTRATE, 0x00},
+ {R367TER_CONSTMODE, 0x01},
+ {R367TER_CONSTCARR1, 0x00},
+ {R367TER_CONSTCARR2, 0x00},
+ {R367TER_ICONSTEL, 0x0a},
+ {R367TER_QCONSTEL, 0x15},
+ {R367TER_TSTBISTRES0, 0x00},
+ {R367TER_TSTBISTRES1, 0x00},
+ {R367TER_TSTBISTRES2, 0x28},
+ {R367TER_TSTBISTRES3, 0x00},
+ {R367TER_RF_AGC1, 0xff},
+ {R367TER_RF_AGC2, 0x83},
+ {R367TER_ANADIGCTRL, 0x19},
+ {R367TER_PLLMDIV, 0x01},/* for xc5000; was 0x0c */
+ {R367TER_PLLNDIV, 0x06},/* for xc5000; was 0x55 */
+ {R367TER_PLLSETUP, 0x18},
+ {R367TER_DUAL_AD12, 0x0C},/* for xc5000 AGC voltage 1.6V */
+ {R367TER_TSTBIST, 0x00},
+ {R367TER_PAD_COMP_CTRL, 0x00},
+ {R367TER_PAD_COMP_WR, 0x00},
+ {R367TER_PAD_COMP_RD, 0xe0},
+ {R367TER_SYR_TARGET_FFTADJT_MSB, 0x00},
+ {R367TER_SYR_TARGET_FFTADJT_LSB, 0x00},
+ {R367TER_SYR_TARGET_CHCADJT_MSB, 0x00},
+ {R367TER_SYR_TARGET_CHCADJT_LSB, 0x00},
+ {R367TER_SYR_FLAG, 0x00},
+ {R367TER_CRL_TARGET1, 0x00},
+ {R367TER_CRL_TARGET2, 0x00},
+ {R367TER_CRL_TARGET3, 0x00},
+ {R367TER_CRL_TARGET4, 0x00},
+ {R367TER_CRL_FLAG, 0x00},
+ {R367TER_TRL_TARGET1, 0x00},
+ {R367TER_TRL_TARGET2, 0x00},
+ {R367TER_TRL_CHC, 0x00},
+ {R367TER_CHC_SNR_TARG, 0x00},
+ {R367TER_TOP_TRACK, 0x00},
+ {R367TER_TRACKER_FREE1, 0x00},
+ {R367TER_ERROR_CRL1, 0x00},
+ {R367TER_ERROR_CRL2, 0x00},
+ {R367TER_ERROR_CRL3, 0x00},
+ {R367TER_ERROR_CRL4, 0x00},
+ {R367TER_DEC_NCO1, 0x2c},
+ {R367TER_DEC_NCO2, 0x0f},
+ {R367TER_DEC_NCO3, 0x20},
+ {R367TER_SNR, 0xf1},
+ {R367TER_SYR_FFTADJ1, 0x00},
+ {R367TER_SYR_FFTADJ2, 0x00},
+ {R367TER_SYR_CHCADJ1, 0x00},
+ {R367TER_SYR_CHCADJ2, 0x00},
+ {R367TER_SYR_OFF, 0x00},
+ {R367TER_PPM_OFFSET1, 0x00},
+ {R367TER_PPM_OFFSET2, 0x03},
+ {R367TER_TRACKER_FREE2, 0x00},
+ {R367TER_DEBG_LT10, 0x00},
+ {R367TER_DEBG_LT11, 0x00},
+ {R367TER_DEBG_LT12, 0x00},
+ {R367TER_DEBG_LT13, 0x00},
+ {R367TER_DEBG_LT14, 0x00},
+ {R367TER_DEBG_LT15, 0x00},
+ {R367TER_DEBG_LT16, 0x00},
+ {R367TER_DEBG_LT17, 0x00},
+ {R367TER_DEBG_LT18, 0x00},
+ {R367TER_DEBG_LT19, 0x00},
+ {R367TER_DEBG_LT1A, 0x00},
+ {R367TER_DEBG_LT1B, 0x00},
+ {R367TER_DEBG_LT1C, 0x00},
+ {R367TER_DEBG_LT1D, 0x00},
+ {R367TER_DEBG_LT1E, 0x00},
+ {R367TER_DEBG_LT1F, 0x00},
+ {R367TER_RCCFGH, 0x00},
+ {R367TER_RCCFGM, 0x00},
+ {R367TER_RCCFGL, 0x00},
+ {R367TER_RCINSDELH, 0x00},
+ {R367TER_RCINSDELM, 0x00},
+ {R367TER_RCINSDELL, 0x00},
+ {R367TER_RCSTATUS, 0x00},
+ {R367TER_RCSPEED, 0x6f},
+ {R367TER_RCDEBUGM, 0xe7},
+ {R367TER_RCDEBUGL, 0x9b},
+ {R367TER_RCOBSCFG, 0x00},
+ {R367TER_RCOBSM, 0x00},
+ {R367TER_RCOBSL, 0x00},
+ {R367TER_RCFECSPY, 0x00},
+ {R367TER_RCFSPYCFG, 0x00},
+ {R367TER_RCFSPYDATA, 0x00},
+ {R367TER_RCFSPYOUT, 0x00},
+ {R367TER_RCFSTATUS, 0x00},
+ {R367TER_RCFGOODPACK, 0x00},
+ {R367TER_RCFPACKCNT, 0x00},
+ {R367TER_RCFSPYMISC, 0x00},
+ {R367TER_RCFBERCPT4, 0x00},
+ {R367TER_RCFBERCPT3, 0x00},
+ {R367TER_RCFBERCPT2, 0x00},
+ {R367TER_RCFBERCPT1, 0x00},
+ {R367TER_RCFBERCPT0, 0x00},
+ {R367TER_RCFBERERR2, 0x00},
+ {R367TER_RCFBERERR1, 0x00},
+ {R367TER_RCFBERERR0, 0x00},
+ {R367TER_RCFSTATESM, 0x00},
+ {R367TER_RCFSTATESL, 0x00},
+ {R367TER_RCFSPYBER, 0x00},
+ {R367TER_RCFSPYDISTM, 0x00},
+ {R367TER_RCFSPYDISTL, 0x00},
+ {R367TER_RCFSPYOBS7, 0x00},
+ {R367TER_RCFSPYOBS6, 0x00},
+ {R367TER_RCFSPYOBS5, 0x00},
+ {R367TER_RCFSPYOBS4, 0x00},
+ {R367TER_RCFSPYOBS3, 0x00},
+ {R367TER_RCFSPYOBS2, 0x00},
+ {R367TER_RCFSPYOBS1, 0x00},
+ {R367TER_RCFSPYOBS0, 0x00},
+ {R367TER_TSGENERAL, 0x00},
+ {R367TER_RC1SPEED, 0x6f},
+ {R367TER_TSGSTATUS, 0x18},
+ {R367TER_FECM, 0x01},
+ {R367TER_VTH12, 0xff},
+ {R367TER_VTH23, 0xa1},
+ {R367TER_VTH34, 0x64},
+ {R367TER_VTH56, 0x40},
+ {R367TER_VTH67, 0x00},
+ {R367TER_VTH78, 0x2c},
+ {R367TER_VITCURPUN, 0x12},
+ {R367TER_VERROR, 0x01},
+ {R367TER_PRVIT, 0x3f},
+ {R367TER_VAVSRVIT, 0x00},
+ {R367TER_VSTATUSVIT, 0xbd},
+ {R367TER_VTHINUSE, 0xa1},
+ {R367TER_KDIV12, 0x20},
+ {R367TER_KDIV23, 0x40},
+ {R367TER_KDIV34, 0x20},
+ {R367TER_KDIV56, 0x30},
+ {R367TER_KDIV67, 0x00},
+ {R367TER_KDIV78, 0x30},
+ {R367TER_SIGPOWER, 0x54},
+ {R367TER_DEMAPVIT, 0x40},
+ {R367TER_VITSCALE, 0x00},
+ {R367TER_FFEC1PRG, 0x00},
+ {R367TER_FVITCURPUN, 0x12},
+ {R367TER_FVERROR, 0x01},
+ {R367TER_FVSTATUSVIT, 0xbd},
+ {R367TER_DEBUG_LT1, 0x00},
+ {R367TER_DEBUG_LT2, 0x00},
+ {R367TER_DEBUG_LT3, 0x00},
+ {R367TER_TSTSFMET, 0x00},
+ {R367TER_SELOUT, 0x00},
+ {R367TER_TSYNC, 0x00},
+ {R367TER_TSTERR, 0x00},
+ {R367TER_TSFSYNC, 0x00},
+ {R367TER_TSTSFERR, 0x00},
+ {R367TER_TSTTSSF1, 0x01},
+ {R367TER_TSTTSSF2, 0x1f},
+ {R367TER_TSTTSSF3, 0x00},
+ {R367TER_TSTTS1, 0x00},
+ {R367TER_TSTTS2, 0x1f},
+ {R367TER_TSTTS3, 0x01},
+ {R367TER_TSTTS4, 0x00},
+ {R367TER_TSTTSRC, 0x00},
+ {R367TER_TSTTSRS, 0x00},
+ {R367TER_TSSTATEM, 0xb0},
+ {R367TER_TSSTATEL, 0x40},
+ {R367TER_TSCFGH, 0xC0},
+ {R367TER_TSCFGM, 0xc0},/* for xc5000; was 0x00 */
+ {R367TER_TSCFGL, 0x20},
+ {R367TER_TSSYNC, 0x00},
+ {R367TER_TSINSDELH, 0x00},
+ {R367TER_TSINSDELM, 0x00},
+ {R367TER_TSINSDELL, 0x00},
+ {R367TER_TSDIVN, 0x03},
+ {R367TER_TSDIVPM, 0x00},
+ {R367TER_TSDIVPL, 0x00},
+ {R367TER_TSDIVQM, 0x00},
+ {R367TER_TSDIVQL, 0x00},
+ {R367TER_TSDILSTKM, 0x00},
+ {R367TER_TSDILSTKL, 0x00},
+ {R367TER_TSSPEED, 0x40},/* for xc5000; was 0x6f */
+ {R367TER_TSSTATUS, 0x81},
+ {R367TER_TSSTATUS2, 0x6a},
+ {R367TER_TSBITRATEM, 0x0f},
+ {R367TER_TSBITRATEL, 0xc6},
+ {R367TER_TSPACKLENM, 0x00},
+ {R367TER_TSPACKLENL, 0xfc},
+ {R367TER_TSBLOCLENM, 0x0a},
+ {R367TER_TSBLOCLENL, 0x80},
+ {R367TER_TSDLYH, 0x90},
+ {R367TER_TSDLYM, 0x68},
+ {R367TER_TSDLYL, 0x01},
+ {R367TER_TSNPDAV, 0x00},
+ {R367TER_TSBUFSTATH, 0x00},
+ {R367TER_TSBUFSTATM, 0x00},
+ {R367TER_TSBUFSTATL, 0x00},
+ {R367TER_TSDEBUGM, 0xcf},
+ {R367TER_TSDEBUGL, 0x1e},
+ {R367TER_TSDLYSETH, 0x00},
+ {R367TER_TSDLYSETM, 0x68},
+ {R367TER_TSDLYSETL, 0x00},
+ {R367TER_TSOBSCFG, 0x00},
+ {R367TER_TSOBSM, 0x47},
+ {R367TER_TSOBSL, 0x1f},
+ {R367TER_ERRCTRL1, 0x95},
+ {R367TER_ERRCNT1H, 0x80},
+ {R367TER_ERRCNT1M, 0x00},
+ {R367TER_ERRCNT1L, 0x00},
+ {R367TER_ERRCTRL2, 0x95},
+ {R367TER_ERRCNT2H, 0x00},
+ {R367TER_ERRCNT2M, 0x00},
+ {R367TER_ERRCNT2L, 0x00},
+ {R367TER_FECSPY, 0x88},
+ {R367TER_FSPYCFG, 0x2c},
+ {R367TER_FSPYDATA, 0x3a},
+ {R367TER_FSPYOUT, 0x06},
+ {R367TER_FSTATUS, 0x61},
+ {R367TER_FGOODPACK, 0xff},
+ {R367TER_FPACKCNT, 0xff},
+ {R367TER_FSPYMISC, 0x66},
+ {R367TER_FBERCPT4, 0x00},
+ {R367TER_FBERCPT3, 0x00},
+ {R367TER_FBERCPT2, 0x36},
+ {R367TER_FBERCPT1, 0x36},
+ {R367TER_FBERCPT0, 0x14},
+ {R367TER_FBERERR2, 0x00},
+ {R367TER_FBERERR1, 0x03},
+ {R367TER_FBERERR0, 0x28},
+ {R367TER_FSTATESM, 0x00},
+ {R367TER_FSTATESL, 0x02},
+ {R367TER_FSPYBER, 0x00},
+ {R367TER_FSPYDISTM, 0x01},
+ {R367TER_FSPYDISTL, 0x9f},
+ {R367TER_FSPYOBS7, 0xc9},
+ {R367TER_FSPYOBS6, 0x99},
+ {R367TER_FSPYOBS5, 0x08},
+ {R367TER_FSPYOBS4, 0xec},
+ {R367TER_FSPYOBS3, 0x01},
+ {R367TER_FSPYOBS2, 0x0f},
+ {R367TER_FSPYOBS1, 0xf5},
+ {R367TER_FSPYOBS0, 0x08},
+ {R367TER_SFDEMAP, 0x40},
+ {R367TER_SFERROR, 0x00},
+ {R367TER_SFAVSR, 0x30},
+ {R367TER_SFECSTATUS, 0xcc},
+ {R367TER_SFKDIV12, 0x20},
+ {R367TER_SFKDIV23, 0x40},
+ {R367TER_SFKDIV34, 0x20},
+ {R367TER_SFKDIV56, 0x20},
+ {R367TER_SFKDIV67, 0x00},
+ {R367TER_SFKDIV78, 0x20},
+ {R367TER_SFDILSTKM, 0x00},
+ {R367TER_SFDILSTKL, 0x00},
+ {R367TER_SFSTATUS, 0xb5},
+ {R367TER_SFDLYH, 0x90},
+ {R367TER_SFDLYM, 0x60},
+ {R367TER_SFDLYL, 0x01},
+ {R367TER_SFDLYSETH, 0xc0},
+ {R367TER_SFDLYSETM, 0x60},
+ {R367TER_SFDLYSETL, 0x00},
+ {R367TER_SFOBSCFG, 0x00},
+ {R367TER_SFOBSM, 0x47},
+ {R367TER_SFOBSL, 0x05},
+ {R367TER_SFECINFO, 0x40},
+ {R367TER_SFERRCTRL, 0x74},
+ {R367TER_SFERRCNTH, 0x80},
+ {R367TER_SFERRCNTM , 0x00},
+ {R367TER_SFERRCNTL, 0x00},
+ {R367TER_SYMBRATEM, 0x2f},
+ {R367TER_SYMBRATEL, 0x50},
+ {R367TER_SYMBSTATUS, 0x7f},
+ {R367TER_SYMBCFG, 0x00},
+ {R367TER_SYMBFIFOM, 0xf4},
+ {R367TER_SYMBFIFOL, 0x0d},
+ {R367TER_SYMBOFFSM, 0xf0},
+ {R367TER_SYMBOFFSL, 0x2d},
+ {R367TER_DEBUG_LT4, 0x00},
+ {R367TER_DEBUG_LT5, 0x00},
+ {R367TER_DEBUG_LT6, 0x00},
+ {R367TER_DEBUG_LT7, 0x00},
+ {R367TER_DEBUG_LT8, 0x00},
+ {R367TER_DEBUG_LT9, 0x00},
+};
+
+#define RF_LOOKUP_TABLE_SIZE 31
+#define RF_LOOKUP_TABLE2_SIZE 16
+/* RF Level (for RF AGC->AGC1) Lookup Table, depends on the board and tuner.*/
+s32 stv0367cab_RF_LookUp1[RF_LOOKUP_TABLE_SIZE][RF_LOOKUP_TABLE_SIZE] = {
+ {/*AGC1*/
+ 48, 50, 51, 53, 54, 56, 57, 58, 60, 61, 62, 63,
+ 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75,
+ 76, 77, 78, 80, 83, 85, 88,
+ }, {/*RF(dbm)*/
+ 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33,
+ 34, 35, 36, 37, 38, 39, 41, 42, 43, 44, 46, 47,
+ 49, 50, 52, 53, 54, 55, 56,
+ }
+};
+/* RF Level (for IF AGC->AGC2) Lookup Table, depends on the board and tuner.*/
+s32 stv0367cab_RF_LookUp2[RF_LOOKUP_TABLE2_SIZE][RF_LOOKUP_TABLE2_SIZE] = {
+ {/*AGC2*/
+ 28, 29, 31, 32, 34, 35, 36, 37,
+ 38, 39, 40, 41, 42, 43, 44, 45,
+ }, {/*RF(dbm)*/
+ 57, 58, 59, 60, 61, 62, 63, 64,
+ 65, 66, 67, 68, 69, 70, 71, 72,
+ }
+};
+
+static struct st_register def0367cab[STV0367CAB_NBREGS] = {
+ {R367CAB_ID, 0x60},
+ {R367CAB_I2CRPT, 0xa0},
+ /*{R367CAB_I2CRPT, 0x22},*/
+ {R367CAB_TOPCTRL, 0x10},
+ {R367CAB_IOCFG0, 0x80},
+ {R367CAB_DAC0R, 0x00},
+ {R367CAB_IOCFG1, 0x00},
+ {R367CAB_DAC1R, 0x00},
+ {R367CAB_IOCFG2, 0x00},
+ {R367CAB_SDFR, 0x00},
+ {R367CAB_AUX_CLK, 0x00},
+ {R367CAB_FREESYS1, 0x00},
+ {R367CAB_FREESYS2, 0x00},
+ {R367CAB_FREESYS3, 0x00},
+ {R367CAB_GPIO_CFG, 0x55},
+ {R367CAB_GPIO_CMD, 0x01},
+ {R367CAB_TSTRES, 0x00},
+ {R367CAB_ANACTRL, 0x0d},/* was 0x00 need to check - I.M.L.*/
+ {R367CAB_TSTBUS, 0x00},
+ {R367CAB_RF_AGC1, 0xea},
+ {R367CAB_RF_AGC2, 0x82},
+ {R367CAB_ANADIGCTRL, 0x0b},
+ {R367CAB_PLLMDIV, 0x01},
+ {R367CAB_PLLNDIV, 0x08},
+ {R367CAB_PLLSETUP, 0x18},
+ {R367CAB_DUAL_AD12, 0x0C}, /* for xc5000 AGC voltage 1.6V */
+ {R367CAB_TSTBIST, 0x00},
+ {R367CAB_CTRL_1, 0x00},
+ {R367CAB_CTRL_2, 0x03},
+ {R367CAB_IT_STATUS1, 0x2b},
+ {R367CAB_IT_STATUS2, 0x08},
+ {R367CAB_IT_EN1, 0x00},
+ {R367CAB_IT_EN2, 0x00},
+ {R367CAB_CTRL_STATUS, 0x04},
+ {R367CAB_TEST_CTL, 0x00},
+ {R367CAB_AGC_CTL, 0x73},
+ {R367CAB_AGC_IF_CFG, 0x50},
+ {R367CAB_AGC_RF_CFG, 0x00},
+ {R367CAB_AGC_PWM_CFG, 0x03},
+ {R367CAB_AGC_PWR_REF_L, 0x5a},
+ {R367CAB_AGC_PWR_REF_H, 0x00},
+ {R367CAB_AGC_RF_TH_L, 0xff},
+ {R367CAB_AGC_RF_TH_H, 0x07},
+ {R367CAB_AGC_IF_LTH_L, 0x00},
+ {R367CAB_AGC_IF_LTH_H, 0x08},
+ {R367CAB_AGC_IF_HTH_L, 0xff},
+ {R367CAB_AGC_IF_HTH_H, 0x07},
+ {R367CAB_AGC_PWR_RD_L, 0xa0},
+ {R367CAB_AGC_PWR_RD_M, 0xe9},
+ {R367CAB_AGC_PWR_RD_H, 0x03},
+ {R367CAB_AGC_PWM_IFCMD_L, 0xe4},
+ {R367CAB_AGC_PWM_IFCMD_H, 0x00},
+ {R367CAB_AGC_PWM_RFCMD_L, 0xff},
+ {R367CAB_AGC_PWM_RFCMD_H, 0x07},
+ {R367CAB_IQDEM_CFG, 0x01},
+ {R367CAB_MIX_NCO_LL, 0x22},
+ {R367CAB_MIX_NCO_HL, 0x96},
+ {R367CAB_MIX_NCO_HH, 0x55},
+ {R367CAB_SRC_NCO_LL, 0xff},
+ {R367CAB_SRC_NCO_LH, 0x0c},
+ {R367CAB_SRC_NCO_HL, 0xf5},
+ {R367CAB_SRC_NCO_HH, 0x20},
+ {R367CAB_IQDEM_GAIN_SRC_L, 0x06},
+ {R367CAB_IQDEM_GAIN_SRC_H, 0x01},
+ {R367CAB_IQDEM_DCRM_CFG_LL, 0xfe},
+ {R367CAB_IQDEM_DCRM_CFG_LH, 0xff},
+ {R367CAB_IQDEM_DCRM_CFG_HL, 0x0f},
+ {R367CAB_IQDEM_DCRM_CFG_HH, 0x00},
+ {R367CAB_IQDEM_ADJ_COEFF0, 0x34},
+ {R367CAB_IQDEM_ADJ_COEFF1, 0xae},
+ {R367CAB_IQDEM_ADJ_COEFF2, 0x46},
+ {R367CAB_IQDEM_ADJ_COEFF3, 0x77},
+ {R367CAB_IQDEM_ADJ_COEFF4, 0x96},
+ {R367CAB_IQDEM_ADJ_COEFF5, 0x69},
+ {R367CAB_IQDEM_ADJ_COEFF6, 0xc7},
+ {R367CAB_IQDEM_ADJ_COEFF7, 0x01},
+ {R367CAB_IQDEM_ADJ_EN, 0x04},
+ {R367CAB_IQDEM_ADJ_AGC_REF, 0x94},
+ {R367CAB_ALLPASSFILT1, 0xc9},
+ {R367CAB_ALLPASSFILT2, 0x2d},
+ {R367CAB_ALLPASSFILT3, 0xa3},
+ {R367CAB_ALLPASSFILT4, 0xfb},
+ {R367CAB_ALLPASSFILT5, 0xf6},
+ {R367CAB_ALLPASSFILT6, 0x45},
+ {R367CAB_ALLPASSFILT7, 0x6f},
+ {R367CAB_ALLPASSFILT8, 0x7e},
+ {R367CAB_ALLPASSFILT9, 0x05},
+ {R367CAB_ALLPASSFILT10, 0x0a},
+ {R367CAB_ALLPASSFILT11, 0x51},
+ {R367CAB_TRL_AGC_CFG, 0x20},
+ {R367CAB_TRL_LPF_CFG, 0x28},
+ {R367CAB_TRL_LPF_ACQ_GAIN, 0x44},
+ {R367CAB_TRL_LPF_TRK_GAIN, 0x22},
+ {R367CAB_TRL_LPF_OUT_GAIN, 0x03},
+ {R367CAB_TRL_LOCKDET_LTH, 0x04},
+ {R367CAB_TRL_LOCKDET_HTH, 0x11},
+ {R367CAB_TRL_LOCKDET_TRGVAL, 0x20},
+ {R367CAB_IQ_QAM, 0x01},
+ {R367CAB_FSM_STATE, 0xa0},
+ {R367CAB_FSM_CTL, 0x08},
+ {R367CAB_FSM_STS, 0x0c},
+ {R367CAB_FSM_SNR0_HTH, 0x00},
+ {R367CAB_FSM_SNR1_HTH, 0x00},
+ {R367CAB_FSM_SNR2_HTH, 0x23},/* 0x00 */
+ {R367CAB_FSM_SNR0_LTH, 0x00},
+ {R367CAB_FSM_SNR1_LTH, 0x00},
+ {R367CAB_FSM_EQA1_HTH, 0x00},
+ {R367CAB_FSM_TEMPO, 0x32},
+ {R367CAB_FSM_CONFIG, 0x03},
+ {R367CAB_EQU_I_TESTTAP_L, 0x11},
+ {R367CAB_EQU_I_TESTTAP_M, 0x00},
+ {R367CAB_EQU_I_TESTTAP_H, 0x00},
+ {R367CAB_EQU_TESTAP_CFG, 0x00},
+ {R367CAB_EQU_Q_TESTTAP_L, 0xff},
+ {R367CAB_EQU_Q_TESTTAP_M, 0x00},
+ {R367CAB_EQU_Q_TESTTAP_H, 0x00},
+ {R367CAB_EQU_TAP_CTRL, 0x00},
+ {R367CAB_EQU_CTR_CRL_CONTROL_L, 0x11},
+ {R367CAB_EQU_CTR_CRL_CONTROL_H, 0x05},
+ {R367CAB_EQU_CTR_HIPOW_L, 0x00},
+ {R367CAB_EQU_CTR_HIPOW_H, 0x00},
+ {R367CAB_EQU_I_EQU_LO, 0xef},
+ {R367CAB_EQU_I_EQU_HI, 0x00},
+ {R367CAB_EQU_Q_EQU_LO, 0xee},
+ {R367CAB_EQU_Q_EQU_HI, 0x00},
+ {R367CAB_EQU_MAPPER, 0xc5},
+ {R367CAB_EQU_SWEEP_RATE, 0x80},
+ {R367CAB_EQU_SNR_LO, 0x64},
+ {R367CAB_EQU_SNR_HI, 0x03},
+ {R367CAB_EQU_GAMMA_LO, 0x00},
+ {R367CAB_EQU_GAMMA_HI, 0x00},
+ {R367CAB_EQU_ERR_GAIN, 0x36},
+ {R367CAB_EQU_RADIUS, 0xaa},
+ {R367CAB_EQU_FFE_MAINTAP, 0x00},
+ {R367CAB_EQU_FFE_LEAKAGE, 0x63},
+ {R367CAB_EQU_FFE_MAINTAP_POS, 0xdf},
+ {R367CAB_EQU_GAIN_WIDE, 0x88},
+ {R367CAB_EQU_GAIN_NARROW, 0x41},
+ {R367CAB_EQU_CTR_LPF_GAIN, 0xd1},
+ {R367CAB_EQU_CRL_LPF_GAIN, 0xa7},
+ {R367CAB_EQU_GLOBAL_GAIN, 0x06},
+ {R367CAB_EQU_CRL_LD_SEN, 0x85},
+ {R367CAB_EQU_CRL_LD_VAL, 0xe2},
+ {R367CAB_EQU_CRL_TFR, 0x20},
+ {R367CAB_EQU_CRL_BISTH_LO, 0x00},
+ {R367CAB_EQU_CRL_BISTH_HI, 0x00},
+ {R367CAB_EQU_SWEEP_RANGE_LO, 0x00},
+ {R367CAB_EQU_SWEEP_RANGE_HI, 0x00},
+ {R367CAB_EQU_CRL_LIMITER, 0x40},
+ {R367CAB_EQU_MODULUS_MAP, 0x90},
+ {R367CAB_EQU_PNT_GAIN, 0xa7},
+ {R367CAB_FEC_AC_CTR_0, 0x16},
+ {R367CAB_FEC_AC_CTR_1, 0x0b},
+ {R367CAB_FEC_AC_CTR_2, 0x88},
+ {R367CAB_FEC_AC_CTR_3, 0x02},
+ {R367CAB_FEC_STATUS, 0x12},
+ {R367CAB_RS_COUNTER_0, 0x7d},
+ {R367CAB_RS_COUNTER_1, 0xd0},
+ {R367CAB_RS_COUNTER_2, 0x19},
+ {R367CAB_RS_COUNTER_3, 0x0b},
+ {R367CAB_RS_COUNTER_4, 0xa3},
+ {R367CAB_RS_COUNTER_5, 0x00},
+ {R367CAB_BERT_0, 0x01},
+ {R367CAB_BERT_1, 0x25},
+ {R367CAB_BERT_2, 0x41},
+ {R367CAB_BERT_3, 0x39},
+ {R367CAB_OUTFORMAT_0, 0xc2},
+ {R367CAB_OUTFORMAT_1, 0x22},
+ {R367CAB_SMOOTHER_2, 0x28},
+ {R367CAB_TSMF_CTRL_0, 0x01},
+ {R367CAB_TSMF_CTRL_1, 0xc6},
+ {R367CAB_TSMF_CTRL_3, 0x43},
+ {R367CAB_TS_ON_ID_0, 0x00},
+ {R367CAB_TS_ON_ID_1, 0x00},
+ {R367CAB_TS_ON_ID_2, 0x00},
+ {R367CAB_TS_ON_ID_3, 0x00},
+ {R367CAB_RE_STATUS_0, 0x00},
+ {R367CAB_RE_STATUS_1, 0x00},
+ {R367CAB_RE_STATUS_2, 0x00},
+ {R367CAB_RE_STATUS_3, 0x00},
+ {R367CAB_TS_STATUS_0, 0x00},
+ {R367CAB_TS_STATUS_1, 0x00},
+ {R367CAB_TS_STATUS_2, 0xa0},
+ {R367CAB_TS_STATUS_3, 0x00},
+ {R367CAB_T_O_ID_0, 0x00},
+ {R367CAB_T_O_ID_1, 0x00},
+ {R367CAB_T_O_ID_2, 0x00},
+ {R367CAB_T_O_ID_3, 0x00},
+};
+
+static
+int stv0367_writeregs(struct stv0367_state *state, u16 reg, u8 *data, int len)
+{
+ u8 buf[len + 2];
+ struct i2c_msg msg = {
+ .addr = state->config->demod_address,
+ .flags = 0,
+ .buf = buf,
+ .len = len + 2
+ };
+ int ret;
+
+ buf[0] = MSB(reg);
+ buf[1] = LSB(reg);
+ memcpy(buf + 2, data, len);
+
+ if (i2cdebug)
+ printk(KERN_DEBUG "%s: %02x: %02x\n", __func__, reg, buf[2]);
+
+ ret = i2c_transfer(state->i2c, &msg, 1);
+ if (ret != 1)
+ printk(KERN_ERR "%s: i2c write error!\n", __func__);
+
+ return (ret != 1) ? -EREMOTEIO : 0;
+}
+
+static int stv0367_writereg(struct stv0367_state *state, u16 reg, u8 data)
+{
+ return stv0367_writeregs(state, reg, &data, 1);
+}
+
+static u8 stv0367_readreg(struct stv0367_state *state, u16 reg)
+{
+ u8 b0[] = { 0, 0 };
+ u8 b1[] = { 0 };
+ struct i2c_msg msg[] = {
+ {
+ .addr = state->config->demod_address,
+ .flags = 0,
+ .buf = b0,
+ .len = 2
+ }, {
+ .addr = state->config->demod_address,
+ .flags = I2C_M_RD,
+ .buf = b1,
+ .len = 1
+ }
+ };
+ int ret;
+
+ b0[0] = MSB(reg);
+ b0[1] = LSB(reg);
+
+ ret = i2c_transfer(state->i2c, msg, 2);
+ if (ret != 2)
+ printk(KERN_ERR "%s: i2c read error\n", __func__);
+
+ if (i2cdebug)
+ printk(KERN_DEBUG "%s: %02x: %02x\n", __func__, reg, b1[0]);
+
+ return b1[0];
+}
+
+static void extract_mask_pos(u32 label, u8 *mask, u8 *pos)
+{
+ u8 position = 0, i = 0;
+
+ (*mask) = label & 0xff;
+
+ while ((position == 0) && (i < 8)) {
+ position = ((*mask) >> i) & 0x01;
+ i++;
+ }
+
+ (*pos) = (i - 1);
+}
+
+static void stv0367_writebits(struct stv0367_state *state, u32 label, u8 val)
+{
+ u8 reg, mask, pos;
+
+ reg = stv0367_readreg(state, (label >> 16) & 0xffff);
+ extract_mask_pos(label, &mask, &pos);
+
+ val = mask & (val << pos);
+
+ reg = (reg & (~mask)) | val;
+ stv0367_writereg(state, (label >> 16) & 0xffff, reg);
+
+}
+
+static void stv0367_setbits(u8 *reg, u32 label, u8 val)
+{
+ u8 mask, pos;
+
+ extract_mask_pos(label, &mask, &pos);
+
+ val = mask & (val << pos);
+
+ (*reg) = ((*reg) & (~mask)) | val;
+}
+
+static u8 stv0367_readbits(struct stv0367_state *state, u32 label)
+{
+ u8 val = 0xff;
+ u8 mask, pos;
+
+ extract_mask_pos(label, &mask, &pos);
+
+ val = stv0367_readreg(state, label >> 16);
+ val = (val & mask) >> pos;
+
+ return val;
+}
+
+u8 stv0367_getbits(u8 reg, u32 label)
+{
+ u8 mask, pos;
+
+ extract_mask_pos(label, &mask, &pos);
+
+ return (reg & mask) >> pos;
+}
+
+static int stv0367ter_gate_ctrl(struct dvb_frontend *fe, int enable)
+{
+ struct stv0367_state *state = fe->demodulator_priv;
+ u8 tmp = stv0367_readreg(state, R367TER_I2CRPT);
+
+ dprintk("%s:\n", __func__);
+
+ if (enable) {
+ stv0367_setbits(&tmp, F367TER_STOP_ENABLE, 0);
+ stv0367_setbits(&tmp, F367TER_I2CT_ON, 1);
+ } else {
+ stv0367_setbits(&tmp, F367TER_STOP_ENABLE, 1);
+ stv0367_setbits(&tmp, F367TER_I2CT_ON, 0);
+ }
+
+ stv0367_writereg(state, R367TER_I2CRPT, tmp);
+
+ return 0;
+}
+
+static u32 stv0367_get_tuner_freq(struct dvb_frontend *fe)
+{
+ struct dvb_frontend_ops *frontend_ops = NULL;
+ struct dvb_tuner_ops *tuner_ops = NULL;
+ u32 freq = 0;
+ int err = 0;
+
+ dprintk("%s:\n", __func__);
+
+
+ if (&fe->ops)
+ frontend_ops = &fe->ops;
+ if (&frontend_ops->tuner_ops)
+ tuner_ops = &frontend_ops->tuner_ops;
+ if (tuner_ops->get_frequency) {
+ err = tuner_ops->get_frequency(fe, &freq);
+ if (err < 0) {
+ printk(KERN_ERR "%s: Invalid parameter\n", __func__);
+ return err;
+ }
+
+ dprintk("%s: frequency=%d\n", __func__, freq);
+
+ } else
+ return -1;
+
+ return freq;
+}
+
+static u16 CellsCoeffs_8MHz_367cofdm[3][6][5] = {
+ {
+ {0x10EF, 0xE205, 0x10EF, 0xCE49, 0x6DA7}, /* CELL 1 COEFFS 27M*/
+ {0x2151, 0xc557, 0x2151, 0xc705, 0x6f93}, /* CELL 2 COEFFS */
+ {0x2503, 0xc000, 0x2503, 0xc375, 0x7194}, /* CELL 3 COEFFS */
+ {0x20E9, 0xca94, 0x20e9, 0xc153, 0x7194}, /* CELL 4 COEFFS */
+ {0x06EF, 0xF852, 0x06EF, 0xC057, 0x7207}, /* CELL 5 COEFFS */
+ {0x0000, 0x0ECC, 0x0ECC, 0x0000, 0x3647} /* CELL 6 COEFFS */
+ }, {
+ {0x10A0, 0xE2AF, 0x10A1, 0xCE76, 0x6D6D}, /* CELL 1 COEFFS 25M*/
+ {0x20DC, 0xC676, 0x20D9, 0xC80A, 0x6F29},
+ {0x2532, 0xC000, 0x251D, 0xC391, 0x706F},
+ {0x1F7A, 0xCD2B, 0x2032, 0xC15E, 0x711F},
+ {0x0698, 0xFA5E, 0x0568, 0xC059, 0x7193},
+ {0x0000, 0x0918, 0x149C, 0x0000, 0x3642} /* CELL 6 COEFFS */
+ }, {
+ {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}, /* 30M */
+ {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
+ {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
+ {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
+ {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
+ {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}
+ }
+};
+
+static u16 CellsCoeffs_7MHz_367cofdm[3][6][5] = {
+ {
+ {0x12CA, 0xDDAF, 0x12CA, 0xCCEB, 0x6FB1}, /* CELL 1 COEFFS 27M*/
+ {0x2329, 0xC000, 0x2329, 0xC6B0, 0x725F}, /* CELL 2 COEFFS */
+ {0x2394, 0xC000, 0x2394, 0xC2C7, 0x7410}, /* CELL 3 COEFFS */
+ {0x251C, 0xC000, 0x251C, 0xC103, 0x74D9}, /* CELL 4 COEFFS */
+ {0x0804, 0xF546, 0x0804, 0xC040, 0x7544}, /* CELL 5 COEFFS */
+ {0x0000, 0x0CD9, 0x0CD9, 0x0000, 0x370A} /* CELL 6 COEFFS */
+ }, {
+ {0x1285, 0xDE47, 0x1285, 0xCD17, 0x6F76}, /*25M*/
+ {0x234C, 0xC000, 0x2348, 0xC6DA, 0x7206},
+ {0x23B4, 0xC000, 0x23AC, 0xC2DB, 0x73B3},
+ {0x253D, 0xC000, 0x25B6, 0xC10B, 0x747F},
+ {0x0721, 0xF79C, 0x065F, 0xC041, 0x74EB},
+ {0x0000, 0x08FA, 0x1162, 0x0000, 0x36FF}
+ }, {
+ {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}, /* 30M */
+ {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
+ {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
+ {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
+ {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
+ {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}
+ }
+};
+
+static u16 CellsCoeffs_6MHz_367cofdm[3][6][5] = {
+ {
+ {0x1699, 0xD5B8, 0x1699, 0xCBC3, 0x713B}, /* CELL 1 COEFFS 27M*/
+ {0x2245, 0xC000, 0x2245, 0xC568, 0x74D5}, /* CELL 2 COEFFS */
+ {0x227F, 0xC000, 0x227F, 0xC1FC, 0x76C6}, /* CELL 3 COEFFS */
+ {0x235E, 0xC000, 0x235E, 0xC0A7, 0x778A}, /* CELL 4 COEFFS */
+ {0x0ECB, 0xEA0B, 0x0ECB, 0xC027, 0x77DD}, /* CELL 5 COEFFS */
+ {0x0000, 0x0B68, 0x0B68, 0x0000, 0xC89A}, /* CELL 6 COEFFS */
+ }, {
+ {0x1655, 0xD64E, 0x1658, 0xCBEF, 0x70FE}, /*25M*/
+ {0x225E, 0xC000, 0x2256, 0xC589, 0x7489},
+ {0x2293, 0xC000, 0x2295, 0xC209, 0x767E},
+ {0x2377, 0xC000, 0x23AA, 0xC0AB, 0x7746},
+ {0x0DC7, 0xEBC8, 0x0D07, 0xC027, 0x7799},
+ {0x0000, 0x0888, 0x0E9C, 0x0000, 0x3757}
+
+ }, {
+ {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}, /* 30M */
+ {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
+ {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
+ {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
+ {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
+ {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}
+ }
+};
+
+static u32 stv0367ter_get_mclk(struct stv0367_state *state, u32 ExtClk_Hz)
+{
+ u32 mclk_Hz = 0; /* master clock frequency (Hz) */
+ u32 m, n, p;
+
+ dprintk("%s:\n", __func__);
+
+ if (stv0367_readbits(state, F367TER_BYPASS_PLLXN) == 0) {
+ n = (u32)stv0367_readbits(state, F367TER_PLL_NDIV);
+ if (n == 0)
+ n = n + 1;
+
+ m = (u32)stv0367_readbits(state, F367TER_PLL_MDIV);
+ if (m == 0)
+ m = m + 1;
+
+ p = (u32)stv0367_readbits(state, F367TER_PLL_PDIV);
+ if (p > 5)
+ p = 5;
+
+ mclk_Hz = ((ExtClk_Hz / 2) * n) / (m * (1 << p));
+
+ dprintk("N=%d M=%d P=%d mclk_Hz=%d ExtClk_Hz=%d\n",
+ n, m, p, mclk_Hz, ExtClk_Hz);
+ } else
+ mclk_Hz = ExtClk_Hz;
+
+ dprintk("%s: mclk_Hz=%d\n", __func__, mclk_Hz);
+
+ return mclk_Hz;
+}
+
+static int stv0367ter_filt_coeff_init(struct stv0367_state *state,
+ u16 CellsCoeffs[3][6][5], u32 DemodXtal)
+{
+ int i, j, k, freq;
+
+ dprintk("%s:\n", __func__);
+
+ freq = stv0367ter_get_mclk(state, DemodXtal);
+
+ if (freq == 53125000)
+ k = 1; /* equivalent to Xtal 25M on 362*/
+ else if (freq == 54000000)
+ k = 0; /* equivalent to Xtal 27M on 362*/
+ else if (freq == 52500000)
+ k = 2; /* equivalent to Xtal 30M on 362*/
+ else
+ return 0;
+
+ for (i = 1; i <= 6; i++) {
+ stv0367_writebits(state, F367TER_IIR_CELL_NB, i - 1);
+
+ for (j = 1; j <= 5; j++) {
+ stv0367_writereg(state,
+ (R367TER_IIRCX_COEFF1_MSB + 2 * (j - 1)),
+ MSB(CellsCoeffs[k][i-1][j-1]));
+ stv0367_writereg(state,
+ (R367TER_IIRCX_COEFF1_LSB + 2 * (j - 1)),
+ LSB(CellsCoeffs[k][i-1][j-1]));
+ }
+ }
+
+ return 1;
+
+}
+
+static void stv0367ter_agc_iir_lock_detect_set(struct stv0367_state *state)
+{
+ dprintk("%s:\n", __func__);
+
+ stv0367_writebits(state, F367TER_LOCK_DETECT_LSB, 0x00);
+
+ /* Lock detect 1 */
+ stv0367_writebits(state, F367TER_LOCK_DETECT_CHOICE, 0x00);
+ stv0367_writebits(state, F367TER_LOCK_DETECT_MSB, 0x06);
+ stv0367_writebits(state, F367TER_AUT_AGC_TARGET_LSB, 0x04);
+
+ /* Lock detect 2 */
+ stv0367_writebits(state, F367TER_LOCK_DETECT_CHOICE, 0x01);
+ stv0367_writebits(state, F367TER_LOCK_DETECT_MSB, 0x06);
+ stv0367_writebits(state, F367TER_AUT_AGC_TARGET_LSB, 0x04);
+
+ /* Lock detect 3 */
+ stv0367_writebits(state, F367TER_LOCK_DETECT_CHOICE, 0x02);
+ stv0367_writebits(state, F367TER_LOCK_DETECT_MSB, 0x01);
+ stv0367_writebits(state, F367TER_AUT_AGC_TARGET_LSB, 0x00);
+
+ /* Lock detect 4 */
+ stv0367_writebits(state, F367TER_LOCK_DETECT_CHOICE, 0x03);
+ stv0367_writebits(state, F367TER_LOCK_DETECT_MSB, 0x01);
+ stv0367_writebits(state, F367TER_AUT_AGC_TARGET_LSB, 0x00);
+
+}
+
+static int stv0367_iir_filt_init(struct stv0367_state *state, u8 Bandwidth,
+ u32 DemodXtalValue)
+{
+ dprintk("%s:\n", __func__);
+
+ stv0367_writebits(state, F367TER_NRST_IIR, 0);
+
+ switch (Bandwidth) {
+ case 6:
+ if (!stv0367ter_filt_coeff_init(state,
+ CellsCoeffs_6MHz_367cofdm,
+ DemodXtalValue))
+ return 0;
+ break;
+ case 7:
+ if (!stv0367ter_filt_coeff_init(state,
+ CellsCoeffs_7MHz_367cofdm,
+ DemodXtalValue))
+ return 0;
+ break;
+ case 8:
+ if (!stv0367ter_filt_coeff_init(state,
+ CellsCoeffs_8MHz_367cofdm,
+ DemodXtalValue))
+ return 0;
+ break;
+ default:
+ return 0;
+ }
+
+ stv0367_writebits(state, F367TER_NRST_IIR, 1);
+
+ return 1;
+}
+
+static void stv0367ter_agc_iir_rst(struct stv0367_state *state)
+{
+
+ u8 com_n;
+
+ dprintk("%s:\n", __func__);
+
+ com_n = stv0367_readbits(state, F367TER_COM_N);
+
+ stv0367_writebits(state, F367TER_COM_N, 0x07);
+
+ stv0367_writebits(state, F367TER_COM_SOFT_RSTN, 0x00);
+ stv0367_writebits(state, F367TER_COM_AGC_ON, 0x00);
+
+ stv0367_writebits(state, F367TER_COM_SOFT_RSTN, 0x01);
+ stv0367_writebits(state, F367TER_COM_AGC_ON, 0x01);
+
+ stv0367_writebits(state, F367TER_COM_N, com_n);
+
+}
+
+static int stv0367ter_duration(s32 mode, int tempo1, int tempo2, int tempo3)
+{
+ int local_tempo = 0;
+ switch (mode) {
+ case 0:
+ local_tempo = tempo1;
+ break;
+ case 1:
+ local_tempo = tempo2;
+ break ;
+
+ case 2:
+ local_tempo = tempo3;
+ break;
+
+ default:
+ break;
+ }
+ /* msleep(local_tempo); */
+ return local_tempo;
+}
+
+static enum
+stv0367_ter_signal_type stv0367ter_check_syr(struct stv0367_state *state)
+{
+ int wd = 100;
+ unsigned short int SYR_var;
+ s32 SYRStatus;
+
+ dprintk("%s:\n", __func__);
+
+ SYR_var = stv0367_readbits(state, F367TER_SYR_LOCK);
+
+ while ((!SYR_var) && (wd > 0)) {
+ usleep_range(2000, 3000);
+ wd -= 2;
+ SYR_var = stv0367_readbits(state, F367TER_SYR_LOCK);
+ }
+
+ if (!SYR_var)
+ SYRStatus = FE_TER_NOSYMBOL;
+ else
+ SYRStatus = FE_TER_SYMBOLOK;
+
+ dprintk("stv0367ter_check_syr SYRStatus %s\n",
+ SYR_var == 0 ? "No Symbol" : "OK");
+
+ return SYRStatus;
+}
+
+static enum
+stv0367_ter_signal_type stv0367ter_check_cpamp(struct stv0367_state *state,
+ s32 FFTmode)
+{
+
+ s32 CPAMPvalue = 0, CPAMPStatus, CPAMPMin;
+ int wd = 0;
+
+ dprintk("%s:\n", __func__);
+
+ switch (FFTmode) {
+ case 0: /*2k mode*/
+ CPAMPMin = 20;
+ wd = 10;
+ break;
+ case 1: /*8k mode*/
+ CPAMPMin = 80;
+ wd = 55;
+ break;
+ case 2: /*4k mode*/
+ CPAMPMin = 40;
+ wd = 30;
+ break;
+ default:
+ CPAMPMin = 0xffff; /*drives to NOCPAMP */
+ break;
+ }
+
+ dprintk("%s: CPAMPMin=%d wd=%d\n", __func__, CPAMPMin, wd);
+
+ CPAMPvalue = stv0367_readbits(state, F367TER_PPM_CPAMP_DIRECT);
+ while ((CPAMPvalue < CPAMPMin) && (wd > 0)) {
+ usleep_range(1000, 2000);
+ wd -= 1;
+ CPAMPvalue = stv0367_readbits(state, F367TER_PPM_CPAMP_DIRECT);
+ /*dprintk("CPAMPvalue= %d at wd=%d\n",CPAMPvalue,wd); */
+ }
+ dprintk("******last CPAMPvalue= %d at wd=%d\n", CPAMPvalue, wd);
+ if (CPAMPvalue < CPAMPMin) {
+ CPAMPStatus = FE_TER_NOCPAMP;
+ printk(KERN_ERR "CPAMP failed\n");
+ } else {
+ printk(KERN_ERR "CPAMP OK !\n");
+ CPAMPStatus = FE_TER_CPAMPOK;
+ }
+
+ return CPAMPStatus;
+}
+
+enum
+stv0367_ter_signal_type stv0367ter_lock_algo(struct stv0367_state *state)
+{
+ enum stv0367_ter_signal_type ret_flag;
+ short int wd, tempo;
+ u8 try, u_var1 = 0, u_var2 = 0, u_var3 = 0, u_var4 = 0, mode, guard;
+ u8 tmp, tmp2;
+
+ dprintk("%s:\n", __func__);
+
+ if (state == NULL)
+ return FE_TER_SWNOK;
+
+ try = 0;
+ do {
+ ret_flag = FE_TER_LOCKOK;
+
+ stv0367_writebits(state, F367TER_CORE_ACTIVE, 0);
+
+ if (state->config->if_iq_mode != 0)
+ stv0367_writebits(state, F367TER_COM_N, 0x07);
+
+ stv0367_writebits(state, F367TER_GUARD, 3);/* suggest 2k 1/4 */
+ stv0367_writebits(state, F367TER_MODE, 0);
+ stv0367_writebits(state, F367TER_SYR_TR_DIS, 0);
+ usleep_range(5000, 10000);
+
+ stv0367_writebits(state, F367TER_CORE_ACTIVE, 1);
+
+
+ if (stv0367ter_check_syr(state) == FE_TER_NOSYMBOL)
+ return FE_TER_NOSYMBOL;
+ else { /*
+ if chip locked on wrong mode first try,
+ it must lock correctly second try */
+ mode = stv0367_readbits(state, F367TER_SYR_MODE);
+ if (stv0367ter_check_cpamp(state, mode) ==
+ FE_TER_NOCPAMP) {
+ if (try == 0)
+ ret_flag = FE_TER_NOCPAMP;
+
+ }
+ }
+
+ try++;
+ } while ((try < 10) && (ret_flag != FE_TER_LOCKOK));
+
+ tmp = stv0367_readreg(state, R367TER_SYR_STAT);
+ tmp2 = stv0367_readreg(state, R367TER_STATUS);
+ dprintk("state=%p\n", state);
+ dprintk("LOCK OK! mode=%d SYR_STAT=0x%x R367TER_STATUS=0x%x\n",
+ mode, tmp, tmp2);
+
+ tmp = stv0367_readreg(state, R367TER_PRVIT);
+ tmp2 = stv0367_readreg(state, R367TER_I2CRPT);
+ dprintk("PRVIT=0x%x I2CRPT=0x%x\n", tmp, tmp2);
+
+ tmp = stv0367_readreg(state, R367TER_GAIN_SRC1);
+ dprintk("GAIN_SRC1=0x%x\n", tmp);
+
+ if ((mode != 0) && (mode != 1) && (mode != 2))
+ return FE_TER_SWNOK;
+
+ /*guard=stv0367_readbits(state,F367TER_SYR_GUARD); */
+
+ /*suppress EPQ auto for SYR_GARD 1/16 or 1/32
+ and set channel predictor in automatic */
+#if 0
+ switch (guard) {
+
+ case 0:
+ case 1:
+ stv0367_writebits(state, F367TER_AUTO_LE_EN, 0);
+ stv0367_writereg(state, R367TER_CHC_CTL, 0x01);
+ break;
+ case 2:
+ case 3:
+ stv0367_writebits(state, F367TER_AUTO_LE_EN, 1);
+ stv0367_writereg(state, R367TER_CHC_CTL, 0x11);
+ break;
+
+ default:
+ return FE_TER_SWNOK;
+ }
+#endif
+
+ /*reset fec an reedsolo FOR 367 only*/
+ stv0367_writebits(state, F367TER_RST_SFEC, 1);
+ stv0367_writebits(state, F367TER_RST_REEDSOLO, 1);
+ usleep_range(1000, 2000);
+ stv0367_writebits(state, F367TER_RST_SFEC, 0);
+ stv0367_writebits(state, F367TER_RST_REEDSOLO, 0);
+
+ u_var1 = stv0367_readbits(state, F367TER_LK);
+ u_var2 = stv0367_readbits(state, F367TER_PRF);
+ u_var3 = stv0367_readbits(state, F367TER_TPS_LOCK);
+ /* u_var4=stv0367_readbits(state,F367TER_TSFIFO_LINEOK); */
+
+ wd = stv0367ter_duration(mode, 125, 500, 250);
+ tempo = stv0367ter_duration(mode, 4, 16, 8);
+
+ /*while ( ((!u_var1)||(!u_var2)||(!u_var3)||(!u_var4)) && (wd>=0)) */
+ while (((!u_var1) || (!u_var2) || (!u_var3)) && (wd >= 0)) {
+ usleep_range(1000 * tempo, 1000 * (tempo + 1));
+ wd -= tempo;
+ u_var1 = stv0367_readbits(state, F367TER_LK);
+ u_var2 = stv0367_readbits(state, F367TER_PRF);
+ u_var3 = stv0367_readbits(state, F367TER_TPS_LOCK);
+ /*u_var4=stv0367_readbits(state, F367TER_TSFIFO_LINEOK); */
+ }
+
+ if (!u_var1)
+ return FE_TER_NOLOCK;
+
+
+ if (!u_var2)
+ return FE_TER_NOPRFOUND;
+
+ if (!u_var3)
+ return FE_TER_NOTPS;
+
+ guard = stv0367_readbits(state, F367TER_SYR_GUARD);
+ stv0367_writereg(state, R367TER_CHC_CTL, 0x11);
+ switch (guard) {
+ case 0:
+ case 1:
+ stv0367_writebits(state, F367TER_AUTO_LE_EN, 0);
+ /*stv0367_writereg(state,R367TER_CHC_CTL, 0x1);*/
+ stv0367_writebits(state, F367TER_SYR_FILTER, 0);
+ break;
+ case 2:
+ case 3:
+ stv0367_writebits(state, F367TER_AUTO_LE_EN, 1);
+ /*stv0367_writereg(state,R367TER_CHC_CTL, 0x11);*/
+ stv0367_writebits(state, F367TER_SYR_FILTER, 1);
+ break;
+
+ default:
+ return FE_TER_SWNOK;
+ }
+
+ /* apply Sfec workaround if 8K 64QAM CR!=1/2*/
+ if ((stv0367_readbits(state, F367TER_TPS_CONST) == 2) &&
+ (mode == 1) &&
+ (stv0367_readbits(state, F367TER_TPS_HPCODE) != 0)) {
+ stv0367_writereg(state, R367TER_SFDLYSETH, 0xc0);
+ stv0367_writereg(state, R367TER_SFDLYSETM, 0x60);
+ stv0367_writereg(state, R367TER_SFDLYSETL, 0x0);
+ } else
+ stv0367_writereg(state, R367TER_SFDLYSETH, 0x0);
+
+ wd = stv0367ter_duration(mode, 125, 500, 250);
+ u_var4 = stv0367_readbits(state, F367TER_TSFIFO_LINEOK);
+
+ while ((!u_var4) && (wd >= 0)) {
+ usleep_range(1000 * tempo, 1000 * (tempo + 1));
+ wd -= tempo;
+ u_var4 = stv0367_readbits(state, F367TER_TSFIFO_LINEOK);
+ }
+
+ if (!u_var4)
+ return FE_TER_NOLOCK;
+
+ /* for 367 leave COM_N at 0x7 for IQ_mode*/
+ /*if(ter_state->if_iq_mode!=FE_TER_NORMAL_IF_TUNER) {
+ tempo=0;
+ while ((stv0367_readbits(state,F367TER_COM_USEGAINTRK)!=1) &&
+ (stv0367_readbits(state,F367TER_COM_AGCLOCK)!=1)&&(tempo<100)) {
+ ChipWaitOrAbort(state,1);
+ tempo+=1;
+ }
+
+ stv0367_writebits(state,F367TER_COM_N,0x17);
+ } */
+
+ stv0367_writebits(state, F367TER_SYR_TR_DIS, 1);
+
+ dprintk("FE_TER_LOCKOK !!!\n");
+
+ return FE_TER_LOCKOK;
+
+}
+
+static void stv0367ter_set_ts_mode(struct stv0367_state *state,
+ enum stv0367_ts_mode PathTS)
+{
+
+ dprintk("%s:\n", __func__);
+
+ if (state == NULL)
+ return;
+
+ stv0367_writebits(state, F367TER_TS_DIS, 0);
+ switch (PathTS) {
+ default:
+ /*for removing warning :default we can assume in parallel mode*/
+ case STV0367_PARALLEL_PUNCT_CLOCK:
+ stv0367_writebits(state, F367TER_TSFIFO_SERIAL, 0);
+ stv0367_writebits(state, F367TER_TSFIFO_DVBCI, 0);
+ break;
+ case STV0367_SERIAL_PUNCT_CLOCK:
+ stv0367_writebits(state, F367TER_TSFIFO_SERIAL, 1);
+ stv0367_writebits(state, F367TER_TSFIFO_DVBCI, 1);
+ break;
+ }
+}
+
+static void stv0367ter_set_clk_pol(struct stv0367_state *state,
+ enum stv0367_clk_pol clock)
+{
+
+ dprintk("%s:\n", __func__);
+
+ if (state == NULL)
+ return;
+
+ switch (clock) {
+ case STV0367_RISINGEDGE_CLOCK:
+ stv0367_writebits(state, F367TER_TS_BYTE_CLK_INV, 1);
+ break;
+ case STV0367_FALLINGEDGE_CLOCK:
+ stv0367_writebits(state, F367TER_TS_BYTE_CLK_INV, 0);
+ break;
+ /*case FE_TER_CLOCK_POLARITY_DEFAULT:*/
+ default:
+ stv0367_writebits(state, F367TER_TS_BYTE_CLK_INV, 0);
+ break;
+ }
+}
+
+#if 0
+static void stv0367ter_core_sw(struct stv0367_state *state)
+{
+
+ dprintk("%s:\n", __func__);
+
+ stv0367_writebits(state, F367TER_CORE_ACTIVE, 0);
+ stv0367_writebits(state, F367TER_CORE_ACTIVE, 1);
+ msleep(350);
+}
+#endif
+static int stv0367ter_standby(struct dvb_frontend *fe, u8 standby_on)
+{
+ struct stv0367_state *state = fe->demodulator_priv;
+
+ dprintk("%s:\n", __func__);
+
+ if (standby_on) {
+ stv0367_writebits(state, F367TER_STDBY, 1);
+ stv0367_writebits(state, F367TER_STDBY_FEC, 1);
+ stv0367_writebits(state, F367TER_STDBY_CORE, 1);
+ } else {
+ stv0367_writebits(state, F367TER_STDBY, 0);
+ stv0367_writebits(state, F367TER_STDBY_FEC, 0);
+ stv0367_writebits(state, F367TER_STDBY_CORE, 0);
+ }
+
+ return 0;
+}
+
+static int stv0367ter_sleep(struct dvb_frontend *fe)
+{
+ return stv0367ter_standby(fe, 1);
+}
+
+int stv0367ter_init(struct dvb_frontend *fe)
+{
+ struct stv0367_state *state = fe->demodulator_priv;
+ struct stv0367ter_state *ter_state = state->ter_state;
+ int i;
+
+ dprintk("%s:\n", __func__);
+
+ ter_state->pBER = 0;
+
+ for (i = 0; i < STV0367TER_NBREGS; i++)
+ stv0367_writereg(state, def0367ter[i].addr,
+ def0367ter[i].value);
+
+ switch (state->config->xtal) {
+ /*set internal freq to 53.125MHz */
+ case 25000000:
+ stv0367_writereg(state, R367TER_PLLMDIV, 0xa);
+ stv0367_writereg(state, R367TER_PLLNDIV, 0x55);
+ stv0367_writereg(state, R367TER_PLLSETUP, 0x18);
+ break;
+ default:
+ case 27000000:
+ dprintk("FE_STV0367TER_SetCLKgen for 27Mhz\n");
+ stv0367_writereg(state, R367TER_PLLMDIV, 0x1);
+ stv0367_writereg(state, R367TER_PLLNDIV, 0x8);
+ stv0367_writereg(state, R367TER_PLLSETUP, 0x18);
+ break;
+ case 30000000:
+ stv0367_writereg(state, R367TER_PLLMDIV, 0xc);
+ stv0367_writereg(state, R367TER_PLLNDIV, 0x55);
+ stv0367_writereg(state, R367TER_PLLSETUP, 0x18);
+ break;
+ }
+
+ stv0367_writereg(state, R367TER_I2CRPT, 0xa0);
+ stv0367_writereg(state, R367TER_ANACTRL, 0x00);
+
+ /*Set TS1 and TS2 to serial or parallel mode */
+ stv0367ter_set_ts_mode(state, state->config->ts_mode);
+ stv0367ter_set_clk_pol(state, state->config->clk_pol);
+
+ state->chip_id = stv0367_readreg(state, R367TER_ID);
+ ter_state->first_lock = 0;
+ ter_state->unlock_counter = 2;
+
+ return 0;
+}
+
+static int stv0367ter_algo(struct dvb_frontend *fe,
+ struct dvb_frontend_parameters *param)
+{
+ struct stv0367_state *state = fe->demodulator_priv;
+ struct stv0367ter_state *ter_state = state->ter_state;
+ int offset = 0, tempo = 0;
+ u8 u_var;
+ u8 /*constell,*/ counter, tps_rcvd[2];
+ s8 step;
+ s32 timing_offset = 0;
+ u32 trl_nomrate = 0, InternalFreq = 0, temp = 0;
+
+ dprintk("%s:\n", __func__);
+
+ ter_state->frequency = param->frequency;
+ ter_state->force = FE_TER_FORCENONE
+ + stv0367_readbits(state, F367TER_FORCE) * 2;
+ ter_state->if_iq_mode = state->config->if_iq_mode;
+ switch (state->config->if_iq_mode) {
+ case FE_TER_NORMAL_IF_TUNER: /* Normal IF mode */
+ dprintk("ALGO: FE_TER_NORMAL_IF_TUNER selected\n");
+ stv0367_writebits(state, F367TER_TUNER_BB, 0);
+ stv0367_writebits(state, F367TER_LONGPATH_IF, 0);
+ stv0367_writebits(state, F367TER_DEMUX_SWAP, 0);
+ break;
+ case FE_TER_LONGPATH_IF_TUNER: /* Long IF mode */
+ dprintk("ALGO: FE_TER_LONGPATH_IF_TUNER selected\n");
+ stv0367_writebits(state, F367TER_TUNER_BB, 0);
+ stv0367_writebits(state, F367TER_LONGPATH_IF, 1);
+ stv0367_writebits(state, F367TER_DEMUX_SWAP, 1);
+ break;
+ case FE_TER_IQ_TUNER: /* IQ mode */
+ dprintk("ALGO: FE_TER_IQ_TUNER selected\n");
+ stv0367_writebits(state, F367TER_TUNER_BB, 1);
+ stv0367_writebits(state, F367TER_PPM_INVSEL, 0);
+ break;
+ default:
+ printk(KERN_ERR "ALGO: wrong TUNER type selected\n");
+ return -EINVAL;
+ }
+
+ usleep_range(5000, 7000);
+
+ switch (param->inversion) {
+ case INVERSION_AUTO:
+ default:
+ dprintk("%s: inversion AUTO\n", __func__);
+ if (ter_state->if_iq_mode == FE_TER_IQ_TUNER)
+ stv0367_writebits(state, F367TER_IQ_INVERT,
+ ter_state->sense);
+ else
+ stv0367_writebits(state, F367TER_INV_SPECTR,
+ ter_state->sense);
+
+ break;
+ case INVERSION_ON:
+ case INVERSION_OFF:
+ if (ter_state->if_iq_mode == FE_TER_IQ_TUNER)
+ stv0367_writebits(state, F367TER_IQ_INVERT,
+ param->inversion);
+ else
+ stv0367_writebits(state, F367TER_INV_SPECTR,
+ param->inversion);
+
+ break;
+ }
+
+ if ((ter_state->if_iq_mode != FE_TER_NORMAL_IF_TUNER) &&
+ (ter_state->pBW != ter_state->bw)) {
+ stv0367ter_agc_iir_lock_detect_set(state);
+
+ /*set fine agc target to 180 for LPIF or IQ mode*/
+ /* set Q_AGCTarget */
+ stv0367_writebits(state, F367TER_SEL_IQNTAR, 1);
+ stv0367_writebits(state, F367TER_AUT_AGC_TARGET_MSB, 0xB);
+ /*stv0367_writebits(state,AUT_AGC_TARGET_LSB,0x04); */
+
+ /* set Q_AGCTarget */
+ stv0367_writebits(state, F367TER_SEL_IQNTAR, 0);
+ stv0367_writebits(state, F367TER_AUT_AGC_TARGET_MSB, 0xB);
+ /*stv0367_writebits(state,AUT_AGC_TARGET_LSB,0x04); */
+
+ if (!stv0367_iir_filt_init(state, ter_state->bw,
+ state->config->xtal))
+ return -EINVAL;
+ /*set IIR filter once for 6,7 or 8MHz BW*/
+ ter_state->pBW = ter_state->bw;
+
+ stv0367ter_agc_iir_rst(state);
+ }
+
+ if (ter_state->hierarchy == FE_TER_HIER_LOW_PRIO)
+ stv0367_writebits(state, F367TER_BDI_LPSEL, 0x01);
+ else
+ stv0367_writebits(state, F367TER_BDI_LPSEL, 0x00);
+
+ InternalFreq = stv0367ter_get_mclk(state, state->config->xtal) / 1000;
+ temp = (int)
+ ((((ter_state->bw * 64 * (1 << 15) * 100)
+ / (InternalFreq)) * 10) / 7);
+
+ stv0367_writebits(state, F367TER_TRL_NOMRATE_LSB, temp % 2);
+ temp = temp / 2;
+ stv0367_writebits(state, F367TER_TRL_NOMRATE_HI, temp / 256);
+ stv0367_writebits(state, F367TER_TRL_NOMRATE_LO, temp % 256);
+
+ temp = stv0367_readbits(state, F367TER_TRL_NOMRATE_HI) * 512 +
+ stv0367_readbits(state, F367TER_TRL_NOMRATE_LO) * 2 +
+ stv0367_readbits(state, F367TER_TRL_NOMRATE_LSB);
+ temp = (int)(((1 << 17) * ter_state->bw * 1000) / (7 * (InternalFreq)));
+ stv0367_writebits(state, F367TER_GAIN_SRC_HI, temp / 256);
+ stv0367_writebits(state, F367TER_GAIN_SRC_LO, temp % 256);
+ temp = stv0367_readbits(state, F367TER_GAIN_SRC_HI) * 256 +
+ stv0367_readbits(state, F367TER_GAIN_SRC_LO);
+
+ temp = (int)
+ ((InternalFreq - state->config->if_khz) * (1 << 16)
+ / (InternalFreq));
+
+ dprintk("DEROT temp=0x%x\n", temp);
+ stv0367_writebits(state, F367TER_INC_DEROT_HI, temp / 256);
+ stv0367_writebits(state, F367TER_INC_DEROT_LO, temp % 256);
+
+ ter_state->echo_pos = 0;
+ ter_state->ucblocks = 0; /* liplianin */
+ ter_state->pBER = 0; /* liplianin */
+ stv0367_writebits(state, F367TER_LONG_ECHO, ter_state->echo_pos);
+
+ if (stv0367ter_lock_algo(state) != FE_TER_LOCKOK)
+ return 0;
+
+ ter_state->state = FE_TER_LOCKOK;
+ /* update results */
+ tps_rcvd[0] = stv0367_readreg(state, R367TER_TPS_RCVD2);
+ tps_rcvd[1] = stv0367_readreg(state, R367TER_TPS_RCVD3);
+
+ ter_state->mode = stv0367_readbits(state, F367TER_SYR_MODE);
+ ter_state->guard = stv0367_readbits(state, F367TER_SYR_GUARD);
+
+ ter_state->first_lock = 1; /* we know sense now :) */
+
+ ter_state->agc_val =
+ (stv0367_readbits(state, F367TER_AGC1_VAL_LO) << 16) +
+ (stv0367_readbits(state, F367TER_AGC1_VAL_HI) << 24) +
+ stv0367_readbits(state, F367TER_AGC2_VAL_LO) +
+ (stv0367_readbits(state, F367TER_AGC2_VAL_HI) << 8);
+
+ /* Carrier offset calculation */
+ stv0367_writebits(state, F367TER_FREEZE, 1);
+ offset = (stv0367_readbits(state, F367TER_CRL_FOFFSET_VHI) << 16) ;
+ offset += (stv0367_readbits(state, F367TER_CRL_FOFFSET_HI) << 8);
+ offset += (stv0367_readbits(state, F367TER_CRL_FOFFSET_LO));
+ stv0367_writebits(state, F367TER_FREEZE, 0);
+ if (offset > 8388607)
+ offset -= 16777216;
+
+ offset = offset * 2 / 16384;
+
+ if (ter_state->mode == FE_TER_MODE_2K)
+ offset = (offset * 4464) / 1000;/*** 1 FFT BIN=4.464khz***/
+ else if (ter_state->mode == FE_TER_MODE_4K)
+ offset = (offset * 223) / 100;/*** 1 FFT BIN=2.23khz***/
+ else if (ter_state->mode == FE_TER_MODE_8K)
+ offset = (offset * 111) / 100;/*** 1 FFT BIN=1.1khz***/
+
+ if (stv0367_readbits(state, F367TER_PPM_INVSEL) == 1) {
+ if ((stv0367_readbits(state, F367TER_INV_SPECTR) ==
+ (stv0367_readbits(state,
+ F367TER_STATUS_INV_SPECRUM) == 1)))
+ offset = offset * -1;
+ }
+
+ if (ter_state->bw == 6)
+ offset = (offset * 6) / 8;
+ else if (ter_state->bw == 7)
+ offset = (offset * 7) / 8;
+
+ ter_state->frequency += offset;
+
+ tempo = 10; /* exit even if timing_offset stays null */
+ while ((timing_offset == 0) && (tempo > 0)) {
+ usleep_range(10000, 20000); /*was 20ms */
+ /* fine tuning of timing offset if required */
+ timing_offset = stv0367_readbits(state, F367TER_TRL_TOFFSET_LO)
+ + 256 * stv0367_readbits(state,
+ F367TER_TRL_TOFFSET_HI);
+ if (timing_offset >= 32768)
+ timing_offset -= 65536;
+ trl_nomrate = (512 * stv0367_readbits(state,
+ F367TER_TRL_NOMRATE_HI)
+ + stv0367_readbits(state, F367TER_TRL_NOMRATE_LO) * 2
+ + stv0367_readbits(state, F367TER_TRL_NOMRATE_LSB));
+
+ timing_offset = ((signed)(1000000 / trl_nomrate) *
+ timing_offset) / 2048;
+ tempo--;
+ }
+
+ if (timing_offset <= 0) {
+ timing_offset = (timing_offset - 11) / 22;
+ step = -1;
+ } else {
+ timing_offset = (timing_offset + 11) / 22;
+ step = 1;
+ }
+
+ for (counter = 0; counter < abs(timing_offset); counter++) {
+ trl_nomrate += step;
+ stv0367_writebits(state, F367TER_TRL_NOMRATE_LSB,
+ trl_nomrate % 2);
+ stv0367_writebits(state, F367TER_TRL_NOMRATE_LO,
+ trl_nomrate / 2);
+ usleep_range(1000, 2000);
+ }
+
+ usleep_range(5000, 6000);
+ /* unlocks could happen in case of trl centring big step,
+ then a core off/on restarts demod */
+ u_var = stv0367_readbits(state, F367TER_LK);
+
+ if (!u_var) {
+ stv0367_writebits(state, F367TER_CORE_ACTIVE, 0);
+ msleep(20);
+ stv0367_writebits(state, F367TER_CORE_ACTIVE, 1);
+ }
+
+ return 0;
+}
+
+static int stv0367ter_set_frontend(struct dvb_frontend *fe,
+ struct dvb_frontend_parameters *param)
+{
+ struct dvb_ofdm_parameters *op = &param->u.ofdm;
+ struct stv0367_state *state = fe->demodulator_priv;
+ struct stv0367ter_state *ter_state = state->ter_state;
+
+ /*u8 trials[2]; */
+ s8 num_trials, index;
+ u8 SenseTrials[] = { INVERSION_ON, INVERSION_OFF };
+
+ stv0367ter_init(fe);
+
+ if (fe->ops.tuner_ops.set_params) {
+ if (fe->ops.i2c_gate_ctrl)
+ fe->ops.i2c_gate_ctrl(fe, 1);
+ fe->ops.tuner_ops.set_params(fe, param);
+ if (fe->ops.i2c_gate_ctrl)
+ fe->ops.i2c_gate_ctrl(fe, 0);
+ }
+
+ switch (op->transmission_mode) {
+ default:
+ case TRANSMISSION_MODE_AUTO:
+ case TRANSMISSION_MODE_2K:
+ ter_state->mode = FE_TER_MODE_2K;
+ break;
+/* case TRANSMISSION_MODE_4K:
+ pLook.mode = FE_TER_MODE_4K;
+ break;*/
+ case TRANSMISSION_MODE_8K:
+ ter_state->mode = FE_TER_MODE_8K;
+ break;
+ }
+
+ switch (op->guard_interval) {
+ default:
+ case GUARD_INTERVAL_1_32:
+ case GUARD_INTERVAL_1_16:
+ case GUARD_INTERVAL_1_8:
+ case GUARD_INTERVAL_1_4:
+ ter_state->guard = op->guard_interval;
+ break;
+ case GUARD_INTERVAL_AUTO:
+ ter_state->guard = GUARD_INTERVAL_1_32;
+ break;
+ }
+
+ switch (op->bandwidth) {
+ case BANDWIDTH_6_MHZ:
+ ter_state->bw = FE_TER_CHAN_BW_6M;
+ break;
+ case BANDWIDTH_7_MHZ:
+ ter_state->bw = FE_TER_CHAN_BW_7M;
+ break;
+ case BANDWIDTH_8_MHZ:
+ default:
+ ter_state->bw = FE_TER_CHAN_BW_8M;
+ }
+
+ ter_state->hierarchy = FE_TER_HIER_NONE;
+
+ switch (param->inversion) {
+ case INVERSION_OFF:
+ case INVERSION_ON:
+ num_trials = 1;
+ break;
+ default:
+ num_trials = 2;
+ if (ter_state->first_lock)
+ num_trials = 1;
+ break;
+ }
+
+ ter_state->state = FE_TER_NOLOCK;
+ index = 0;
+
+ while (((index) < num_trials) && (ter_state->state != FE_TER_LOCKOK)) {
+ if (!ter_state->first_lock) {
+ if (param->inversion == INVERSION_AUTO)
+ ter_state->sense = SenseTrials[index];
+
+ }
+ stv0367ter_algo(fe,/* &pLook, result,*/ param);
+
+ if ((ter_state->state == FE_TER_LOCKOK) &&
+ (param->inversion == INVERSION_AUTO) &&
+ (index == 1)) {
+ /* invert spectrum sense */
+ SenseTrials[index] = SenseTrials[0];
+ SenseTrials[(index + 1) % 2] = (SenseTrials[1] + 1) % 2;
+ }
+
+ index++;
+ }
+
+ return 0;
+}
+
+static int stv0367ter_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
+{
+ struct stv0367_state *state = fe->demodulator_priv;
+ struct stv0367ter_state *ter_state = state->ter_state;
+ u32 errs = 0;
+
+ /*wait for counting completion*/
+ if (stv0367_readbits(state, F367TER_SFERRC_OLDVALUE) == 0) {
+ errs =
+ ((u32)stv0367_readbits(state, F367TER_ERR_CNT1)
+ * (1 << 16))
+ + ((u32)stv0367_readbits(state, F367TER_ERR_CNT1_HI)
+ * (1 << 8))
+ + ((u32)stv0367_readbits(state, F367TER_ERR_CNT1_LO));
+ ter_state->ucblocks = errs;
+ }
+
+ (*ucblocks) = ter_state->ucblocks;
+
+ return 0;
+}
+
+static int stv0367ter_get_frontend(struct dvb_frontend *fe,
+ struct dvb_frontend_parameters *param)
+{
+ struct stv0367_state *state = fe->demodulator_priv;
+ struct stv0367ter_state *ter_state = state->ter_state;
+ struct dvb_ofdm_parameters *op = &param->u.ofdm;
+ struct dtv_frontend_properties *c = &fe->dtv_property_cache;
+
+ int error = 0;
+ enum stv0367_ter_mode mode;
+ int constell = 0,/* snr = 0,*/ Data = 0;
+
+ param->frequency = stv0367_get_tuner_freq(fe);
+ if ((int)param->frequency < 0)
+ param->frequency = c->frequency;
+
+ constell = stv0367_readbits(state, F367TER_TPS_CONST);
+ if (constell == 0)
+ op->constellation = QPSK;
+ else if (constell == 1)
+ op->constellation = QAM_16;
+ else
+ op->constellation = QAM_64;
+
+ param->inversion = stv0367_readbits(state, F367TER_INV_SPECTR);
+
+ /* Get the Hierarchical mode */
+ Data = stv0367_readbits(state, F367TER_TPS_HIERMODE);
+
+ switch (Data) {
+ case 0:
+ op->hierarchy_information = HIERARCHY_NONE;
+ break;
+ case 1:
+ op->hierarchy_information = HIERARCHY_1;
+ break;
+ case 2:
+ op->hierarchy_information = HIERARCHY_2;
+ break;
+ case 3:
+ op->hierarchy_information = HIERARCHY_4;
+ break;
+ default:
+ op->hierarchy_information = HIERARCHY_AUTO;
+ break; /* error */
+ }
+
+ /* Get the FEC Rate */
+ if (ter_state->hierarchy == FE_TER_HIER_LOW_PRIO)
+ Data = stv0367_readbits(state, F367TER_TPS_LPCODE);
+ else
+ Data = stv0367_readbits(state, F367TER_TPS_HPCODE);
+
+ switch (Data) {
+ case 0:
+ op->code_rate_HP = FEC_1_2;
+ break;
+ case 1:
+ op->code_rate_HP = FEC_2_3;
+ break;
+ case 2:
+ op->code_rate_HP = FEC_3_4;
+ break;
+ case 3:
+ op->code_rate_HP = FEC_5_6;
+ break;
+ case 4:
+ op->code_rate_HP = FEC_7_8;
+ break;
+ default:
+ op->code_rate_HP = FEC_AUTO;
+ break; /* error */
+ }
+
+ mode = stv0367_readbits(state, F367TER_SYR_MODE);
+
+ switch (mode) {
+ case FE_TER_MODE_2K:
+ op->transmission_mode = TRANSMISSION_MODE_2K;
+ break;
+/* case FE_TER_MODE_4K:
+ op->transmission_mode = TRANSMISSION_MODE_4K;
+ break;*/
+ case FE_TER_MODE_8K:
+ op->transmission_mode = TRANSMISSION_MODE_8K;
+ break;
+ default:
+ op->transmission_mode = TRANSMISSION_MODE_AUTO;
+ }
+
+ op->guard_interval = stv0367_readbits(state, F367TER_SYR_GUARD);
+
+ return error;
+}
+
+static int stv0367ter_read_snr(struct dvb_frontend *fe, u16 *snr)
+{
+ struct stv0367_state *state = fe->demodulator_priv;
+ u32 snru32 = 0;
+ int cpt = 0;
+ u8 cut = stv0367_readbits(state, F367TER_IDENTIFICATIONREG);
+
+ while (cpt < 10) {
+ usleep_range(2000, 3000);
+ if (cut == 0x50) /*cut 1.0 cut 1.1*/
+ snru32 += stv0367_readbits(state, F367TER_CHCSNR) / 4;
+ else /*cu2.0*/
+ snru32 += 125 * stv0367_readbits(state, F367TER_CHCSNR);
+
+ cpt++;
+ }
+
+ snru32 /= 10;/*average on 10 values*/
+
+ *snr = snru32 / 1000;
+
+ return 0;
+}
+
+#if 0
+static int stv0367ter_status(struct dvb_frontend *fe)
+{
+
+ struct stv0367_state *state = fe->demodulator_priv;
+ struct stv0367ter_state *ter_state = state->ter_state;
+ int locked = FALSE;
+
+ locked = (stv0367_readbits(state, F367TER_LK));
+ if (!locked)
+ ter_state->unlock_counter += 1;
+ else
+ ter_state->unlock_counter = 0;
+
+ if (ter_state->unlock_counter > 2) {
+ if (!stv0367_readbits(state, F367TER_TPS_LOCK) ||
+ (!stv0367_readbits(state, F367TER_LK))) {
+ stv0367_writebits(state, F367TER_CORE_ACTIVE, 0);
+ usleep_range(2000, 3000);
+ stv0367_writebits(state, F367TER_CORE_ACTIVE, 1);
+ msleep(350);
+ locked = (stv0367_readbits(state, F367TER_TPS_LOCK)) &&
+ (stv0367_readbits(state, F367TER_LK));
+ }
+
+ }
+
+ return locked;
+}
+#endif
+static int stv0367ter_read_status(struct dvb_frontend *fe, fe_status_t *status)
+{
+ struct stv0367_state *state = fe->demodulator_priv;
+
+ dprintk("%s:\n", __func__);
+
+ *status = 0;
+
+ if (stv0367_readbits(state, F367TER_LK)) {
+ *status |= FE_HAS_LOCK;
+ dprintk("%s: stv0367 has locked\n", __func__);
+ }
+
+ return 0;
+}
+
+static int stv0367ter_read_ber(struct dvb_frontend *fe, u32 *ber)
+{
+ struct stv0367_state *state = fe->demodulator_priv;
+ struct stv0367ter_state *ter_state = state->ter_state;
+ u32 Errors = 0, tber = 0, temporary = 0;
+ int abc = 0, def = 0;
+
+
+ /*wait for counting completion*/
+ if (stv0367_readbits(state, F367TER_SFERRC_OLDVALUE) == 0)
+ Errors = ((u32)stv0367_readbits(state, F367TER_SFEC_ERR_CNT)
+ * (1 << 16))
+ + ((u32)stv0367_readbits(state, F367TER_SFEC_ERR_CNT_HI)
+ * (1 << 8))
+ + ((u32)stv0367_readbits(state,
+ F367TER_SFEC_ERR_CNT_LO));
+ /*measurement not completed, load previous value*/
+ else {
+ tber = ter_state->pBER;
+ return 0;
+ }
+
+ abc = stv0367_readbits(state, F367TER_SFEC_ERR_SOURCE);
+ def = stv0367_readbits(state, F367TER_SFEC_NUM_EVENT);
+
+ if (Errors == 0) {
+ tber = 0;
+ } else if (abc == 0x7) {
+ if (Errors <= 4) {
+ temporary = (Errors * 1000000000) / (8 * (1 << 14));
+ temporary = temporary;
+ } else if (Errors <= 42) {
+ temporary = (Errors * 100000000) / (8 * (1 << 14));
+ temporary = temporary * 10;
+ } else if (Errors <= 429) {
+ temporary = (Errors * 10000000) / (8 * (1 << 14));
+ temporary = temporary * 100;
+ } else if (Errors <= 4294) {
+ temporary = (Errors * 1000000) / (8 * (1 << 14));
+ temporary = temporary * 1000;
+ } else if (Errors <= 42949) {
+ temporary = (Errors * 100000) / (8 * (1 << 14));
+ temporary = temporary * 10000;
+ } else if (Errors <= 429496) {
+ temporary = (Errors * 10000) / (8 * (1 << 14));
+ temporary = temporary * 100000;
+ } else { /*if (Errors<4294967) 2^22 max error*/
+ temporary = (Errors * 1000) / (8 * (1 << 14));
+ temporary = temporary * 100000; /* still to *10 */
+ }
+
+ /* Byte error*/
+ if (def == 2)
+ /*tber=Errors/(8*(1 <<14));*/
+ tber = temporary;
+ else if (def == 3)
+ /*tber=Errors/(8*(1 <<16));*/
+ tber = temporary / 4;
+ else if (def == 4)
+ /*tber=Errors/(8*(1 <<18));*/
+ tber = temporary / 16;
+ else if (def == 5)
+ /*tber=Errors/(8*(1 <<20));*/
+ tber = temporary / 64;
+ else if (def == 6)
+ /*tber=Errors/(8*(1 <<22));*/
+ tber = temporary / 256;
+ else
+ /* should not pass here*/
+ tber = 0;
+
+ if ((Errors < 4294967) && (Errors > 429496))
+ tber *= 10;
+
+ }
+
+ /* save actual value */
+ ter_state->pBER = tber;
+
+ (*ber) = tber;
+
+ return 0;
+}
+#if 0
+static u32 stv0367ter_get_per(struct stv0367_state *state)
+{
+ struct stv0367ter_state *ter_state = state->ter_state;
+ u32 Errors = 0, Per = 0, temporary = 0;
+ int abc = 0, def = 0, cpt = 0;
+
+ while (((stv0367_readbits(state, F367TER_SFERRC_OLDVALUE) == 1) &&
+ (cpt < 400)) || ((Errors == 0) && (cpt < 400))) {
+ usleep_range(1000, 2000);
+ Errors = ((u32)stv0367_readbits(state, F367TER_ERR_CNT1)
+ * (1 << 16))
+ + ((u32)stv0367_readbits(state, F367TER_ERR_CNT1_HI)
+ * (1 << 8))
+ + ((u32)stv0367_readbits(state, F367TER_ERR_CNT1_LO));
+ cpt++;
+ }
+ abc = stv0367_readbits(state, F367TER_ERR_SRC1);
+ def = stv0367_readbits(state, F367TER_NUM_EVT1);
+
+ if (Errors == 0)
+ Per = 0;
+ else if (abc == 0x9) {
+ if (Errors <= 4) {
+ temporary = (Errors * 1000000000) / (8 * (1 << 8));
+ temporary = temporary;
+ } else if (Errors <= 42) {
+ temporary = (Errors * 100000000) / (8 * (1 << 8));
+ temporary = temporary * 10;
+ } else if (Errors <= 429) {
+ temporary = (Errors * 10000000) / (8 * (1 << 8));
+ temporary = temporary * 100;
+ } else if (Errors <= 4294) {
+ temporary = (Errors * 1000000) / (8 * (1 << 8));
+ temporary = temporary * 1000;
+ } else if (Errors <= 42949) {
+ temporary = (Errors * 100000) / (8 * (1 << 8));
+ temporary = temporary * 10000;
+ } else { /*if(Errors<=429496) 2^16 errors max*/
+ temporary = (Errors * 10000) / (8 * (1 << 8));
+ temporary = temporary * 100000;
+ }
+
+ /* pkt error*/
+ if (def == 2)
+ /*Per=Errors/(1 << 8);*/
+ Per = temporary;
+ else if (def == 3)
+ /*Per=Errors/(1 << 10);*/
+ Per = temporary / 4;
+ else if (def == 4)
+ /*Per=Errors/(1 << 12);*/
+ Per = temporary / 16;
+ else if (def == 5)
+ /*Per=Errors/(1 << 14);*/
+ Per = temporary / 64;
+ else if (def == 6)
+ /*Per=Errors/(1 << 16);*/
+ Per = temporary / 256;
+ else
+ Per = 0;
+
+ }
+ /* save actual value */
+ ter_state->pPER = Per;
+
+ return Per;
+}
+#endif
+static int stv0367_get_tune_settings(struct dvb_frontend *fe,
+ struct dvb_frontend_tune_settings
+ *fe_tune_settings)
+{
+ fe_tune_settings->min_delay_ms = 1000;
+ fe_tune_settings->step_size = 0;
+ fe_tune_settings->max_drift = 0;
+
+ return 0;
+}
+
+static void stv0367_release(struct dvb_frontend *fe)
+{
+ struct stv0367_state *state = fe->demodulator_priv;
+
+ kfree(state->ter_state);
+ kfree(state->cab_state);
+ kfree(state);
+}
+
+static struct dvb_frontend_ops stv0367ter_ops = {
+ .info = {
+ .name = "ST STV0367 DVB-T",
+ .type = FE_OFDM,
+ .frequency_min = 47000000,
+ .frequency_max = 862000000,
+ .frequency_stepsize = 15625,
+ .frequency_tolerance = 0,
+ .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 |
+ FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 |
+ FE_CAN_FEC_AUTO |
+ FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 |
+ FE_CAN_QAM_128 | FE_CAN_QAM_256 | FE_CAN_QAM_AUTO |
+ FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_RECOVER |
+ FE_CAN_INVERSION_AUTO |
+ FE_CAN_MUTE_TS
+ },
+ .release = stv0367_release,
+ .init = stv0367ter_init,
+ .sleep = stv0367ter_sleep,
+ .i2c_gate_ctrl = stv0367ter_gate_ctrl,
+ .set_frontend = stv0367ter_set_frontend,
+ .get_frontend = stv0367ter_get_frontend,
+ .get_tune_settings = stv0367_get_tune_settings,
+ .read_status = stv0367ter_read_status,
+ .read_ber = stv0367ter_read_ber,/* too slow */
+/* .read_signal_strength = stv0367_read_signal_strength,*/
+ .read_snr = stv0367ter_read_snr,
+ .read_ucblocks = stv0367ter_read_ucblocks,
+};
+
+struct dvb_frontend *stv0367ter_attach(const struct stv0367_config *config,
+ struct i2c_adapter *i2c)
+{
+ struct stv0367_state *state = NULL;
+ struct stv0367ter_state *ter_state = NULL;
+
+ /* allocate memory for the internal state */
+ state = kzalloc(sizeof(struct stv0367_state), GFP_KERNEL);
+ if (state == NULL)
+ goto error;
+ ter_state = kzalloc(sizeof(struct stv0367ter_state), GFP_KERNEL);
+ if (ter_state == NULL)
+ goto error;
+
+ /* setup the state */
+ state->i2c = i2c;
+ state->config = config;
+ state->ter_state = ter_state;
+ state->fe.ops = stv0367ter_ops;
+ state->fe.demodulator_priv = state;
+ state->chip_id = stv0367_readreg(state, 0xf000);
+
+ dprintk("%s: chip_id = 0x%x\n", __func__, state->chip_id);
+
+ /* check if the demod is there */
+ if ((state->chip_id != 0x50) && (state->chip_id != 0x60))
+ goto error;
+
+ return &state->fe;
+
+error:
+ kfree(ter_state);
+ kfree(state);
+ return NULL;
+}
+EXPORT_SYMBOL(stv0367ter_attach);
+
+static int stv0367cab_gate_ctrl(struct dvb_frontend *fe, int enable)
+{
+ struct stv0367_state *state = fe->demodulator_priv;
+
+ dprintk("%s:\n", __func__);
+
+ stv0367_writebits(state, F367CAB_I2CT_ON, (enable > 0) ? 1 : 0);
+
+ return 0;
+}
+
+static u32 stv0367cab_get_mclk(struct dvb_frontend *fe, u32 ExtClk_Hz)
+{
+ struct stv0367_state *state = fe->demodulator_priv;
+ u32 mclk_Hz = 0;/* master clock frequency (Hz) */
+ u32 M, N, P;
+
+
+ if (stv0367_readbits(state, F367CAB_BYPASS_PLLXN) == 0) {
+ N = (u32)stv0367_readbits(state, F367CAB_PLL_NDIV);
+ if (N == 0)
+ N = N + 1;
+
+ M = (u32)stv0367_readbits(state, F367CAB_PLL_MDIV);
+ if (M == 0)
+ M = M + 1;
+
+ P = (u32)stv0367_readbits(state, F367CAB_PLL_PDIV);
+
+ if (P > 5)
+ P = 5;
+
+ mclk_Hz = ((ExtClk_Hz / 2) * N) / (M * (1 << P));
+ dprintk("stv0367cab_get_mclk BYPASS_PLLXN mclk_Hz=%d\n",
+ mclk_Hz);
+ } else
+ mclk_Hz = ExtClk_Hz;
+
+ dprintk("stv0367cab_get_mclk final mclk_Hz=%d\n", mclk_Hz);
+
+ return mclk_Hz;
+}
+
+static u32 stv0367cab_get_adc_freq(struct dvb_frontend *fe, u32 ExtClk_Hz)
+{
+ u32 ADCClk_Hz = ExtClk_Hz;
+
+ ADCClk_Hz = stv0367cab_get_mclk(fe, ExtClk_Hz);
+
+ return ADCClk_Hz;
+}
+
+enum stv0367cab_mod stv0367cab_SetQamSize(struct stv0367_state *state,
+ u32 SymbolRate,
+ enum stv0367cab_mod QAMSize)
+{
+ /* Set QAM size */
+ stv0367_writebits(state, F367CAB_QAM_MODE, QAMSize);
+
+ /* Set Registers settings specific to the QAM size */
+ switch (QAMSize) {
+ case FE_CAB_MOD_QAM4:
+ stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00);
+ break;
+ case FE_CAB_MOD_QAM16:
+ stv0367_writereg(state, R367CAB_AGC_PWR_REF_L, 0x64);
+ stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00);
+ stv0367_writereg(state, R367CAB_FSM_STATE, 0x90);
+ stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1);
+ stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa7);
+ stv0367_writereg(state, R367CAB_EQU_CRL_LD_SEN, 0x95);
+ stv0367_writereg(state, R367CAB_EQU_CRL_LIMITER, 0x40);
+ stv0367_writereg(state, R367CAB_EQU_PNT_GAIN, 0x8a);
+ break;
+ case FE_CAB_MOD_QAM32:
+ stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00);
+ stv0367_writereg(state, R367CAB_AGC_PWR_REF_L, 0x6e);
+ stv0367_writereg(state, R367CAB_FSM_STATE, 0xb0);
+ stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1);
+ stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xb7);
+ stv0367_writereg(state, R367CAB_EQU_CRL_LD_SEN, 0x9d);
+ stv0367_writereg(state, R367CAB_EQU_CRL_LIMITER, 0x7f);
+ stv0367_writereg(state, R367CAB_EQU_PNT_GAIN, 0xa7);
+ break;
+ case FE_CAB_MOD_QAM64:
+ stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x82);
+ stv0367_writereg(state, R367CAB_AGC_PWR_REF_L, 0x5a);
+ if (SymbolRate > 45000000) {
+ stv0367_writereg(state, R367CAB_FSM_STATE, 0xb0);
+ stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1);
+ stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa5);
+ } else if (SymbolRate > 25000000) {
+ stv0367_writereg(state, R367CAB_FSM_STATE, 0xa0);
+ stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1);
+ stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa6);
+ } else {
+ stv0367_writereg(state, R367CAB_FSM_STATE, 0xa0);
+ stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xd1);
+ stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa7);
+ }
+ stv0367_writereg(state, R367CAB_EQU_CRL_LD_SEN, 0x95);
+ stv0367_writereg(state, R367CAB_EQU_CRL_LIMITER, 0x40);
+ stv0367_writereg(state, R367CAB_EQU_PNT_GAIN, 0x99);
+ break;
+ case FE_CAB_MOD_QAM128:
+ stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00);
+ stv0367_writereg(state, R367CAB_AGC_PWR_REF_L, 0x76);
+ stv0367_writereg(state, R367CAB_FSM_STATE, 0x90);
+ stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xb1);
+ if (SymbolRate > 45000000)
+ stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa7);
+ else if (SymbolRate > 25000000)
+ stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa6);
+ else
+ stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0x97);
+
+ stv0367_writereg(state, R367CAB_EQU_CRL_LD_SEN, 0x8e);
+ stv0367_writereg(state, R367CAB_EQU_CRL_LIMITER, 0x7f);
+ stv0367_writereg(state, R367CAB_EQU_PNT_GAIN, 0xa7);
+ break;
+ case FE_CAB_MOD_QAM256:
+ stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x94);
+ stv0367_writereg(state, R367CAB_AGC_PWR_REF_L, 0x5a);
+ stv0367_writereg(state, R367CAB_FSM_STATE, 0xa0);
+ if (SymbolRate > 45000000)
+ stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1);
+ else if (SymbolRate > 25000000)
+ stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1);
+ else
+ stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xd1);
+
+ stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa7);
+ stv0367_writereg(state, R367CAB_EQU_CRL_LD_SEN, 0x85);
+ stv0367_writereg(state, R367CAB_EQU_CRL_LIMITER, 0x40);
+ stv0367_writereg(state, R367CAB_EQU_PNT_GAIN, 0xa7);
+ break;
+ case FE_CAB_MOD_QAM512:
+ stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00);
+ break;
+ case FE_CAB_MOD_QAM1024:
+ stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00);
+ break;
+ default:
+ break;
+ }
+
+ return QAMSize;
+}
+
+static u32 stv0367cab_set_derot_freq(struct stv0367_state *state,
+ u32 adc_hz, s32 derot_hz)
+{
+ u32 sampled_if = 0;
+ u32 adc_khz;
+
+ adc_khz = adc_hz / 1000;
+
+ dprintk("%s: adc_hz=%d derot_hz=%d\n", __func__, adc_hz, derot_hz);
+
+ if (adc_khz != 0) {
+ if (derot_hz < 1000000)
+ derot_hz = adc_hz / 4; /* ZIF operation */
+ if (derot_hz > adc_hz)
+ derot_hz = derot_hz - adc_hz;
+ sampled_if = (u32)derot_hz / 1000;
+ sampled_if *= 32768;
+ sampled_if /= adc_khz;
+ sampled_if *= 256;
+ }
+
+ if (sampled_if > 8388607)
+ sampled_if = 8388607;
+
+ dprintk("%s: sampled_if=0x%x\n", __func__, sampled_if);
+
+ stv0367_writereg(state, R367CAB_MIX_NCO_LL, sampled_if);
+ stv0367_writereg(state, R367CAB_MIX_NCO_HL, (sampled_if >> 8));
+ stv0367_writebits(state, F367CAB_MIX_NCO_INC_HH, (sampled_if >> 16));
+
+ return derot_hz;
+}
+
+static u32 stv0367cab_get_derot_freq(struct stv0367_state *state, u32 adc_hz)
+{
+ u32 sampled_if;
+
+ sampled_if = stv0367_readbits(state, F367CAB_MIX_NCO_INC_LL) +
+ (stv0367_readbits(state, F367CAB_MIX_NCO_INC_HL) << 8) +
+ (stv0367_readbits(state, F367CAB_MIX_NCO_INC_HH) << 16);
+
+ sampled_if /= 256;
+ sampled_if *= (adc_hz / 1000);
+ sampled_if += 1;
+ sampled_if /= 32768;
+
+ return sampled_if;
+}
+
+static u32 stv0367cab_set_srate(struct stv0367_state *state, u32 adc_hz,
+ u32 mclk_hz, u32 SymbolRate,
+ enum stv0367cab_mod QAMSize)
+{
+ u32 QamSizeCorr = 0;
+ u32 u32_tmp = 0, u32_tmp1 = 0;
+ u32 adp_khz;
+
+ dprintk("%s:\n", __func__);
+
+ /* Set Correction factor of SRC gain */
+ switch (QAMSize) {
+ case FE_CAB_MOD_QAM4:
+ QamSizeCorr = 1110;
+ break;
+ case FE_CAB_MOD_QAM16:
+ QamSizeCorr = 1032;
+ break;
+ case FE_CAB_MOD_QAM32:
+ QamSizeCorr = 954;
+ break;
+ case FE_CAB_MOD_QAM64:
+ QamSizeCorr = 983;
+ break;
+ case FE_CAB_MOD_QAM128:
+ QamSizeCorr = 957;
+ break;
+ case FE_CAB_MOD_QAM256:
+ QamSizeCorr = 948;
+ break;
+ case FE_CAB_MOD_QAM512:
+ QamSizeCorr = 0;
+ break;
+ case FE_CAB_MOD_QAM1024:
+ QamSizeCorr = 944;
+ break;
+ default:
+ break;
+ }
+
+ /* Transfer ratio calculation */
+ if (adc_hz != 0) {
+ u32_tmp = 256 * SymbolRate;
+ u32_tmp = u32_tmp / adc_hz;
+ }
+ stv0367_writereg(state, R367CAB_EQU_CRL_TFR, (u8)u32_tmp);
+
+ /* Symbol rate and SRC gain calculation */
+ adp_khz = (mclk_hz >> 1) / 1000;/* TRL works at half the system clock */
+ if (adp_khz != 0) {
+ u32_tmp = SymbolRate;
+ u32_tmp1 = SymbolRate;
+
+ if (u32_tmp < 2097152) { /* 2097152 = 2^21 */
+ /* Symbol rate calculation */
+ u32_tmp *= 2048; /* 2048 = 2^11 */
+ u32_tmp = u32_tmp / adp_khz;
+ u32_tmp = u32_tmp * 16384; /* 16384 = 2^14 */
+ u32_tmp /= 125 ; /* 125 = 1000/2^3 */
+ u32_tmp = u32_tmp * 8; /* 8 = 2^3 */
+
+ /* SRC Gain Calculation */
+ u32_tmp1 *= 2048; /* *2*2^10 */
+ u32_tmp1 /= 439; /* *2/878 */
+ u32_tmp1 *= 256; /* *2^8 */
+ u32_tmp1 = u32_tmp1 / adp_khz; /* /(AdpClk in kHz) */
+ u32_tmp1 *= QamSizeCorr * 9; /* *1000*corr factor */
+ u32_tmp1 = u32_tmp1 / 10000000;
+
+ } else if (u32_tmp < 4194304) { /* 4194304 = 2**22 */
+ /* Symbol rate calculation */
+ u32_tmp *= 1024 ; /* 1024 = 2**10 */
+ u32_tmp = u32_tmp / adp_khz;
+ u32_tmp = u32_tmp * 16384; /* 16384 = 2**14 */
+ u32_tmp /= 125 ; /* 125 = 1000/2**3 */
+ u32_tmp = u32_tmp * 16; /* 16 = 2**4 */
+
+ /* SRC Gain Calculation */
+ u32_tmp1 *= 1024; /* *2*2^9 */
+ u32_tmp1 /= 439; /* *2/878 */
+ u32_tmp1 *= 256; /* *2^8 */
+ u32_tmp1 = u32_tmp1 / adp_khz; /* /(AdpClk in kHz)*/
+ u32_tmp1 *= QamSizeCorr * 9; /* *1000*corr factor */
+ u32_tmp1 = u32_tmp1 / 5000000;
+ } else if (u32_tmp < 8388607) { /* 8388607 = 2**23 */
+ /* Symbol rate calculation */
+ u32_tmp *= 512 ; /* 512 = 2**9 */
+ u32_tmp = u32_tmp / adp_khz;
+ u32_tmp = u32_tmp * 16384; /* 16384 = 2**14 */
+ u32_tmp /= 125 ; /* 125 = 1000/2**3 */
+ u32_tmp = u32_tmp * 32; /* 32 = 2**5 */
+
+ /* SRC Gain Calculation */
+ u32_tmp1 *= 512; /* *2*2^8 */
+ u32_tmp1 /= 439; /* *2/878 */
+ u32_tmp1 *= 256; /* *2^8 */
+ u32_tmp1 = u32_tmp1 / adp_khz; /* /(AdpClk in kHz) */
+ u32_tmp1 *= QamSizeCorr * 9; /* *1000*corr factor */
+ u32_tmp1 = u32_tmp1 / 2500000;
+ } else {
+ /* Symbol rate calculation */
+ u32_tmp *= 256 ; /* 256 = 2**8 */
+ u32_tmp = u32_tmp / adp_khz;
+ u32_tmp = u32_tmp * 16384; /* 16384 = 2**13 */
+ u32_tmp /= 125 ; /* 125 = 1000/2**3 */
+ u32_tmp = u32_tmp * 64; /* 64 = 2**6 */
+
+ /* SRC Gain Calculation */
+ u32_tmp1 *= 256; /* 2*2^7 */
+ u32_tmp1 /= 439; /* *2/878 */
+ u32_tmp1 *= 256; /* *2^8 */
+ u32_tmp1 = u32_tmp1 / adp_khz; /* /(AdpClk in kHz) */
+ u32_tmp1 *= QamSizeCorr * 9; /* *1000*corr factor */
+ u32_tmp1 = u32_tmp1 / 1250000;
+ }
+ }
+#if 0
+ /* Filters' coefficients are calculated and written
+ into registers only if the filters are enabled */
+ if (stv0367_readbits(state, F367CAB_ADJ_EN)) {
+ stv0367cab_SetIirAdjacentcoefficient(state, mclk_hz,
+ SymbolRate);
+ /* AllPass filter must be enabled
+ when the adjacents filter is used */
+ stv0367_writebits(state, F367CAB_ALLPASSFILT_EN, 1);
+ stv0367cab_SetAllPasscoefficient(state, mclk_hz, SymbolRate);
+ } else
+ /* AllPass filter must be disabled
+ when the adjacents filter is not used */
+#endif
+ stv0367_writebits(state, F367CAB_ALLPASSFILT_EN, 0);
+
+ stv0367_writereg(state, R367CAB_SRC_NCO_LL, u32_tmp);
+ stv0367_writereg(state, R367CAB_SRC_NCO_LH, (u32_tmp >> 8));
+ stv0367_writereg(state, R367CAB_SRC_NCO_HL, (u32_tmp >> 16));
+ stv0367_writereg(state, R367CAB_SRC_NCO_HH, (u32_tmp >> 24));
+
+ stv0367_writereg(state, R367CAB_IQDEM_GAIN_SRC_L, u32_tmp1 & 0x00ff);
+ stv0367_writebits(state, F367CAB_GAIN_SRC_HI, (u32_tmp1 >> 8) & 0x00ff);
+
+ return SymbolRate ;
+}
+
+static u32 stv0367cab_GetSymbolRate(struct stv0367_state *state, u32 mclk_hz)
+{
+ u32 regsym;
+ u32 adp_khz;
+
+ regsym = stv0367_readreg(state, R367CAB_SRC_NCO_LL) +
+ (stv0367_readreg(state, R367CAB_SRC_NCO_LH) << 8) +
+ (stv0367_readreg(state, R367CAB_SRC_NCO_HL) << 16) +
+ (stv0367_readreg(state, R367CAB_SRC_NCO_HH) << 24);
+
+ adp_khz = (mclk_hz >> 1) / 1000;/* TRL works at half the system clock */
+
+ if (regsym < 134217728) { /* 134217728L = 2**27*/
+ regsym = regsym * 32; /* 32 = 2**5 */
+ regsym = regsym / 32768; /* 32768L = 2**15 */
+ regsym = adp_khz * regsym; /* AdpClk in kHz */
+ regsym = regsym / 128; /* 128 = 2**7 */
+ regsym *= 125 ; /* 125 = 1000/2**3 */
+ regsym /= 2048 ; /* 2048 = 2**11 */
+ } else if (regsym < 268435456) { /* 268435456L = 2**28 */
+ regsym = regsym * 16; /* 16 = 2**4 */
+ regsym = regsym / 32768; /* 32768L = 2**15 */
+ regsym = adp_khz * regsym; /* AdpClk in kHz */
+ regsym = regsym / 128; /* 128 = 2**7 */
+ regsym *= 125 ; /* 125 = 1000/2**3*/
+ regsym /= 1024 ; /* 256 = 2**10*/
+ } else if (regsym < 536870912) { /* 536870912L = 2**29*/
+ regsym = regsym * 8; /* 8 = 2**3 */
+ regsym = regsym / 32768; /* 32768L = 2**15 */
+ regsym = adp_khz * regsym; /* AdpClk in kHz */
+ regsym = regsym / 128; /* 128 = 2**7 */
+ regsym *= 125 ; /* 125 = 1000/2**3 */
+ regsym /= 512 ; /* 128 = 2**9 */
+ } else {
+ regsym = regsym * 4; /* 4 = 2**2 */
+ regsym = regsym / 32768; /* 32768L = 2**15 */
+ regsym = adp_khz * regsym; /* AdpClk in kHz */
+ regsym = regsym / 128; /* 128 = 2**7 */
+ regsym *= 125 ; /* 125 = 1000/2**3 */
+ regsym /= 256 ; /* 64 = 2**8 */
+ }
+
+ return regsym;
+}
+
+static int stv0367cab_read_status(struct dvb_frontend *fe, fe_status_t *status)
+{
+ struct stv0367_state *state = fe->demodulator_priv;
+
+ dprintk("%s:\n", __func__);
+
+ *status = 0;
+
+ if (stv0367_readbits(state, F367CAB_QAMFEC_LOCK)) {
+ *status |= FE_HAS_LOCK;
+ dprintk("%s: stv0367 has locked\n", __func__);
+ }
+
+ return 0;
+}
+
+static int stv0367cab_standby(struct dvb_frontend *fe, u8 standby_on)
+{
+ struct stv0367_state *state = fe->demodulator_priv;
+
+ dprintk("%s:\n", __func__);
+
+ if (standby_on) {
+ stv0367_writebits(state, F367CAB_BYPASS_PLLXN, 0x03);
+ stv0367_writebits(state, F367CAB_STDBY_PLLXN, 0x01);
+ stv0367_writebits(state, F367CAB_STDBY, 1);
+ stv0367_writebits(state, F367CAB_STDBY_CORE, 1);
+ stv0367_writebits(state, F367CAB_EN_BUFFER_I, 0);
+ stv0367_writebits(state, F367CAB_EN_BUFFER_Q, 0);
+ stv0367_writebits(state, F367CAB_POFFQ, 1);
+ stv0367_writebits(state, F367CAB_POFFI, 1);
+ } else {
+ stv0367_writebits(state, F367CAB_STDBY_PLLXN, 0x00);
+ stv0367_writebits(state, F367CAB_BYPASS_PLLXN, 0x00);
+ stv0367_writebits(state, F367CAB_STDBY, 0);
+ stv0367_writebits(state, F367CAB_STDBY_CORE, 0);
+ stv0367_writebits(state, F367CAB_EN_BUFFER_I, 1);
+ stv0367_writebits(state, F367CAB_EN_BUFFER_Q, 1);
+ stv0367_writebits(state, F367CAB_POFFQ, 0);
+ stv0367_writebits(state, F367CAB_POFFI, 0);
+ }
+
+ return 0;
+}
+
+static int stv0367cab_sleep(struct dvb_frontend *fe)
+{
+ return stv0367cab_standby(fe, 1);
+}
+
+int stv0367cab_init(struct dvb_frontend *fe)
+{
+ struct stv0367_state *state = fe->demodulator_priv;
+ struct stv0367cab_state *cab_state = state->cab_state;
+ int i;
+
+ dprintk("%s:\n", __func__);
+
+ for (i = 0; i < STV0367CAB_NBREGS; i++)
+ stv0367_writereg(state, def0367cab[i].addr,
+ def0367cab[i].value);
+
+ switch (state->config->ts_mode) {
+ case STV0367_DVBCI_CLOCK:
+ dprintk("Setting TSMode = STV0367_DVBCI_CLOCK\n");
+ stv0367_writebits(state, F367CAB_OUTFORMAT, 0x03);
+ break;
+ case STV0367_SERIAL_PUNCT_CLOCK:
+ case STV0367_SERIAL_CONT_CLOCK:
+ stv0367_writebits(state, F367CAB_OUTFORMAT, 0x01);
+ break;
+ case STV0367_PARALLEL_PUNCT_CLOCK:
+ case STV0367_OUTPUTMODE_DEFAULT:
+ stv0367_writebits(state, F367CAB_OUTFORMAT, 0x00);
+ break;
+ }
+
+ switch (state->config->clk_pol) {
+ case STV0367_RISINGEDGE_CLOCK:
+ stv0367_writebits(state, F367CAB_CLK_POLARITY, 0x00);
+ break;
+ case STV0367_FALLINGEDGE_CLOCK:
+ case STV0367_CLOCKPOLARITY_DEFAULT:
+ stv0367_writebits(state, F367CAB_CLK_POLARITY, 0x01);
+ break;
+ }
+
+ stv0367_writebits(state, F367CAB_SYNC_STRIP, 0x00);
+
+ stv0367_writebits(state, F367CAB_CT_NBST, 0x01);
+
+ stv0367_writebits(state, F367CAB_TS_SWAP, 0x01);
+
+ stv0367_writebits(state, F367CAB_FIFO_BYPASS, 0x00);
+
+ stv0367_writereg(state, R367CAB_ANACTRL, 0x00);/*PLL enabled and used */
+
+ cab_state->mclk = stv0367cab_get_mclk(fe, state->config->xtal);
+ cab_state->adc_clk = stv0367cab_get_adc_freq(fe, state->config->xtal);
+
+ return 0;
+}
+static
+enum stv0367_cab_signal_type stv0367cab_algo(struct stv0367_state *state,
+ struct dvb_frontend_parameters *param)
+{
+ struct dvb_qam_parameters *op = &param->u.qam;
+ struct stv0367cab_state *cab_state = state->cab_state;
+ enum stv0367_cab_signal_type signalType = FE_CAB_NOAGC;
+ u32 QAMFEC_Lock, QAM_Lock, u32_tmp,
+ LockTime, TRLTimeOut, AGCTimeOut, CRLSymbols,
+ CRLTimeOut, EQLTimeOut, DemodTimeOut, FECTimeOut;
+ u8 TrackAGCAccum;
+ s32 tmp;
+
+ dprintk("%s:\n", __func__);
+
+ /* Timeouts calculation */
+ /* A max lock time of 25 ms is allowed for delayed AGC */
+ AGCTimeOut = 25;
+ /* 100000 symbols needed by the TRL as a maximum value */
+ TRLTimeOut = 100000000 / op->symbol_rate;
+ /* CRLSymbols is the needed number of symbols to achieve a lock
+ within [-4%, +4%] of the symbol rate.
+ CRL timeout is calculated
+ for a lock within [-search_range, +search_range].
+ EQL timeout can be changed depending on
+ the micro-reflections we want to handle.
+ A characterization must be performed
+ with these echoes to get new timeout values.
+ */
+ switch (op->modulation) {
+ case QAM_16:
+ CRLSymbols = 150000;
+ EQLTimeOut = 100;
+ break;
+ case QAM_32:
+ CRLSymbols = 250000;
+ EQLTimeOut = 100;
+ break;
+ case QAM_64:
+ CRLSymbols = 200000;
+ EQLTimeOut = 100;
+ break;
+ case QAM_128:
+ CRLSymbols = 250000;
+ EQLTimeOut = 100;
+ break;
+ case QAM_256:
+ CRLSymbols = 250000;
+ EQLTimeOut = 100;
+ break;
+ default:
+ CRLSymbols = 200000;
+ EQLTimeOut = 100;
+ break;
+ }
+#if 0
+ if (pIntParams->search_range < 0) {
+ CRLTimeOut = (25 * CRLSymbols *
+ (-pIntParams->search_range / 1000)) /
+ (pIntParams->symbol_rate / 1000);
+ } else
+#endif
+ CRLTimeOut = (25 * CRLSymbols * (cab_state->search_range / 1000)) /
+ (op->symbol_rate / 1000);
+
+ CRLTimeOut = (1000 * CRLTimeOut) / op->symbol_rate;
+ /* Timeouts below 50ms are coerced */
+ if (CRLTimeOut < 50)
+ CRLTimeOut = 50;
+ /* A maximum of 100 TS packets is needed to get FEC lock even in case
+ the spectrum inversion needs to be changed.
+ This is equal to 20 ms in case of the lowest symbol rate of 0.87Msps
+ */
+ FECTimeOut = 20;
+ DemodTimeOut = AGCTimeOut + TRLTimeOut + CRLTimeOut + EQLTimeOut;
+
+ dprintk("%s: DemodTimeOut=%d\n", __func__, DemodTimeOut);
+
+ /* Reset the TRL to ensure nothing starts until the
+ AGC is stable which ensures a better lock time
+ */
+ stv0367_writereg(state, R367CAB_CTRL_1, 0x04);
+ /* Set AGC accumulation time to minimum and lock threshold to maximum
+ in order to speed up the AGC lock */
+ TrackAGCAccum = stv0367_readbits(state, F367CAB_AGC_ACCUMRSTSEL);
+ stv0367_writebits(state, F367CAB_AGC_ACCUMRSTSEL, 0x0);
+ /* Modulus Mapper is disabled */
+ stv0367_writebits(state, F367CAB_MODULUSMAP_EN, 0);
+ /* Disable the sweep function */
+ stv0367_writebits(state, F367CAB_SWEEP_EN, 0);
+ /* The sweep function is never used, Sweep rate must be set to 0 */
+ /* Set the derotator frequency in Hz */
+ stv0367cab_set_derot_freq(state, cab_state->adc_clk,
+ (1000 * (s32)state->config->if_khz + cab_state->derot_offset));
+ /* Disable the Allpass Filter when the symbol rate is out of range */
+ if ((op->symbol_rate > 10800000) | (op->symbol_rate < 1800000)) {
+ stv0367_writebits(state, F367CAB_ADJ_EN, 0);
+ stv0367_writebits(state, F367CAB_ALLPASSFILT_EN, 0);
+ }
+#if 0
+ /* Check if the tuner is locked */
+ tuner_lock = stv0367cab_tuner_get_status(fe);
+ if (tuner_lock == 0)
+ return FE_367CAB_NOTUNER;
+#endif
+ /* Relase the TRL to start demodulator acquisition */
+ /* Wait for QAM lock */
+ LockTime = 0;
+ stv0367_writereg(state, R367CAB_CTRL_1, 0x00);
+ do {
+ QAM_Lock = stv0367_readbits(state, F367CAB_FSM_STATUS);
+ if ((LockTime >= (DemodTimeOut - EQLTimeOut)) &&
+ (QAM_Lock == 0x04))
+ /*
+ * We don't wait longer, the frequency/phase offset
+ * must be too big
+ */
+ LockTime = DemodTimeOut;
+ else if ((LockTime >= (AGCTimeOut + TRLTimeOut)) &&
+ (QAM_Lock == 0x02))
+ /*
+ * We don't wait longer, either there is no signal or
+ * it is not the right symbol rate or it is an analog
+ * carrier
+ */
+ {
+ LockTime = DemodTimeOut;
+ u32_tmp = stv0367_readbits(state,
+ F367CAB_AGC_PWR_WORD_LO) +
+ (stv0367_readbits(state,
+ F367CAB_AGC_PWR_WORD_ME) << 8) +
+ (stv0367_readbits(state,
+ F367CAB_AGC_PWR_WORD_HI) << 16);
+ if (u32_tmp >= 131072)
+ u32_tmp = 262144 - u32_tmp;
+ u32_tmp = u32_tmp / (1 << (11 - stv0367_readbits(state,
+ F367CAB_AGC_IF_BWSEL)));
+
+ if (u32_tmp < stv0367_readbits(state,
+ F367CAB_AGC_PWRREF_LO) +
+ 256 * stv0367_readbits(state,
+ F367CAB_AGC_PWRREF_HI) - 10)
+ QAM_Lock = 0x0f;
+ } else {
+ usleep_range(10000, 20000);
+ LockTime += 10;
+ }
+ dprintk("QAM_Lock=0x%x LockTime=%d\n", QAM_Lock, LockTime);
+ tmp = stv0367_readreg(state, R367CAB_IT_STATUS1);
+
+ dprintk("R367CAB_IT_STATUS1=0x%x\n", tmp);
+
+ } while (((QAM_Lock != 0x0c) && (QAM_Lock != 0x0b)) &&
+ (LockTime < DemodTimeOut));
+
+ dprintk("QAM_Lock=0x%x\n", QAM_Lock);
+
+ tmp = stv0367_readreg(state, R367CAB_IT_STATUS1);
+ dprintk("R367CAB_IT_STATUS1=0x%x\n", tmp);
+ tmp = stv0367_readreg(state, R367CAB_IT_STATUS2);
+ dprintk("R367CAB_IT_STATUS2=0x%x\n", tmp);
+
+ tmp = stv0367cab_get_derot_freq(state, cab_state->adc_clk);
+ dprintk("stv0367cab_get_derot_freq=0x%x\n", tmp);
+
+ if ((QAM_Lock == 0x0c) || (QAM_Lock == 0x0b)) {
+ /* Wait for FEC lock */
+ LockTime = 0;
+ do {
+ usleep_range(5000, 7000);
+ LockTime += 5;
+ QAMFEC_Lock = stv0367_readbits(state,
+ F367CAB_QAMFEC_LOCK);
+ } while (!QAMFEC_Lock && (LockTime < FECTimeOut));
+ } else
+ QAMFEC_Lock = 0;
+
+ if (QAMFEC_Lock) {
+ signalType = FE_CAB_DATAOK;
+ cab_state->modulation = op->modulation;
+ cab_state->spect_inv = stv0367_readbits(state,
+ F367CAB_QUAD_INV);
+#if 0
+/* not clear for me */
+ if (state->config->if_khz != 0) {
+ if (state->config->if_khz > cab_state->adc_clk / 1000) {
+ cab_state->freq_khz =
+ FE_Cab_TunerGetFrequency(pIntParams->hTuner)
+ - stv0367cab_get_derot_freq(state, cab_state->adc_clk)
+ - cab_state->adc_clk / 1000 + state->config->if_khz;
+ } else {
+ cab_state->freq_khz =
+ FE_Cab_TunerGetFrequency(pIntParams->hTuner)
+ - stv0367cab_get_derot_freq(state, cab_state->adc_clk)
+ + state->config->if_khz;
+ }
+ } else {
+ cab_state->freq_khz =
+ FE_Cab_TunerGetFrequency(pIntParams->hTuner) +
+ stv0367cab_get_derot_freq(state,
+ cab_state->adc_clk) -
+ cab_state->adc_clk / 4000;
+ }
+#endif
+ cab_state->symbol_rate = stv0367cab_GetSymbolRate(state,
+ cab_state->mclk);
+ cab_state->locked = 1;
+
+ /* stv0367_setbits(state, F367CAB_AGC_ACCUMRSTSEL,7);*/
+ } else {
+ switch (QAM_Lock) {
+ case 1:
+ signalType = FE_CAB_NOAGC;
+ break;
+ case 2:
+ signalType = FE_CAB_NOTIMING;
+ break;
+ case 3:
+ signalType = FE_CAB_TIMINGOK;
+ break;
+ case 4:
+ signalType = FE_CAB_NOCARRIER;
+ break;
+ case 5:
+ signalType = FE_CAB_CARRIEROK;
+ break;
+ case 7:
+ signalType = FE_CAB_NOBLIND;
+ break;
+ case 8:
+ signalType = FE_CAB_BLINDOK;
+ break;
+ case 10:
+ signalType = FE_CAB_NODEMOD;
+ break;
+ case 11:
+ signalType = FE_CAB_DEMODOK;
+ break;
+ case 12:
+ signalType = FE_CAB_DEMODOK;
+ break;
+ case 13:
+ signalType = FE_CAB_NODEMOD;
+ break;
+ case 14:
+ signalType = FE_CAB_NOBLIND;
+ break;
+ case 15:
+ signalType = FE_CAB_NOSIGNAL;
+ break;
+ default:
+ break;
+ }
+
+ }
+
+ /* Set the AGC control values to tracking values */
+ stv0367_writebits(state, F367CAB_AGC_ACCUMRSTSEL, TrackAGCAccum);
+ return signalType;
+}
+
+static int stv0367cab_set_frontend(struct dvb_frontend *fe,
+ struct dvb_frontend_parameters *param)
+{
+ struct stv0367_state *state = fe->demodulator_priv;
+ struct stv0367cab_state *cab_state = state->cab_state;
+ struct dvb_qam_parameters *op = &param->u.qam;
+ enum stv0367cab_mod QAMSize = 0;
+
+ dprintk("%s: freq = %d, srate = %d\n", __func__,
+ param->frequency, op->symbol_rate);
+
+ cab_state->derot_offset = 0;
+
+ switch (op->modulation) {
+ case QAM_16:
+ QAMSize = FE_CAB_MOD_QAM16;
+ break;
+ case QAM_32:
+ QAMSize = FE_CAB_MOD_QAM32;
+ break;
+ case QAM_64:
+ QAMSize = FE_CAB_MOD_QAM64;
+ break;
+ case QAM_128:
+ QAMSize = FE_CAB_MOD_QAM128;
+ break;
+ case QAM_256:
+ QAMSize = FE_CAB_MOD_QAM256;
+ break;
+ default:
+ break;
+ }
+
+ stv0367cab_init(fe);
+
+ /* Tuner Frequency Setting */
+ if (fe->ops.tuner_ops.set_params) {
+ if (fe->ops.i2c_gate_ctrl)
+ fe->ops.i2c_gate_ctrl(fe, 1);
+ fe->ops.tuner_ops.set_params(fe, param);
+ if (fe->ops.i2c_gate_ctrl)
+ fe->ops.i2c_gate_ctrl(fe, 0);
+ }
+
+ stv0367cab_SetQamSize(
+ state,
+ op->symbol_rate,
+ QAMSize);
+
+ stv0367cab_set_srate(state,
+ cab_state->adc_clk,
+ cab_state->mclk,
+ op->symbol_rate,
+ QAMSize);
+ /* Search algorithm launch, [-1.1*RangeOffset, +1.1*RangeOffset] scan */
+ cab_state->state = stv0367cab_algo(state, param);
+ return 0;
+}
+
+static int stv0367cab_get_frontend(struct dvb_frontend *fe,
+ struct dvb_frontend_parameters *param)
+{
+ struct stv0367_state *state = fe->demodulator_priv;
+ struct stv0367cab_state *cab_state = state->cab_state;
+ struct dvb_qam_parameters *op = &param->u.qam;
+
+ enum stv0367cab_mod QAMSize;
+
+ dprintk("%s:\n", __func__);
+
+ op->symbol_rate = stv0367cab_GetSymbolRate(state, cab_state->mclk);
+
+ QAMSize = stv0367_readbits(state, F367CAB_QAM_MODE);
+ switch (QAMSize) {
+ case FE_CAB_MOD_QAM16:
+ op->modulation = QAM_16;
+ break;
+ case FE_CAB_MOD_QAM32:
+ op->modulation = QAM_32;
+ break;
+ case FE_CAB_MOD_QAM64:
+ op->modulation = QAM_64;
+ break;
+ case FE_CAB_MOD_QAM128:
+ op->modulation = QAM_128;
+ break;
+ case QAM_256:
+ op->modulation = QAM_256;
+ break;
+ default:
+ break;
+ }
+
+ param->frequency = stv0367_get_tuner_freq(fe);
+
+ dprintk("%s: tuner frequency = %d\n", __func__, param->frequency);
+
+ if (state->config->if_khz == 0) {
+ param->frequency +=
+ (stv0367cab_get_derot_freq(state, cab_state->adc_clk) -
+ cab_state->adc_clk / 4000);
+ return 0;
+ }
+
+ if (state->config->if_khz > cab_state->adc_clk / 1000)
+ param->frequency += (state->config->if_khz
+ - stv0367cab_get_derot_freq(state, cab_state->adc_clk)
+ - cab_state->adc_clk / 1000);
+ else
+ param->frequency += (state->config->if_khz
+ - stv0367cab_get_derot_freq(state, cab_state->adc_clk));
+
+ return 0;
+}
+
+#if 0
+void stv0367cab_GetErrorCount(state, enum stv0367cab_mod QAMSize,
+ u32 symbol_rate, FE_367qam_Monitor *Monitor_results)
+{
+ stv0367cab_OptimiseNByteAndGetBER(state, QAMSize, symbol_rate, Monitor_results);
+ stv0367cab_GetPacketsCount(state, Monitor_results);
+
+ return;
+}
+
+static int stv0367cab_read_ber(struct dvb_frontend *fe, u32 *ber)
+{
+ struct stv0367_state *state = fe->demodulator_priv;
+
+ return 0;
+}
+#endif
+static s32 stv0367cab_get_rf_lvl(struct stv0367_state *state)
+{
+ s32 rfLevel = 0;
+ s32 RfAgcPwm = 0, IfAgcPwm = 0;
+ u8 i;
+
+ stv0367_writebits(state, F367CAB_STDBY_ADCGP, 0x0);
+
+ RfAgcPwm =
+ (stv0367_readbits(state, F367CAB_RF_AGC1_LEVEL_LO) & 0x03) +
+ (stv0367_readbits(state, F367CAB_RF_AGC1_LEVEL_HI) << 2);
+ RfAgcPwm = 100 * RfAgcPwm / 1023;
+
+ IfAgcPwm =
+ stv0367_readbits(state, F367CAB_AGC_IF_PWMCMD_LO) +
+ (stv0367_readbits(state, F367CAB_AGC_IF_PWMCMD_HI) << 8);
+ if (IfAgcPwm >= 2048)
+ IfAgcPwm -= 2048;
+ else
+ IfAgcPwm += 2048;
+
+ IfAgcPwm = 100 * IfAgcPwm / 4095;
+
+ /* For DTT75467 on NIM */
+ if (RfAgcPwm < 90 && IfAgcPwm < 28) {
+ for (i = 0; i < RF_LOOKUP_TABLE_SIZE; i++) {
+ if (RfAgcPwm <= stv0367cab_RF_LookUp1[0][i]) {
+ rfLevel = (-1) * stv0367cab_RF_LookUp1[1][i];
+ break;
+ }
+ }
+ if (i == RF_LOOKUP_TABLE_SIZE)
+ rfLevel = -56;
+ } else { /*if IF AGC>10*/
+ for (i = 0; i < RF_LOOKUP_TABLE2_SIZE; i++) {
+ if (IfAgcPwm <= stv0367cab_RF_LookUp2[0][i]) {
+ rfLevel = (-1) * stv0367cab_RF_LookUp2[1][i];
+ break;
+ }
+ }
+ if (i == RF_LOOKUP_TABLE2_SIZE)
+ rfLevel = -72;
+ }
+ return rfLevel;
+}
+
+static int stv0367cab_read_strength(struct dvb_frontend *fe, u16 *strength)
+{
+ struct stv0367_state *state = fe->demodulator_priv;
+
+ s32 signal = stv0367cab_get_rf_lvl(state);
+
+ dprintk("%s: signal=%d dBm\n", __func__, signal);
+
+ if (signal <= -72)
+ *strength = 65535;
+ else
+ *strength = (22 + signal) * (-1311);
+
+ dprintk("%s: strength=%d\n", __func__, (*strength));
+
+ return 0;
+}
+
+static int stv0367cab_read_snr(struct dvb_frontend *fe, u16 *snr)
+{
+ struct stv0367_state *state = fe->demodulator_priv;
+ u32 noisepercentage;
+ enum stv0367cab_mod QAMSize;
+ u32 regval = 0, temp = 0;
+ int power, i;
+
+ QAMSize = stv0367_readbits(state, F367CAB_QAM_MODE);
+ switch (QAMSize) {
+ case FE_CAB_MOD_QAM4:
+ power = 21904;
+ break;
+ case FE_CAB_MOD_QAM16:
+ power = 20480;
+ break;
+ case FE_CAB_MOD_QAM32:
+ power = 23040;
+ break;
+ case FE_CAB_MOD_QAM64:
+ power = 21504;
+ break;
+ case FE_CAB_MOD_QAM128:
+ power = 23616;
+ break;
+ case FE_CAB_MOD_QAM256:
+ power = 21760;
+ break;
+ case FE_CAB_MOD_QAM512:
+ power = 1;
+ break;
+ case FE_CAB_MOD_QAM1024:
+ power = 21280;
+ break;
+ default:
+ power = 1;
+ break;
+ }
+
+ for (i = 0; i < 10; i++) {
+ regval += (stv0367_readbits(state, F367CAB_SNR_LO)
+ + 256 * stv0367_readbits(state, F367CAB_SNR_HI));
+ }
+
+ regval /= 10; /*for average over 10 times in for loop above*/
+ if (regval != 0) {
+ temp = power
+ * (1 << (3 + stv0367_readbits(state, F367CAB_SNR_PER)));
+ temp /= regval;
+ }
+
+ /* table values, not needed to calculate logarithms */
+ if (temp >= 5012)
+ noisepercentage = 100;
+ else if (temp >= 3981)
+ noisepercentage = 93;
+ else if (temp >= 3162)
+ noisepercentage = 86;
+ else if (temp >= 2512)
+ noisepercentage = 79;
+ else if (temp >= 1995)
+ noisepercentage = 72;
+ else if (temp >= 1585)
+ noisepercentage = 65;
+ else if (temp >= 1259)
+ noisepercentage = 58;
+ else if (temp >= 1000)
+ noisepercentage = 50;
+ else if (temp >= 794)
+ noisepercentage = 43;
+ else if (temp >= 501)
+ noisepercentage = 36;
+ else if (temp >= 316)
+ noisepercentage = 29;
+ else if (temp >= 200)
+ noisepercentage = 22;
+ else if (temp >= 158)
+ noisepercentage = 14;
+ else if (temp >= 126)
+ noisepercentage = 7;
+ else
+ noisepercentage = 0;
+
+ dprintk("%s: noisepercentage=%d\n", __func__, noisepercentage);
+
+ *snr = (noisepercentage * 65535) / 100;
+
+ return 0;
+}
+
+static int stv0367cab_read_ucblcks(struct dvb_frontend *fe, u32 *ucblocks)
+{
+ struct stv0367_state *state = fe->demodulator_priv;
+ int corrected, tscount;
+
+ *ucblocks = (stv0367_readreg(state, R367CAB_RS_COUNTER_5) << 8)
+ | stv0367_readreg(state, R367CAB_RS_COUNTER_4);
+ corrected = (stv0367_readreg(state, R367CAB_RS_COUNTER_3) << 8)
+ | stv0367_readreg(state, R367CAB_RS_COUNTER_2);
+ tscount = (stv0367_readreg(state, R367CAB_RS_COUNTER_2) << 8)
+ | stv0367_readreg(state, R367CAB_RS_COUNTER_1);
+
+ dprintk("%s: uncorrected blocks=%d corrected blocks=%d tscount=%d\n",
+ __func__, *ucblocks, corrected, tscount);
+
+ return 0;
+};
+
+static struct dvb_frontend_ops stv0367cab_ops = {
+ .info = {
+ .name = "ST STV0367 DVB-C",
+ .type = FE_QAM,
+ .frequency_min = 47000000,
+ .frequency_max = 862000000,
+ .frequency_stepsize = 62500,
+ .symbol_rate_min = 870000,
+ .symbol_rate_max = 11700000,
+ .caps = 0x400 |/* FE_CAN_QAM_4 */
+ FE_CAN_QAM_16 | FE_CAN_QAM_32 |
+ FE_CAN_QAM_64 | FE_CAN_QAM_128 |
+ FE_CAN_QAM_256 | FE_CAN_FEC_AUTO
+ },
+ .release = stv0367_release,
+ .init = stv0367cab_init,
+ .sleep = stv0367cab_sleep,
+ .i2c_gate_ctrl = stv0367cab_gate_ctrl,
+ .set_frontend = stv0367cab_set_frontend,
+ .get_frontend = stv0367cab_get_frontend,
+ .read_status = stv0367cab_read_status,
+/* .read_ber = stv0367cab_read_ber, */
+ .read_signal_strength = stv0367cab_read_strength,
+ .read_snr = stv0367cab_read_snr,
+ .read_ucblocks = stv0367cab_read_ucblcks,
+ .get_tune_settings = stv0367_get_tune_settings,
+};
+
+struct dvb_frontend *stv0367cab_attach(const struct stv0367_config *config,
+ struct i2c_adapter *i2c)
+{
+ struct stv0367_state *state = NULL;
+ struct stv0367cab_state *cab_state = NULL;
+
+ /* allocate memory for the internal state */
+ state = kzalloc(sizeof(struct stv0367_state), GFP_KERNEL);
+ if (state == NULL)
+ goto error;
+ cab_state = kzalloc(sizeof(struct stv0367cab_state), GFP_KERNEL);
+ if (cab_state == NULL)
+ goto error;
+
+ /* setup the state */
+ state->i2c = i2c;
+ state->config = config;
+ cab_state->search_range = 280000;
+ state->cab_state = cab_state;
+ state->fe.ops = stv0367cab_ops;
+ state->fe.demodulator_priv = state;
+ state->chip_id = stv0367_readreg(state, 0xf000);
+
+ dprintk("%s: chip_id = 0x%x\n", __func__, state->chip_id);
+
+ /* check if the demod is there */
+ if ((state->chip_id != 0x50) && (state->chip_id != 0x60))
+ goto error;
+
+ return &state->fe;
+
+error:
+ kfree(cab_state);
+ kfree(state);
+ return NULL;
+}
+EXPORT_SYMBOL(stv0367cab_attach);
+
+MODULE_PARM_DESC(debug, "Set debug");
+MODULE_PARM_DESC(i2c_debug, "Set i2c debug");
+
+MODULE_AUTHOR("Igor M. Liplianin");
+MODULE_DESCRIPTION("ST STV0367 DVB-C/T demodulator driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/media/dvb/frontends/stv0367.h b/drivers/media/dvb/frontends/stv0367.h
new file mode 100644
index 00000000000..93cc4a57eea
--- /dev/null
+++ b/drivers/media/dvb/frontends/stv0367.h
@@ -0,0 +1,66 @@
+/*
+ * stv0367.h
+ *
+ * Driver for ST STV0367 DVB-T & DVB-C demodulator IC.
+ *
+ * Copyright (C) ST Microelectronics.
+ * Copyright (C) 2010,2011 NetUP Inc.
+ * Copyright (C) 2010,2011 Igor M. Liplianin <liplianin@netup.ru>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ *
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef STV0367_H
+#define STV0367_H
+
+#include <linux/dvb/frontend.h>
+#include "dvb_frontend.h"
+
+struct stv0367_config {
+ u8 demod_address;
+ u32 xtal;
+ u32 if_khz;/*4500*/
+ int if_iq_mode;
+ int ts_mode;
+ int clk_pol;
+};
+
+#if defined(CONFIG_DVB_STV0367) || (defined(CONFIG_DVB_STV0367_MODULE) \
+ && defined(MODULE))
+extern struct
+dvb_frontend *stv0367ter_attach(const struct stv0367_config *config,
+ struct i2c_adapter *i2c);
+extern struct
+dvb_frontend *stv0367cab_attach(const struct stv0367_config *config,
+ struct i2c_adapter *i2c);
+#else
+static inline struct
+dvb_frontend *stv0367ter_attach(const struct stv0367_config *config,
+ struct i2c_adapter *i2c)
+{
+ printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
+ return NULL;
+}
+static inline struct
+dvb_frontend *stv0367cab_attach(const struct stv0367_config *config,
+ struct i2c_adapter *i2c)
+{
+ printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
+ return NULL;
+}
+#endif
+
+#endif
diff --git a/drivers/media/dvb/frontends/stv0367_priv.h b/drivers/media/dvb/frontends/stv0367_priv.h
new file mode 100644
index 00000000000..995db0689dd
--- /dev/null
+++ b/drivers/media/dvb/frontends/stv0367_priv.h
@@ -0,0 +1,212 @@
+/*
+ * stv0367_priv.h
+ *
+ * Driver for ST STV0367 DVB-T & DVB-C demodulator IC.
+ *
+ * Copyright (C) ST Microelectronics.
+ * Copyright (C) 2010,2011 NetUP Inc.
+ * Copyright (C) 2010,2011 Igor M. Liplianin <liplianin@netup.ru>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ *
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+/* Common driver error constants */
+
+#ifndef STV0367_PRIV_H
+#define STV0367_PRIV_H
+
+#ifndef TRUE
+ #define TRUE (1 == 1)
+#endif
+#ifndef FALSE
+ #define FALSE (!TRUE)
+#endif
+
+#ifndef NULL
+#define NULL 0
+#endif
+
+/* MACRO definitions */
+#define ABS(X) ((X) < 0 ? (-1 * (X)) : (X))
+#define MAX(X, Y) ((X) >= (Y) ? (X) : (Y))
+#define MIN(X, Y) ((X) <= (Y) ? (X) : (Y))
+#define INRANGE(X, Y, Z) \
+ ((((X) <= (Y)) && ((Y) <= (Z))) || \
+ (((Z) <= (Y)) && ((Y) <= (X))) ? 1 : 0)
+
+#ifndef MAKEWORD
+#define MAKEWORD(X, Y) (((X) << 8) + (Y))
+#endif
+
+#define LSB(X) (((X) & 0xff))
+#define MSB(Y) (((Y) >> 8) & 0xff)
+#define MMSB(Y)(((Y) >> 16) & 0xff)
+
+enum stv0367_ter_signal_type {
+ FE_TER_NOAGC = 0,
+ FE_TER_AGCOK = 5,
+ FE_TER_NOTPS = 6,
+ FE_TER_TPSOK = 7,
+ FE_TER_NOSYMBOL = 8,
+ FE_TER_BAD_CPQ = 9,
+ FE_TER_PRFOUNDOK = 10,
+ FE_TER_NOPRFOUND = 11,
+ FE_TER_LOCKOK = 12,
+ FE_TER_NOLOCK = 13,
+ FE_TER_SYMBOLOK = 15,
+ FE_TER_CPAMPOK = 16,
+ FE_TER_NOCPAMP = 17,
+ FE_TER_SWNOK = 18
+};
+
+enum stv0367_ts_mode {
+ STV0367_OUTPUTMODE_DEFAULT,
+ STV0367_SERIAL_PUNCT_CLOCK,
+ STV0367_SERIAL_CONT_CLOCK,
+ STV0367_PARALLEL_PUNCT_CLOCK,
+ STV0367_DVBCI_CLOCK
+};
+
+enum stv0367_clk_pol {
+ STV0367_CLOCKPOLARITY_DEFAULT,
+ STV0367_RISINGEDGE_CLOCK,
+ STV0367_FALLINGEDGE_CLOCK
+};
+
+enum stv0367_ter_bw {
+ FE_TER_CHAN_BW_6M = 6,
+ FE_TER_CHAN_BW_7M = 7,
+ FE_TER_CHAN_BW_8M = 8
+};
+
+#if 0
+enum FE_TER_Rate_TPS {
+ FE_TER_TPS_1_2 = 0,
+ FE_TER_TPS_2_3 = 1,
+ FE_TER_TPS_3_4 = 2,
+ FE_TER_TPS_5_6 = 3,
+ FE_TER_TPS_7_8 = 4
+};
+#endif
+
+enum stv0367_ter_mode {
+ FE_TER_MODE_2K,
+ FE_TER_MODE_8K,
+ FE_TER_MODE_4K
+};
+#if 0
+enum FE_TER_Hierarchy_Alpha {
+ FE_TER_HIER_ALPHA_NONE, /* Regular modulation */
+ FE_TER_HIER_ALPHA_1, /* Hierarchical modulation a = 1*/
+ FE_TER_HIER_ALPHA_2, /* Hierarchical modulation a = 2*/
+ FE_TER_HIER_ALPHA_4 /* Hierarchical modulation a = 4*/
+};
+#endif
+enum stv0367_ter_hierarchy {
+ FE_TER_HIER_NONE, /*Hierarchy None*/
+ FE_TER_HIER_LOW_PRIO, /*Hierarchy : Low Priority*/
+ FE_TER_HIER_HIGH_PRIO, /*Hierarchy : High Priority*/
+ FE_TER_HIER_PRIO_ANY /*Hierarchy :Any*/
+};
+
+#if 0
+enum fe_stv0367_ter_spec {
+ FE_TER_INVERSION_NONE = 0,
+ FE_TER_INVERSION = 1,
+ FE_TER_INVERSION_AUTO = 2,
+ FE_TER_INVERSION_UNK = 4
+};
+#endif
+
+enum stv0367_ter_if_iq_mode {
+ FE_TER_NORMAL_IF_TUNER = 0,
+ FE_TER_LONGPATH_IF_TUNER = 1,
+ FE_TER_IQ_TUNER = 2
+
+};
+
+#if 0
+enum FE_TER_FECRate {
+ FE_TER_FEC_NONE = 0x00, /* no FEC rate specified */
+ FE_TER_FEC_ALL = 0xFF, /* Logical OR of all FECs */
+ FE_TER_FEC_1_2 = 1,
+ FE_TER_FEC_2_3 = (1 << 1),
+ FE_TER_FEC_3_4 = (1 << 2),
+ FE_TER_FEC_4_5 = (1 << 3),
+ FE_TER_FEC_5_6 = (1 << 4),
+ FE_TER_FEC_6_7 = (1 << 5),
+ FE_TER_FEC_7_8 = (1 << 6),
+ FE_TER_FEC_8_9 = (1 << 7)
+};
+
+enum FE_TER_Rate {
+ FE_TER_FE_1_2 = 0,
+ FE_TER_FE_2_3 = 1,
+ FE_TER_FE_3_4 = 2,
+ FE_TER_FE_5_6 = 3,
+ FE_TER_FE_6_7 = 4,
+ FE_TER_FE_7_8 = 5
+};
+#endif
+
+enum stv0367_ter_force {
+ FE_TER_FORCENONE = 0,
+ FE_TER_FORCE_M_G = 1
+};
+
+enum stv0367cab_mod {
+ FE_CAB_MOD_QAM4,
+ FE_CAB_MOD_QAM16,
+ FE_CAB_MOD_QAM32,
+ FE_CAB_MOD_QAM64,
+ FE_CAB_MOD_QAM128,
+ FE_CAB_MOD_QAM256,
+ FE_CAB_MOD_QAM512,
+ FE_CAB_MOD_QAM1024
+};
+#if 0
+enum {
+ FE_CAB_FEC_A = 1, /* J83 Annex A */
+ FE_CAB_FEC_B = (1 << 1),/* J83 Annex B */
+ FE_CAB_FEC_C = (1 << 2) /* J83 Annex C */
+} FE_CAB_FECType_t;
+#endif
+struct stv0367_cab_signal_info {
+ int locked;
+ u32 frequency; /* kHz */
+ u32 symbol_rate; /* Mbds */
+ enum stv0367cab_mod modulation;
+ fe_spectral_inversion_t spect_inv;
+ s32 Power_dBmx10; /* Power of the RF signal (dBm x 10) */
+ u32 CN_dBx10; /* Carrier to noise ratio (dB x 10) */
+ u32 BER; /* Bit error rate (x 10000000) */
+};
+
+enum stv0367_cab_signal_type {
+ FE_CAB_NOTUNER,
+ FE_CAB_NOAGC,
+ FE_CAB_NOSIGNAL,
+ FE_CAB_NOTIMING,
+ FE_CAB_TIMINGOK,
+ FE_CAB_NOCARRIER,
+ FE_CAB_CARRIEROK,
+ FE_CAB_NOBLIND,
+ FE_CAB_BLINDOK,
+ FE_CAB_NODEMOD,
+ FE_CAB_DEMODOK,
+ FE_CAB_DATAOK
+};
+
+#endif
diff --git a/drivers/media/dvb/frontends/stv0367_regs.h b/drivers/media/dvb/frontends/stv0367_regs.h
new file mode 100644
index 00000000000..a96fbdc7e25
--- /dev/null
+++ b/drivers/media/dvb/frontends/stv0367_regs.h
@@ -0,0 +1,3614 @@
+/*
+ * stv0367_regs.h
+ *
+ * Driver for ST STV0367 DVB-T & DVB-C demodulator IC.
+ *
+ * Copyright (C) ST Microelectronics.
+ * Copyright (C) 2010,2011 NetUP Inc.
+ * Copyright (C) 2010,2011 Igor M. Liplianin <liplianin@netup.ru>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ *
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef STV0367_REGS_H
+#define STV0367_REGS_H
+
+/* ID */
+#define R367TER_ID 0xf000
+#define F367TER_IDENTIFICATIONREG 0xf00000ff
+
+/* I2CRPT */
+#define R367TER_I2CRPT 0xf001
+#define F367TER_I2CT_ON 0xf0010080
+#define F367TER_ENARPT_LEVEL 0xf0010070
+#define F367TER_SCLT_DELAY 0xf0010008
+#define F367TER_SCLT_NOD 0xf0010004
+#define F367TER_STOP_ENABLE 0xf0010002
+#define F367TER_SDAT_NOD 0xf0010001
+
+/* TOPCTRL */
+#define R367TER_TOPCTRL 0xf002
+#define F367TER_STDBY 0xf0020080
+#define F367TER_STDBY_FEC 0xf0020040
+#define F367TER_STDBY_CORE 0xf0020020
+#define F367TER_QAM_COFDM 0xf0020010
+#define F367TER_TS_DIS 0xf0020008
+#define F367TER_DIR_CLK_216 0xf0020004
+#define F367TER_TUNER_BB 0xf0020002
+#define F367TER_DVBT_H 0xf0020001
+
+/* IOCFG0 */
+#define R367TER_IOCFG0 0xf003
+#define F367TER_OP0_SD 0xf0030080
+#define F367TER_OP0_VAL 0xf0030040
+#define F367TER_OP0_OD 0xf0030020
+#define F367TER_OP0_INV 0xf0030010
+#define F367TER_OP0_DACVALUE_HI 0xf003000f
+
+/* DAc0R */
+#define R367TER_DAC0R 0xf004
+#define F367TER_OP0_DACVALUE_LO 0xf00400ff
+
+/* IOCFG1 */
+#define R367TER_IOCFG1 0xf005
+#define F367TER_IP0 0xf0050040
+#define F367TER_OP1_OD 0xf0050020
+#define F367TER_OP1_INV 0xf0050010
+#define F367TER_OP1_DACVALUE_HI 0xf005000f
+
+/* DAC1R */
+#define R367TER_DAC1R 0xf006
+#define F367TER_OP1_DACVALUE_LO 0xf00600ff
+
+/* IOCFG2 */
+#define R367TER_IOCFG2 0xf007
+#define F367TER_OP2_LOCK_CONF 0xf00700e0
+#define F367TER_OP2_OD 0xf0070010
+#define F367TER_OP2_VAL 0xf0070008
+#define F367TER_OP1_LOCK_CONF 0xf0070007
+
+/* SDFR */
+#define R367TER_SDFR 0xf008
+#define F367TER_OP0_FREQ 0xf00800f0
+#define F367TER_OP1_FREQ 0xf008000f
+
+/* STATUS */
+#define R367TER_STATUS 0xf009
+#define F367TER_TPS_LOCK 0xf0090080
+#define F367TER_SYR_LOCK 0xf0090040
+#define F367TER_AGC_LOCK 0xf0090020
+#define F367TER_PRF 0xf0090010
+#define F367TER_LK 0xf0090008
+#define F367TER_PR 0xf0090007
+
+/* AUX_CLK */
+#define R367TER_AUX_CLK 0xf00a
+#define F367TER_AUXFEC_CTL 0xf00a00c0
+#define F367TER_DIS_CKX4 0xf00a0020
+#define F367TER_CKSEL 0xf00a0018
+#define F367TER_CKDIV_PROG 0xf00a0006
+#define F367TER_AUXCLK_ENA 0xf00a0001
+
+/* FREESYS1 */
+#define R367TER_FREESYS1 0xf00b
+#define F367TER_FREE_SYS1 0xf00b00ff
+
+/* FREESYS2 */
+#define R367TER_FREESYS2 0xf00c
+#define F367TER_FREE_SYS2 0xf00c00ff
+
+/* FREESYS3 */
+#define R367TER_FREESYS3 0xf00d
+#define F367TER_FREE_SYS3 0xf00d00ff
+
+/* GPIO_CFG */
+#define R367TER_GPIO_CFG 0xf00e
+#define F367TER_GPIO7_NOD 0xf00e0080
+#define F367TER_GPIO7_CFG 0xf00e0040
+#define F367TER_GPIO6_NOD 0xf00e0020
+#define F367TER_GPIO6_CFG 0xf00e0010
+#define F367TER_GPIO5_NOD 0xf00e0008
+#define F367TER_GPIO5_CFG 0xf00e0004
+#define F367TER_GPIO4_NOD 0xf00e0002
+#define F367TER_GPIO4_CFG 0xf00e0001
+
+/* GPIO_CMD */
+#define R367TER_GPIO_CMD 0xf00f
+#define F367TER_GPIO7_VAL 0xf00f0008
+#define F367TER_GPIO6_VAL 0xf00f0004
+#define F367TER_GPIO5_VAL 0xf00f0002
+#define F367TER_GPIO4_VAL 0xf00f0001
+
+/* AGC2MAX */
+#define R367TER_AGC2MAX 0xf010
+#define F367TER_AGC2_MAX 0xf01000ff
+
+/* AGC2MIN */
+#define R367TER_AGC2MIN 0xf011
+#define F367TER_AGC2_MIN 0xf01100ff
+
+/* AGC1MAX */
+#define R367TER_AGC1MAX 0xf012
+#define F367TER_AGC1_MAX 0xf01200ff
+
+/* AGC1MIN */
+#define R367TER_AGC1MIN 0xf013
+#define F367TER_AGC1_MIN 0xf01300ff
+
+/* AGCR */
+#define R367TER_AGCR 0xf014
+#define F367TER_RATIO_A 0xf01400e0
+#define F367TER_RATIO_B 0xf0140018
+#define F367TER_RATIO_C 0xf0140007
+
+/* AGC2TH */
+#define R367TER_AGC2TH 0xf015
+#define F367TER_AGC2_THRES 0xf01500ff
+
+/* AGC12c */
+#define R367TER_AGC12C 0xf016
+#define F367TER_AGC1_IV 0xf0160080
+#define F367TER_AGC1_OD 0xf0160040
+#define F367TER_AGC1_LOAD 0xf0160020
+#define F367TER_AGC2_IV 0xf0160010
+#define F367TER_AGC2_OD 0xf0160008
+#define F367TER_AGC2_LOAD 0xf0160004
+#define F367TER_AGC12_MODE 0xf0160003
+
+/* AGCCTRL1 */
+#define R367TER_AGCCTRL1 0xf017
+#define F367TER_DAGC_ON 0xf0170080
+#define F367TER_INVERT_AGC12 0xf0170040
+#define F367TER_AGC1_MODE 0xf0170008
+#define F367TER_AGC2_MODE 0xf0170007
+
+/* AGCCTRL2 */
+#define R367TER_AGCCTRL2 0xf018
+#define F367TER_FRZ2_CTRL 0xf0180060
+#define F367TER_FRZ1_CTRL 0xf0180018
+#define F367TER_TIME_CST 0xf0180007
+
+/* AGC1VAL1 */
+#define R367TER_AGC1VAL1 0xf019
+#define F367TER_AGC1_VAL_LO 0xf01900ff
+
+/* AGC1VAL2 */
+#define R367TER_AGC1VAL2 0xf01a
+#define F367TER_AGC1_VAL_HI 0xf01a000f
+
+/* AGC2VAL1 */
+#define R367TER_AGC2VAL1 0xf01b
+#define F367TER_AGC2_VAL_LO 0xf01b00ff
+
+/* AGC2VAL2 */
+#define R367TER_AGC2VAL2 0xf01c
+#define F367TER_AGC2_VAL_HI 0xf01c000f
+
+/* AGC2PGA */
+#define R367TER_AGC2PGA 0xf01d
+#define F367TER_AGC2_PGA 0xf01d00ff
+
+/* OVF_RATE1 */
+#define R367TER_OVF_RATE1 0xf01e
+#define F367TER_OVF_RATE_HI 0xf01e000f
+
+/* OVF_RATE2 */
+#define R367TER_OVF_RATE2 0xf01f
+#define F367TER_OVF_RATE_LO 0xf01f00ff
+
+/* GAIN_SRC1 */
+#define R367TER_GAIN_SRC1 0xf020
+#define F367TER_INV_SPECTR 0xf0200080
+#define F367TER_IQ_INVERT 0xf0200040
+#define F367TER_INR_BYPASS 0xf0200020
+#define F367TER_STATUS_INV_SPECRUM 0xf0200010
+#define F367TER_GAIN_SRC_HI 0xf020000f
+
+/* GAIN_SRC2 */
+#define R367TER_GAIN_SRC2 0xf021
+#define F367TER_GAIN_SRC_LO 0xf02100ff
+
+/* INC_DEROT1 */
+#define R367TER_INC_DEROT1 0xf022
+#define F367TER_INC_DEROT_HI 0xf02200ff
+
+/* INC_DEROT2 */
+#define R367TER_INC_DEROT2 0xf023
+#define F367TER_INC_DEROT_LO 0xf02300ff
+
+/* PPM_CPAMP_DIR */
+#define R367TER_PPM_CPAMP_DIR 0xf024
+#define F367TER_PPM_CPAMP_DIRECT 0xf02400ff
+
+/* PPM_CPAMP_INV */
+#define R367TER_PPM_CPAMP_INV 0xf025
+#define F367TER_PPM_CPAMP_INVER 0xf02500ff
+
+/* FREESTFE_1 */
+#define R367TER_FREESTFE_1 0xf026
+#define F367TER_SYMBOL_NUMBER_INC 0xf02600c0
+#define F367TER_SEL_LSB 0xf0260004
+#define F367TER_AVERAGE_ON 0xf0260002
+#define F367TER_DC_ADJ 0xf0260001
+
+/* FREESTFE_2 */
+#define R367TER_FREESTFE_2 0xf027
+#define F367TER_SEL_SRCOUT 0xf02700c0
+#define F367TER_SEL_SYRTHR 0xf027001f
+
+/* DCOFFSET */
+#define R367TER_DCOFFSET 0xf028
+#define F367TER_SELECT_I_Q 0xf0280080
+#define F367TER_DC_OFFSET 0xf028007f
+
+/* EN_PROCESS */
+#define R367TER_EN_PROCESS 0xf029
+#define F367TER_FREE 0xf02900f0
+#define F367TER_ENAB_MANUAL 0xf0290001
+
+/* SDI_SMOOTHER */
+#define R367TER_SDI_SMOOTHER 0xf02a
+#define F367TER_DIS_SMOOTH 0xf02a0080
+#define F367TER_SDI_INC_SMOOTHER 0xf02a007f
+
+/* FE_LOOP_OPEN */
+#define R367TER_FE_LOOP_OPEN 0xf02b
+#define F367TER_TRL_LOOP_OP 0xf02b0002
+#define F367TER_CRL_LOOP_OP 0xf02b0001
+
+/* FREQOFF1 */
+#define R367TER_FREQOFF1 0xf02c
+#define F367TER_FREQ_OFFSET_LOOP_OPEN_VHI 0xf02c00ff
+
+/* FREQOFF2 */
+#define R367TER_FREQOFF2 0xf02d
+#define F367TER_FREQ_OFFSET_LOOP_OPEN_HI 0xf02d00ff
+
+/* FREQOFF3 */
+#define R367TER_FREQOFF3 0xf02e
+#define F367TER_FREQ_OFFSET_LOOP_OPEN_LO 0xf02e00ff
+
+/* TIMOFF1 */
+#define R367TER_TIMOFF1 0xf02f
+#define F367TER_TIM_OFFSET_LOOP_OPEN_HI 0xf02f00ff
+
+/* TIMOFF2 */
+#define R367TER_TIMOFF2 0xf030
+#define F367TER_TIM_OFFSET_LOOP_OPEN_LO 0xf03000ff
+
+/* EPQ */
+#define R367TER_EPQ 0xf031
+#define F367TER_EPQ1 0xf03100ff
+
+/* EPQAUTO */
+#define R367TER_EPQAUTO 0xf032
+#define F367TER_EPQ2 0xf03200ff
+
+/* SYR_UPDATE */
+#define R367TER_SYR_UPDATE 0xf033
+#define F367TER_SYR_PROTV 0xf0330080
+#define F367TER_SYR_PROTV_GAIN 0xf0330060
+#define F367TER_SYR_FILTER 0xf0330010
+#define F367TER_SYR_TRACK_THRES 0xf033000c
+
+/* CHPFREE */
+#define R367TER_CHPFREE 0xf034
+#define F367TER_CHP_FREE 0xf03400ff
+
+/* PPM_STATE_MAC */
+#define R367TER_PPM_STATE_MAC 0xf035
+#define F367TER_PPM_STATE_MACHINE_DECODER 0xf035003f
+
+/* INR_THRESHOLD */
+#define R367TER_INR_THRESHOLD 0xf036
+#define F367TER_INR_THRESH 0xf03600ff
+
+/* EPQ_TPS_ID_CELL */
+#define R367TER_EPQ_TPS_ID_CELL 0xf037
+#define F367TER_ENABLE_LGTH_TO_CF 0xf0370080
+#define F367TER_DIS_TPS_RSVD 0xf0370040
+#define F367TER_DIS_BCH 0xf0370020
+#define F367TER_DIS_ID_CEL 0xf0370010
+#define F367TER_TPS_ADJUST_SYM 0xf037000f
+
+/* EPQ_CFG */
+#define R367TER_EPQ_CFG 0xf038
+#define F367TER_EPQ_RANGE 0xf0380002
+#define F367TER_EPQ_SOFT 0xf0380001
+
+/* EPQ_STATUS */
+#define R367TER_EPQ_STATUS 0xf039
+#define F367TER_SLOPE_INC 0xf03900fc
+#define F367TER_TPS_FIELD 0xf0390003
+
+/* AUTORELOCK */
+#define R367TER_AUTORELOCK 0xf03a
+#define F367TER_BYPASS_BER_TEMPO 0xf03a0080
+#define F367TER_BER_TEMPO 0xf03a0070
+#define F367TER_BYPASS_COFDM_TEMPO 0xf03a0008
+#define F367TER_COFDM_TEMPO 0xf03a0007
+
+/* BER_THR_VMSB */
+#define R367TER_BER_THR_VMSB 0xf03b
+#define F367TER_BER_THRESHOLD_HI 0xf03b00ff
+
+/* BER_THR_MSB */
+#define R367TER_BER_THR_MSB 0xf03c
+#define F367TER_BER_THRESHOLD_MID 0xf03c00ff
+
+/* BER_THR_LSB */
+#define R367TER_BER_THR_LSB 0xf03d
+#define F367TER_BER_THRESHOLD_LO 0xf03d00ff
+
+/* CCD */
+#define R367TER_CCD 0xf03e
+#define F367TER_CCD_DETECTED 0xf03e0080
+#define F367TER_CCD_RESET 0xf03e0040
+#define F367TER_CCD_THRESHOLD 0xf03e000f
+
+/* SPECTR_CFG */
+#define R367TER_SPECTR_CFG 0xf03f
+#define F367TER_SPECT_CFG 0xf03f0003
+
+/* CONSTMU_MSB */
+#define R367TER_CONSTMU_MSB 0xf040
+#define F367TER_CONSTMU_FREEZE 0xf0400080
+#define F367TER_CONSTNU_FORCE_EN 0xf0400040
+#define F367TER_CONST_MU_MSB 0xf040003f
+
+/* CONSTMU_LSB */
+#define R367TER_CONSTMU_LSB 0xf041
+#define F367TER_CONST_MU_LSB 0xf04100ff
+
+/* CONSTMU_MAX_MSB */
+#define R367TER_CONSTMU_MAX_MSB 0xf042
+#define F367TER_CONST_MU_MAX_MSB 0xf042003f
+
+/* CONSTMU_MAX_LSB */
+#define R367TER_CONSTMU_MAX_LSB 0xf043
+#define F367TER_CONST_MU_MAX_LSB 0xf04300ff
+
+/* ALPHANOISE */
+#define R367TER_ALPHANOISE 0xf044
+#define F367TER_USE_ALLFILTER 0xf0440080
+#define F367TER_INTER_ON 0xf0440040
+#define F367TER_ALPHA_NOISE 0xf044001f
+
+/* MAXGP_MSB */
+#define R367TER_MAXGP_MSB 0xf045
+#define F367TER_MUFILTER_LENGTH 0xf04500f0
+#define F367TER_MAX_GP_MSB 0xf045000f
+
+/* MAXGP_LSB */
+#define R367TER_MAXGP_LSB 0xf046
+#define F367TER_MAX_GP_LSB 0xf04600ff
+
+/* ALPHAMSB */
+#define R367TER_ALPHAMSB 0xf047
+#define F367TER_CHC_DATARATE 0xf04700c0
+#define F367TER_ALPHA_MSB 0xf047003f
+
+/* ALPHALSB */
+#define R367TER_ALPHALSB 0xf048
+#define F367TER_ALPHA_LSB 0xf04800ff
+
+/* PILOT_ACCU */
+#define R367TER_PILOT_ACCU 0xf049
+#define F367TER_USE_SCAT4ADDAPT 0xf0490080
+#define F367TER_PILOT_ACC 0xf049001f
+
+/* PILOTMU_ACCU */
+#define R367TER_PILOTMU_ACCU 0xf04a
+#define F367TER_DISCARD_BAD_SP 0xf04a0080
+#define F367TER_DISCARD_BAD_CP 0xf04a0040
+#define F367TER_PILOT_MU_ACCU 0xf04a001f
+
+/* FILT_CHANNEL_EST */
+#define R367TER_FILT_CHANNEL_EST 0xf04b
+#define F367TER_USE_FILT_PILOT 0xf04b0080
+#define F367TER_FILT_CHANNEL 0xf04b007f
+
+/* ALPHA_NOPISE_FREQ */
+#define R367TER_ALPHA_NOPISE_FREQ 0xf04c
+#define F367TER_NOISE_FREQ_FILT 0xf04c0040
+#define F367TER_ALPHA_NOISE_FREQ 0xf04c003f
+
+/* RATIO_PILOT */
+#define R367TER_RATIO_PILOT 0xf04d
+#define F367TER_RATIO_MEAN_SP 0xf04d00f0
+#define F367TER_RATIO_MEAN_CP 0xf04d000f
+
+/* CHC_CTL */
+#define R367TER_CHC_CTL 0xf04e
+#define F367TER_TRACK_EN 0xf04e0080
+#define F367TER_NOISE_NORM_EN 0xf04e0040
+#define F367TER_FORCE_CHC_RESET 0xf04e0020
+#define F367TER_SHORT_TIME 0xf04e0010
+#define F367TER_FORCE_STATE_EN 0xf04e0008
+#define F367TER_FORCE_STATE 0xf04e0007
+
+/* EPQ_ADJUST */
+#define R367TER_EPQ_ADJUST 0xf04f
+#define F367TER_ADJUST_SCAT_IND 0xf04f00c0
+#define F367TER_ONE_SYMBOL 0xf04f0010
+#define F367TER_EPQ_DECAY 0xf04f000e
+#define F367TER_HOLD_SLOPE 0xf04f0001
+
+/* EPQ_THRES */
+#define R367TER_EPQ_THRES 0xf050
+#define F367TER_EPQ_THR 0xf05000ff
+
+/* OMEGA_CTL */
+#define R367TER_OMEGA_CTL 0xf051
+#define F367TER_OMEGA_RST 0xf0510080
+#define F367TER_FREEZE_OMEGA 0xf0510040
+#define F367TER_OMEGA_SEL 0xf051003f
+
+/* GP_CTL */
+#define R367TER_GP_CTL 0xf052
+#define F367TER_CHC_STATE 0xf05200e0
+#define F367TER_FREEZE_GP 0xf0520010
+#define F367TER_GP_SEL 0xf052000f
+
+/* MUMSB */
+#define R367TER_MUMSB 0xf053
+#define F367TER_MU_MSB 0xf053007f
+
+/* MULSB */
+#define R367TER_MULSB 0xf054
+#define F367TER_MU_LSB 0xf05400ff
+
+/* GPMSB */
+#define R367TER_GPMSB 0xf055
+#define F367TER_CSI_THRESHOLD 0xf05500e0
+#define F367TER_GP_MSB 0xf055000f
+
+/* GPLSB */
+#define R367TER_GPLSB 0xf056
+#define F367TER_GP_LSB 0xf05600ff
+
+/* OMEGAMSB */
+#define R367TER_OMEGAMSB 0xf057
+#define F367TER_OMEGA_MSB 0xf057007f
+
+/* OMEGALSB */
+#define R367TER_OMEGALSB 0xf058
+#define F367TER_OMEGA_LSB 0xf05800ff
+
+/* SCAT_NB */
+#define R367TER_SCAT_NB 0xf059
+#define F367TER_CHC_TEST 0xf05900f8
+#define F367TER_SCAT_NUMB 0xf0590003
+
+/* CHC_DUMMY */
+#define R367TER_CHC_DUMMY 0xf05a
+#define F367TER_CHC_DUM 0xf05a00ff
+
+/* INC_CTL */
+#define R367TER_INC_CTL 0xf05b
+#define F367TER_INC_BYPASS 0xf05b0080
+#define F367TER_INC_NDEPTH 0xf05b000c
+#define F367TER_INC_MADEPTH 0xf05b0003
+
+/* INCTHRES_COR1 */
+#define R367TER_INCTHRES_COR1 0xf05c
+#define F367TER_INC_THRES_COR1 0xf05c00ff
+
+/* INCTHRES_COR2 */
+#define R367TER_INCTHRES_COR2 0xf05d
+#define F367TER_INC_THRES_COR2 0xf05d00ff
+
+/* INCTHRES_DET1 */
+#define R367TER_INCTHRES_DET1 0xf05e
+#define F367TER_INC_THRES_DET1 0xf05e003f
+
+/* INCTHRES_DET2 */
+#define R367TER_INCTHRES_DET2 0xf05f
+#define F367TER_INC_THRES_DET2 0xf05f003f
+
+/* IIR_CELLNB */
+#define R367TER_IIR_CELLNB 0xf060
+#define F367TER_NRST_IIR 0xf0600080
+#define F367TER_IIR_CELL_NB 0xf0600007
+
+/* IIRCX_COEFF1_MSB */
+#define R367TER_IIRCX_COEFF1_MSB 0xf061
+#define F367TER_IIR_CX_COEFF1_MSB 0xf06100ff
+
+/* IIRCX_COEFF1_LSB */
+#define R367TER_IIRCX_COEFF1_LSB 0xf062
+#define F367TER_IIR_CX_COEFF1_LSB 0xf06200ff
+
+/* IIRCX_COEFF2_MSB */
+#define R367TER_IIRCX_COEFF2_MSB 0xf063
+#define F367TER_IIR_CX_COEFF2_MSB 0xf06300ff
+
+/* IIRCX_COEFF2_LSB */
+#define R367TER_IIRCX_COEFF2_LSB 0xf064
+#define F367TER_IIR_CX_COEFF2_LSB 0xf06400ff
+
+/* IIRCX_COEFF3_MSB */
+#define R367TER_IIRCX_COEFF3_MSB 0xf065
+#define F367TER_IIR_CX_COEFF3_MSB 0xf06500ff
+
+/* IIRCX_COEFF3_LSB */
+#define R367TER_IIRCX_COEFF3_LSB 0xf066
+#define F367TER_IIR_CX_COEFF3_LSB 0xf06600ff
+
+/* IIRCX_COEFF4_MSB */
+#define R367TER_IIRCX_COEFF4_MSB 0xf067
+#define F367TER_IIR_CX_COEFF4_MSB 0xf06700ff
+
+/* IIRCX_COEFF4_LSB */
+#define R367TER_IIRCX_COEFF4_LSB 0xf068
+#define F367TER_IIR_CX_COEFF4_LSB 0xf06800ff
+
+/* IIRCX_COEFF5_MSB */
+#define R367TER_IIRCX_COEFF5_MSB 0xf069
+#define F367TER_IIR_CX_COEFF5_MSB 0xf06900ff
+
+/* IIRCX_COEFF5_LSB */
+#define R367TER_IIRCX_COEFF5_LSB 0xf06a
+#define F367TER_IIR_CX_COEFF5_LSB 0xf06a00ff
+
+/* FEPATH_CFG */
+#define R367TER_FEPATH_CFG 0xf06b
+#define F367TER_DEMUX_SWAP 0xf06b0004
+#define F367TER_DIGAGC_SWAP 0xf06b0002
+#define F367TER_LONGPATH_IF 0xf06b0001
+
+/* PMC1_FUNC */
+#define R367TER_PMC1_FUNC 0xf06c
+#define F367TER_SOFT_RSTN 0xf06c0080
+#define F367TER_PMC1_AVERAGE_TIME 0xf06c0078
+#define F367TER_PMC1_WAIT_TIME 0xf06c0006
+#define F367TER_PMC1_2N_SEL 0xf06c0001
+
+/* PMC1_FOR */
+#define R367TER_PMC1_FOR 0xf06d
+#define F367TER_PMC1_FORCE 0xf06d0080
+#define F367TER_PMC1_FORCE_VALUE 0xf06d007c
+
+/* PMC2_FUNC */
+#define R367TER_PMC2_FUNC 0xf06e
+#define F367TER_PMC2_SOFT_STN 0xf06e0080
+#define F367TER_PMC2_ACCU_TIME 0xf06e0070
+#define F367TER_PMC2_CMDP_MN 0xf06e0008
+#define F367TER_PMC2_SWAP 0xf06e0004
+
+/* STATUS_ERR_DA */
+#define R367TER_STATUS_ERR_DA 0xf06f
+#define F367TER_COM_USEGAINTRK 0xf06f0080
+#define F367TER_COM_AGCLOCK 0xf06f0040
+#define F367TER_AUT_AGCLOCK 0xf06f0020
+#define F367TER_MIN_ERR_X_LSB 0xf06f000f
+
+/* DIG_AGC_R */
+#define R367TER_DIG_AGC_R 0xf070
+#define F367TER_COM_SOFT_RSTN 0xf0700080
+#define F367TER_COM_AGC_ON 0xf0700040
+#define F367TER_COM_EARLY 0xf0700020
+#define F367TER_AUT_SOFT_RESETN 0xf0700010
+#define F367TER_AUT_AGC_ON 0xf0700008
+#define F367TER_AUT_EARLY 0xf0700004
+#define F367TER_AUT_ROT_EN 0xf0700002
+#define F367TER_LOCK_SOFT_RESETN 0xf0700001
+
+/* COMAGC_TARMSB */
+#define R367TER_COMAGC_TARMSB 0xf071
+#define F367TER_COM_AGC_TARGET_MSB 0xf07100ff
+
+/* COM_AGC_TAR_ENMODE */
+#define R367TER_COM_AGC_TAR_ENMODE 0xf072
+#define F367TER_COM_AGC_TARGET_LSB 0xf07200f0
+#define F367TER_COM_ENMODE 0xf072000f
+
+/* COM_AGC_CFG */
+#define R367TER_COM_AGC_CFG 0xf073
+#define F367TER_COM_N 0xf07300f8
+#define F367TER_COM_STABMODE 0xf0730006
+#define F367TER_ERR_SEL 0xf0730001
+
+/* COM_AGC_GAIN1 */
+#define R367TER_COM_AGC_GAIN1 0xf074
+#define F367TER_COM_GAIN1aCK 0xf07400f0
+#define F367TER_COM_GAIN1TRK 0xf074000f
+
+/* AUT_AGC_TARGETMSB */
+#define R367TER_AUT_AGC_TARGETMSB 0xf075
+#define F367TER_AUT_AGC_TARGET_MSB 0xf07500ff
+
+/* LOCK_DET_MSB */
+#define R367TER_LOCK_DET_MSB 0xf076
+#define F367TER_LOCK_DETECT_MSB 0xf07600ff
+
+/* AGCTAR_LOCK_LSBS */
+#define R367TER_AGCTAR_LOCK_LSBS 0xf077
+#define F367TER_AUT_AGC_TARGET_LSB 0xf07700f0
+#define F367TER_LOCK_DETECT_LSB 0xf077000f
+
+/* AUT_GAIN_EN */
+#define R367TER_AUT_GAIN_EN 0xf078
+#define F367TER_AUT_ENMODE 0xf07800f0
+#define F367TER_AUT_GAIN2 0xf078000f
+
+/* AUT_CFG */
+#define R367TER_AUT_CFG 0xf079
+#define F367TER_AUT_N 0xf07900f8
+#define F367TER_INT_CHOICE 0xf0790006
+#define F367TER_INT_LOAD 0xf0790001
+
+/* LOCKN */
+#define R367TER_LOCKN 0xf07a
+#define F367TER_LOCK_N 0xf07a00f8
+#define F367TER_SEL_IQNTAR 0xf07a0004
+#define F367TER_LOCK_DETECT_CHOICE 0xf07a0003
+
+/* INT_X_3 */
+#define R367TER_INT_X_3 0xf07b
+#define F367TER_INT_X3 0xf07b00ff
+
+/* INT_X_2 */
+#define R367TER_INT_X_2 0xf07c
+#define F367TER_INT_X2 0xf07c00ff
+
+/* INT_X_1 */
+#define R367TER_INT_X_1 0xf07d
+#define F367TER_INT_X1 0xf07d00ff
+
+/* INT_X_0 */
+#define R367TER_INT_X_0 0xf07e
+#define F367TER_INT_X0 0xf07e00ff
+
+/* MIN_ERRX_MSB */
+#define R367TER_MIN_ERRX_MSB 0xf07f
+#define F367TER_MIN_ERR_X_MSB 0xf07f00ff
+
+/* COR_CTL */
+#define R367TER_COR_CTL 0xf080
+#define F367TER_CORE_ACTIVE 0xf0800020
+#define F367TER_HOLD 0xf0800010
+#define F367TER_CORE_STATE_CTL 0xf080000f
+
+/* COR_STAT */
+#define R367TER_COR_STAT 0xf081
+#define F367TER_SCATT_LOCKED 0xf0810080
+#define F367TER_TPS_LOCKED 0xf0810040
+#define F367TER_SYR_LOCKED_COR 0xf0810020
+#define F367TER_AGC_LOCKED_STAT 0xf0810010
+#define F367TER_CORE_STATE_STAT 0xf081000f
+
+/* COR_INTEN */
+#define R367TER_COR_INTEN 0xf082
+#define F367TER_INTEN 0xf0820080
+#define F367TER_INTEN_SYR 0xf0820020
+#define F367TER_INTEN_FFT 0xf0820010
+#define F367TER_INTEN_AGC 0xf0820008
+#define F367TER_INTEN_TPS1 0xf0820004
+#define F367TER_INTEN_TPS2 0xf0820002
+#define F367TER_INTEN_TPS3 0xf0820001
+
+/* COR_INTSTAT */
+#define R367TER_COR_INTSTAT 0xf083
+#define F367TER_INTSTAT_SYR 0xf0830020
+#define F367TER_INTSTAT_FFT 0xf0830010
+#define F367TER_INTSAT_AGC 0xf0830008
+#define F367TER_INTSTAT_TPS1 0xf0830004
+#define F367TER_INTSTAT_TPS2 0xf0830002
+#define F367TER_INTSTAT_TPS3 0xf0830001
+
+/* COR_MODEGUARD */
+#define R367TER_COR_MODEGUARD 0xf084
+#define F367TER_FORCE 0xf0840010
+#define F367TER_MODE 0xf084000c
+#define F367TER_GUARD 0xf0840003
+
+/* AGC_CTL */
+#define R367TER_AGC_CTL 0xf085
+#define F367TER_AGC_TIMING_FACTOR 0xf08500e0
+#define F367TER_AGC_LAST 0xf0850010
+#define F367TER_AGC_GAIN 0xf085000c
+#define F367TER_AGC_NEG 0xf0850002
+#define F367TER_AGC_SET 0xf0850001
+
+/* AGC_MANUAL1 */
+#define R367TER_AGC_MANUAL1 0xf086
+#define F367TER_AGC_VAL_LO 0xf08600ff
+
+/* AGC_MANUAL2 */
+#define R367TER_AGC_MANUAL2 0xf087
+#define F367TER_AGC_VAL_HI 0xf087000f
+
+/* AGC_TARG */
+#define R367TER_AGC_TARG 0xf088
+#define F367TER_AGC_TARGET 0xf08800ff
+
+/* AGC_GAIN1 */
+#define R367TER_AGC_GAIN1 0xf089
+#define F367TER_AGC_GAIN_LO 0xf08900ff
+
+/* AGC_GAIN2 */
+#define R367TER_AGC_GAIN2 0xf08a
+#define F367TER_AGC_LOCKED_GAIN2 0xf08a0010
+#define F367TER_AGC_GAIN_HI 0xf08a000f
+
+/* RESERVED_1 */
+#define R367TER_RESERVED_1 0xf08b
+#define F367TER_RESERVED1 0xf08b00ff
+
+/* RESERVED_2 */
+#define R367TER_RESERVED_2 0xf08c
+#define F367TER_RESERVED2 0xf08c00ff
+
+/* RESERVED_3 */
+#define R367TER_RESERVED_3 0xf08d
+#define F367TER_RESERVED3 0xf08d00ff
+
+/* CAS_CTL */
+#define R367TER_CAS_CTL 0xf08e
+#define F367TER_CCS_ENABLE 0xf08e0080
+#define F367TER_ACS_DISABLE 0xf08e0040
+#define F367TER_DAGC_DIS 0xf08e0020
+#define F367TER_DAGC_GAIN 0xf08e0018
+#define F367TER_CCSMU 0xf08e0007
+
+/* CAS_FREQ */
+#define R367TER_CAS_FREQ 0xf08f
+#define F367TER_CCS_FREQ 0xf08f00ff
+
+/* CAS_DAGCGAIN */
+#define R367TER_CAS_DAGCGAIN 0xf090
+#define F367TER_CAS_DAGC_GAIN 0xf09000ff
+
+/* SYR_CTL */
+#define R367TER_SYR_CTL 0xf091
+#define F367TER_SICTH_ENABLE 0xf0910080
+#define F367TER_LONG_ECHO 0xf0910078
+#define F367TER_AUTO_LE_EN 0xf0910004
+#define F367TER_SYR_BYPASS 0xf0910002
+#define F367TER_SYR_TR_DIS 0xf0910001
+
+/* SYR_STAT */
+#define R367TER_SYR_STAT 0xf092
+#define F367TER_SYR_LOCKED_STAT 0xf0920010
+#define F367TER_SYR_MODE 0xf092000c
+#define F367TER_SYR_GUARD 0xf0920003
+
+/* SYR_NCO1 */
+#define R367TER_SYR_NCO1 0xf093
+#define F367TER_SYR_NCO_LO 0xf09300ff
+
+/* SYR_NCO2 */
+#define R367TER_SYR_NCO2 0xf094
+#define F367TER_SYR_NCO_HI 0xf094003f
+
+/* SYR_OFFSET1 */
+#define R367TER_SYR_OFFSET1 0xf095
+#define F367TER_SYR_OFFSET_LO 0xf09500ff
+
+/* SYR_OFFSET2 */
+#define R367TER_SYR_OFFSET2 0xf096
+#define F367TER_SYR_OFFSET_HI 0xf096003f
+
+/* FFT_CTL */
+#define R367TER_FFT_CTL 0xf097
+#define F367TER_SHIFT_FFT_TRIG 0xf0970018
+#define F367TER_FFT_TRIGGER 0xf0970004
+#define F367TER_FFT_MANUAL 0xf0970002
+#define F367TER_IFFT_MODE 0xf0970001
+
+/* SCR_CTL */
+#define R367TER_SCR_CTL 0xf098
+#define F367TER_SYRADJDECAY 0xf0980070
+#define F367TER_SCR_CPEDIS 0xf0980002
+#define F367TER_SCR_DIS 0xf0980001
+
+/* PPM_CTL1 */
+#define R367TER_PPM_CTL1 0xf099
+#define F367TER_PPM_MAXFREQ 0xf0990030
+#define F367TER_PPM_MAXTIM 0xf0990008
+#define F367TER_PPM_INVSEL 0xf0990004
+#define F367TER_PPM_SCATDIS 0xf0990002
+#define F367TER_PPM_BYP 0xf0990001
+
+/* TRL_CTL */
+#define R367TER_TRL_CTL 0xf09a
+#define F367TER_TRL_NOMRATE_LSB 0xf09a0080
+#define F367TER_TRL_GAIN_FACTOR 0xf09a0078
+#define F367TER_TRL_LOOPGAIN 0xf09a0007
+
+/* TRL_NOMRATE1 */
+#define R367TER_TRL_NOMRATE1 0xf09b
+#define F367TER_TRL_NOMRATE_LO 0xf09b00ff
+
+/* TRL_NOMRATE2 */
+#define R367TER_TRL_NOMRATE2 0xf09c
+#define F367TER_TRL_NOMRATE_HI 0xf09c00ff
+
+/* TRL_TIME1 */
+#define R367TER_TRL_TIME1 0xf09d
+#define F367TER_TRL_TOFFSET_LO 0xf09d00ff
+
+/* TRL_TIME2 */
+#define R367TER_TRL_TIME2 0xf09e
+#define F367TER_TRL_TOFFSET_HI 0xf09e00ff
+
+/* CRL_CTL */
+#define R367TER_CRL_CTL 0xf09f
+#define F367TER_CRL_DIS 0xf09f0080
+#define F367TER_CRL_GAIN_FACTOR 0xf09f0078
+#define F367TER_CRL_LOOPGAIN 0xf09f0007
+
+/* CRL_FREQ1 */
+#define R367TER_CRL_FREQ1 0xf0a0
+#define F367TER_CRL_FOFFSET_LO 0xf0a000ff
+
+/* CRL_FREQ2 */
+#define R367TER_CRL_FREQ2 0xf0a1
+#define F367TER_CRL_FOFFSET_HI 0xf0a100ff
+
+/* CRL_FREQ3 */
+#define R367TER_CRL_FREQ3 0xf0a2
+#define F367TER_CRL_FOFFSET_VHI 0xf0a200ff
+
+/* TPS_SFRAME_CTL */
+#define R367TER_TPS_SFRAME_CTL 0xf0a3
+#define F367TER_TPS_SFRAME_SYNC 0xf0a30001
+
+/* CHC_SNR */
+#define R367TER_CHC_SNR 0xf0a4
+#define F367TER_CHCSNR 0xf0a400ff
+
+/* BDI_CTL */
+#define R367TER_BDI_CTL 0xf0a5
+#define F367TER_BDI_LPSEL 0xf0a50002
+#define F367TER_BDI_SERIAL 0xf0a50001
+
+/* DMP_CTL */
+#define R367TER_DMP_CTL 0xf0a6
+#define F367TER_DMP_SCALING_FACTOR 0xf0a6001e
+#define F367TER_DMP_SDDIS 0xf0a60001
+
+/* TPS_RCVD1 */
+#define R367TER_TPS_RCVD1 0xf0a7
+#define F367TER_TPS_CHANGE 0xf0a70040
+#define F367TER_BCH_OK 0xf0a70020
+#define F367TER_TPS_SYNC 0xf0a70010
+#define F367TER_TPS_FRAME 0xf0a70003
+
+/* TPS_RCVD2 */
+#define R367TER_TPS_RCVD2 0xf0a8
+#define F367TER_TPS_HIERMODE 0xf0a80070
+#define F367TER_TPS_CONST 0xf0a80003
+
+/* TPS_RCVD3 */
+#define R367TER_TPS_RCVD3 0xf0a9
+#define F367TER_TPS_LPCODE 0xf0a90070
+#define F367TER_TPS_HPCODE 0xf0a90007
+
+/* TPS_RCVD4 */
+#define R367TER_TPS_RCVD4 0xf0aa
+#define F367TER_TPS_GUARD 0xf0aa0030
+#define F367TER_TPS_MODE 0xf0aa0003
+
+/* TPS_ID_CELL1 */
+#define R367TER_TPS_ID_CELL1 0xf0ab
+#define F367TER_TPS_ID_CELL_LO 0xf0ab00ff
+
+/* TPS_ID_CELL2 */
+#define R367TER_TPS_ID_CELL2 0xf0ac
+#define F367TER_TPS_ID_CELL_HI 0xf0ac00ff
+
+/* TPS_RCVD5_SET1 */
+#define R367TER_TPS_RCVD5_SET1 0xf0ad
+#define F367TER_TPS_NA 0xf0ad00fC
+#define F367TER_TPS_SETFRAME 0xf0ad0003
+
+/* TPS_SET2 */
+#define R367TER_TPS_SET2 0xf0ae
+#define F367TER_TPS_SETHIERMODE 0xf0ae0070
+#define F367TER_TPS_SETCONST 0xf0ae0003
+
+/* TPS_SET3 */
+#define R367TER_TPS_SET3 0xf0af
+#define F367TER_TPS_SETLPCODE 0xf0af0070
+#define F367TER_TPS_SETHPCODE 0xf0af0007
+
+/* TPS_CTL */
+#define R367TER_TPS_CTL 0xf0b0
+#define F367TER_TPS_IMM 0xf0b00004
+#define F367TER_TPS_BCHDIS 0xf0b00002
+#define F367TER_TPS_UPDDIS 0xf0b00001
+
+/* CTL_FFTOSNUM */
+#define R367TER_CTL_FFTOSNUM 0xf0b1
+#define F367TER_SYMBOL_NUMBER 0xf0b1007f
+
+/* TESTSELECT */
+#define R367TER_TESTSELECT 0xf0b2
+#define F367TER_TEST_SELECT 0xf0b2001f
+
+/* MSC_REV */
+#define R367TER_MSC_REV 0xf0b3
+#define F367TER_REV_NUMBER 0xf0b300ff
+
+/* PIR_CTL */
+#define R367TER_PIR_CTL 0xf0b4
+#define F367TER_FREEZE 0xf0b40001
+
+/* SNR_CARRIER1 */
+#define R367TER_SNR_CARRIER1 0xf0b5
+#define F367TER_SNR_CARRIER_LO 0xf0b500ff
+
+/* SNR_CARRIER2 */
+#define R367TER_SNR_CARRIER2 0xf0b6
+#define F367TER_MEAN 0xf0b600c0
+#define F367TER_SNR_CARRIER_HI 0xf0b6001f
+
+/* PPM_CPAMP */
+#define R367TER_PPM_CPAMP 0xf0b7
+#define F367TER_PPM_CPC 0xf0b700ff
+
+/* TSM_AP0 */
+#define R367TER_TSM_AP0 0xf0b8
+#define F367TER_ADDRESS_BYTE_0 0xf0b800ff
+
+/* TSM_AP1 */
+#define R367TER_TSM_AP1 0xf0b9
+#define F367TER_ADDRESS_BYTE_1 0xf0b900ff
+
+/* TSM_AP2 */
+#define R367TER_TSM_AP2 0xf0bA
+#define F367TER_DATA_BYTE_0 0xf0ba00ff
+
+/* TSM_AP3 */
+#define R367TER_TSM_AP3 0xf0bB
+#define F367TER_DATA_BYTE_1 0xf0bb00ff
+
+/* TSM_AP4 */
+#define R367TER_TSM_AP4 0xf0bC
+#define F367TER_DATA_BYTE_2 0xf0bc00ff
+
+/* TSM_AP5 */
+#define R367TER_TSM_AP5 0xf0bD
+#define F367TER_DATA_BYTE_3 0xf0bd00ff
+
+/* TSM_AP6 */
+#define R367TER_TSM_AP6 0xf0bE
+#define F367TER_TSM_AP_6 0xf0be00ff
+
+/* TSM_AP7 */
+#define R367TER_TSM_AP7 0xf0bF
+#define F367TER_MEM_SELECT_BYTE 0xf0bf00ff
+
+/* TSTRES */
+#define R367TER_TSTRES 0xf0c0
+#define F367TER_FRES_DISPLAY 0xf0c00080
+#define F367TER_FRES_FIFO_AD 0xf0c00020
+#define F367TER_FRESRS 0xf0c00010
+#define F367TER_FRESACS 0xf0c00008
+#define F367TER_FRESFEC 0xf0c00004
+#define F367TER_FRES_PRIF 0xf0c00002
+#define F367TER_FRESCORE 0xf0c00001
+
+/* ANACTRL */
+#define R367TER_ANACTRL 0xf0c1
+#define F367TER_BYPASS_XTAL 0xf0c10040
+#define F367TER_BYPASS_PLLXN 0xf0c1000c
+#define F367TER_DIS_PAD_OSC 0xf0c10002
+#define F367TER_STDBY_PLLXN 0xf0c10001
+
+/* TSTBUS */
+#define R367TER_TSTBUS 0xf0c2
+#define F367TER_TS_BYTE_CLK_INV 0xf0c20080
+#define F367TER_CFG_IP 0xf0c20070
+#define F367TER_CFG_TST 0xf0c2000f
+
+/* TSTRATE */
+#define R367TER_TSTRATE 0xf0c6
+#define F367TER_FORCEPHA 0xf0c60080
+#define F367TER_FNEWPHA 0xf0c60010
+#define F367TER_FROT90 0xf0c60008
+#define F367TER_FR 0xf0c60007
+
+/* CONSTMODE */
+#define R367TER_CONSTMODE 0xf0cb
+#define F367TER_TST_PRIF 0xf0cb00e0
+#define F367TER_CAR_TYPE 0xf0cb0018
+#define F367TER_CONST_MODE 0xf0cb0003
+
+/* CONSTCARR1 */
+#define R367TER_CONSTCARR1 0xf0cc
+#define F367TER_CONST_CARR_LO 0xf0cc00ff
+
+/* CONSTCARR2 */
+#define R367TER_CONSTCARR2 0xf0cd
+#define F367TER_CONST_CARR_HI 0xf0cd001f
+
+/* ICONSTEL */
+#define R367TER_ICONSTEL 0xf0ce
+#define F367TER_PICONSTEL 0xf0ce00ff
+
+/* QCONSTEL */
+#define R367TER_QCONSTEL 0xf0cf
+#define F367TER_PQCONSTEL 0xf0cf00ff
+
+/* TSTBISTRES0 */
+#define R367TER_TSTBISTRES0 0xf0d0
+#define F367TER_BEND_PPM 0xf0d00080
+#define F367TER_BBAD_PPM 0xf0d00040
+#define F367TER_BEND_FFTW 0xf0d00020
+#define F367TER_BBAD_FFTW 0xf0d00010
+#define F367TER_BEND_FFT_BUF 0xf0d00008
+#define F367TER_BBAD_FFT_BUF 0xf0d00004
+#define F367TER_BEND_SYR 0xf0d00002
+#define F367TER_BBAD_SYR 0xf0d00001
+
+/* TSTBISTRES1 */
+#define R367TER_TSTBISTRES1 0xf0d1
+#define F367TER_BEND_CHC_CP 0xf0d10080
+#define F367TER_BBAD_CHC_CP 0xf0d10040
+#define F367TER_BEND_CHCI 0xf0d10020
+#define F367TER_BBAD_CHCI 0xf0d10010
+#define F367TER_BEND_BDI 0xf0d10008
+#define F367TER_BBAD_BDI 0xf0d10004
+#define F367TER_BEND_SDI 0xf0d10002
+#define F367TER_BBAD_SDI 0xf0d10001
+
+/* TSTBISTRES2 */
+#define R367TER_TSTBISTRES2 0xf0d2
+#define F367TER_BEND_CHC_INC 0xf0d20080
+#define F367TER_BBAD_CHC_INC 0xf0d20040
+#define F367TER_BEND_CHC_SPP 0xf0d20020
+#define F367TER_BBAD_CHC_SPP 0xf0d20010
+#define F367TER_BEND_CHC_CPP 0xf0d20008
+#define F367TER_BBAD_CHC_CPP 0xf0d20004
+#define F367TER_BEND_CHC_SP 0xf0d20002
+#define F367TER_BBAD_CHC_SP 0xf0d20001
+
+/* TSTBISTRES3 */
+#define R367TER_TSTBISTRES3 0xf0d3
+#define F367TER_BEND_QAM 0xf0d30080
+#define F367TER_BBAD_QAM 0xf0d30040
+#define F367TER_BEND_SFEC_VIT 0xf0d30020
+#define F367TER_BBAD_SFEC_VIT 0xf0d30010
+#define F367TER_BEND_SFEC_DLINE 0xf0d30008
+#define F367TER_BBAD_SFEC_DLINE 0xf0d30004
+#define F367TER_BEND_SFEC_HW 0xf0d30002
+#define F367TER_BBAD_SFEC_HW 0xf0d30001
+
+/* RF_AGC1 */
+#define R367TER_RF_AGC1 0xf0d4
+#define F367TER_RF_AGC1_LEVEL_HI 0xf0d400ff
+
+/* RF_AGC2 */
+#define R367TER_RF_AGC2 0xf0d5
+#define F367TER_REF_ADGP 0xf0d50080
+#define F367TER_STDBY_ADCGP 0xf0d50020
+#define F367TER_CHANNEL_SEL 0xf0d5001c
+#define F367TER_RF_AGC1_LEVEL_LO 0xf0d50003
+
+/* ANADIGCTRL */
+#define R367TER_ANADIGCTRL 0xf0d7
+#define F367TER_SEL_CLKDEM 0xf0d70020
+#define F367TER_EN_BUFFER_Q 0xf0d70010
+#define F367TER_EN_BUFFER_I 0xf0d70008
+#define F367TER_ADC_RIS_EGDE 0xf0d70004
+#define F367TER_SGN_ADC 0xf0d70002
+#define F367TER_SEL_AD12_SYNC 0xf0d70001
+
+/* PLLMDIV */
+#define R367TER_PLLMDIV 0xf0d8
+#define F367TER_PLL_MDIV 0xf0d800ff
+
+/* PLLNDIV */
+#define R367TER_PLLNDIV 0xf0d9
+#define F367TER_PLL_NDIV 0xf0d900ff
+
+/* PLLSETUP */
+#define R367TER_PLLSETUP 0xf0dA
+#define F367TER_PLL_PDIV 0xf0da0070
+#define F367TER_PLL_KDIV 0xf0da000f
+
+/* DUAL_AD12 */
+#define R367TER_DUAL_AD12 0xf0dB
+#define F367TER_FS20M 0xf0db0020
+#define F367TER_FS50M 0xf0db0010
+#define F367TER_INMODe0 0xf0db0008
+#define F367TER_POFFQ 0xf0db0004
+#define F367TER_POFFI 0xf0db0002
+#define F367TER_INMODE1 0xf0db0001
+
+/* TSTBIST */
+#define R367TER_TSTBIST 0xf0dC
+#define F367TER_TST_BYP_CLK 0xf0dc0080
+#define F367TER_TST_GCLKENA_STD 0xf0dc0040
+#define F367TER_TST_GCLKENA 0xf0dc0020
+#define F367TER_TST_MEMBIST 0xf0dc001f
+
+/* PAD_COMP_CTRL */
+#define R367TER_PAD_COMP_CTRL 0xf0dD
+#define F367TER_COMPTQ 0xf0dd0010
+#define F367TER_COMPEN 0xf0dd0008
+#define F367TER_FREEZE2 0xf0dd0004
+#define F367TER_SLEEP_INHBT 0xf0dd0002
+#define F367TER_CHIP_SLEEP 0xf0dd0001
+
+/* PAD_COMP_WR */
+#define R367TER_PAD_COMP_WR 0xf0de
+#define F367TER_WR_ASRC 0xf0de007f
+
+/* PAD_COMP_RD */
+#define R367TER_PAD_COMP_RD 0xf0df
+#define F367TER_COMPOK 0xf0df0080
+#define F367TER_RD_ASRC 0xf0df007f
+
+/* SYR_TARGET_FFTADJT_MSB */
+#define R367TER_SYR_TARGET_FFTADJT_MSB 0xf100
+#define F367TER_SYR_START 0xf1000080
+#define F367TER_SYR_TARGET_FFTADJ_HI 0xf100000f
+
+/* SYR_TARGET_FFTADJT_LSB */
+#define R367TER_SYR_TARGET_FFTADJT_LSB 0xf101
+#define F367TER_SYR_TARGET_FFTADJ_LO 0xf10100ff
+
+/* SYR_TARGET_CHCADJT_MSB */
+#define R367TER_SYR_TARGET_CHCADJT_MSB 0xf102
+#define F367TER_SYR_TARGET_CHCADJ_HI 0xf102000f
+
+/* SYR_TARGET_CHCADJT_LSB */
+#define R367TER_SYR_TARGET_CHCADJT_LSB 0xf103
+#define F367TER_SYR_TARGET_CHCADJ_LO 0xf10300ff
+
+/* SYR_FLAG */
+#define R367TER_SYR_FLAG 0xf104
+#define F367TER_TRIG_FLG1 0xf1040080
+#define F367TER_TRIG_FLG0 0xf1040040
+#define F367TER_FFT_FLG1 0xf1040008
+#define F367TER_FFT_FLG0 0xf1040004
+#define F367TER_CHC_FLG1 0xf1040002
+#define F367TER_CHC_FLG0 0xf1040001
+
+/* CRL_TARGET1 */
+#define R367TER_CRL_TARGET1 0xf105
+#define F367TER_CRL_START 0xf1050080
+#define F367TER_CRL_TARGET_VHI 0xf105000f
+
+/* CRL_TARGET2 */
+#define R367TER_CRL_TARGET2 0xf106
+#define F367TER_CRL_TARGET_HI 0xf10600ff
+
+/* CRL_TARGET3 */
+#define R367TER_CRL_TARGET3 0xf107
+#define F367TER_CRL_TARGET_LO 0xf10700ff
+
+/* CRL_TARGET4 */
+#define R367TER_CRL_TARGET4 0xf108
+#define F367TER_CRL_TARGET_VLO 0xf10800ff
+
+/* CRL_FLAG */
+#define R367TER_CRL_FLAG 0xf109
+#define F367TER_CRL_FLAG1 0xf1090002
+#define F367TER_CRL_FLAG0 0xf1090001
+
+/* TRL_TARGET1 */
+#define R367TER_TRL_TARGET1 0xf10a
+#define F367TER_TRL_TARGET_HI 0xf10a00ff
+
+/* TRL_TARGET2 */
+#define R367TER_TRL_TARGET2 0xf10b
+#define F367TER_TRL_TARGET_LO 0xf10b00ff
+
+/* TRL_CHC */
+#define R367TER_TRL_CHC 0xf10c
+#define F367TER_TRL_START 0xf10c0080
+#define F367TER_CHC_START 0xf10c0040
+#define F367TER_TRL_FLAG1 0xf10c0002
+#define F367TER_TRL_FLAG0 0xf10c0001
+
+/* CHC_SNR_TARG */
+#define R367TER_CHC_SNR_TARG 0xf10d
+#define F367TER_CHC_SNR_TARGET 0xf10d00ff
+
+/* TOP_TRACK */
+#define R367TER_TOP_TRACK 0xf10e
+#define F367TER_TOP_START 0xf10e0080
+#define F367TER_FIRST_FLAG 0xf10e0070
+#define F367TER_TOP_FLAG1 0xf10e0008
+#define F367TER_TOP_FLAG0 0xf10e0004
+#define F367TER_CHC_FLAG1 0xf10e0002
+#define F367TER_CHC_FLAG0 0xf10e0001
+
+/* TRACKER_FREE1 */
+#define R367TER_TRACKER_FREE1 0xf10f
+#define F367TER_TRACKER_FREE_1 0xf10f00ff
+
+/* ERROR_CRL1 */
+#define R367TER_ERROR_CRL1 0xf110
+#define F367TER_ERROR_CRL_VHI 0xf11000ff
+
+/* ERROR_CRL2 */
+#define R367TER_ERROR_CRL2 0xf111
+#define F367TER_ERROR_CRL_HI 0xf11100ff
+
+/* ERROR_CRL3 */
+#define R367TER_ERROR_CRL3 0xf112
+#define F367TER_ERROR_CRL_LOI 0xf11200ff
+
+/* ERROR_CRL4 */
+#define R367TER_ERROR_CRL4 0xf113
+#define F367TER_ERROR_CRL_VLO 0xf11300ff
+
+/* DEC_NCO1 */
+#define R367TER_DEC_NCO1 0xf114
+#define F367TER_DEC_NCO_VHI 0xf11400ff
+
+/* DEC_NCO2 */
+#define R367TER_DEC_NCO2 0xf115
+#define F367TER_DEC_NCO_HI 0xf11500ff
+
+/* DEC_NCO3 */
+#define R367TER_DEC_NCO3 0xf116
+#define F367TER_DEC_NCO_LO 0xf11600ff
+
+/* SNR */
+#define R367TER_SNR 0xf117
+#define F367TER_SNRATIO 0xf11700ff
+
+/* SYR_FFTADJ1 */
+#define R367TER_SYR_FFTADJ1 0xf118
+#define F367TER_SYR_FFTADJ_HI 0xf11800ff
+
+/* SYR_FFTADJ2 */
+#define R367TER_SYR_FFTADJ2 0xf119
+#define F367TER_SYR_FFTADJ_LO 0xf11900ff
+
+/* SYR_CHCADJ1 */
+#define R367TER_SYR_CHCADJ1 0xf11a
+#define F367TER_SYR_CHCADJ_HI 0xf11a00ff
+
+/* SYR_CHCADJ2 */
+#define R367TER_SYR_CHCADJ2 0xf11b
+#define F367TER_SYR_CHCADJ_LO 0xf11b00ff
+
+/* SYR_OFF */
+#define R367TER_SYR_OFF 0xf11c
+#define F367TER_SYR_OFFSET 0xf11c00ff
+
+/* PPM_OFFSET1 */
+#define R367TER_PPM_OFFSET1 0xf11d
+#define F367TER_PPM_OFFSET_HI 0xf11d00ff
+
+/* PPM_OFFSET2 */
+#define R367TER_PPM_OFFSET2 0xf11e
+#define F367TER_PPM_OFFSET_LO 0xf11e00ff
+
+/* TRACKER_FREE2 */
+#define R367TER_TRACKER_FREE2 0xf11f
+#define F367TER_TRACKER_FREE_2 0xf11f00ff
+
+/* DEBG_LT10 */
+#define R367TER_DEBG_LT10 0xf120
+#define F367TER_DEBUG_LT10 0xf12000ff
+
+/* DEBG_LT11 */
+#define R367TER_DEBG_LT11 0xf121
+#define F367TER_DEBUG_LT11 0xf12100ff
+
+/* DEBG_LT12 */
+#define R367TER_DEBG_LT12 0xf122
+#define F367TER_DEBUG_LT12 0xf12200ff
+
+/* DEBG_LT13 */
+#define R367TER_DEBG_LT13 0xf123
+#define F367TER_DEBUG_LT13 0xf12300ff
+
+/* DEBG_LT14 */
+#define R367TER_DEBG_LT14 0xf124
+#define F367TER_DEBUG_LT14 0xf12400ff
+
+/* DEBG_LT15 */
+#define R367TER_DEBG_LT15 0xf125
+#define F367TER_DEBUG_LT15 0xf12500ff
+
+/* DEBG_LT16 */
+#define R367TER_DEBG_LT16 0xf126
+#define F367TER_DEBUG_LT16 0xf12600ff
+
+/* DEBG_LT17 */
+#define R367TER_DEBG_LT17 0xf127
+#define F367TER_DEBUG_LT17 0xf12700ff
+
+/* DEBG_LT18 */
+#define R367TER_DEBG_LT18 0xf128
+#define F367TER_DEBUG_LT18 0xf12800ff
+
+/* DEBG_LT19 */
+#define R367TER_DEBG_LT19 0xf129
+#define F367TER_DEBUG_LT19 0xf12900ff
+
+/* DEBG_LT1a */
+#define R367TER_DEBG_LT1A 0xf12a
+#define F367TER_DEBUG_LT1A 0xf12a00ff
+
+/* DEBG_LT1b */
+#define R367TER_DEBG_LT1B 0xf12b
+#define F367TER_DEBUG_LT1B 0xf12b00ff
+
+/* DEBG_LT1c */
+#define R367TER_DEBG_LT1C 0xf12c
+#define F367TER_DEBUG_LT1C 0xf12c00ff
+
+/* DEBG_LT1D */
+#define R367TER_DEBG_LT1D 0xf12d
+#define F367TER_DEBUG_LT1D 0xf12d00ff
+
+/* DEBG_LT1E */
+#define R367TER_DEBG_LT1E 0xf12e
+#define F367TER_DEBUG_LT1E 0xf12e00ff
+
+/* DEBG_LT1F */
+#define R367TER_DEBG_LT1F 0xf12f
+#define F367TER_DEBUG_LT1F 0xf12f00ff
+
+/* RCCFGH */
+#define R367TER_RCCFGH 0xf200
+#define F367TER_TSRCFIFO_DVBCI 0xf2000080
+#define F367TER_TSRCFIFO_SERIAL 0xf2000040
+#define F367TER_TSRCFIFO_DISABLE 0xf2000020
+#define F367TER_TSFIFO_2TORC 0xf2000010
+#define F367TER_TSRCFIFO_HSGNLOUT 0xf2000008
+#define F367TER_TSRCFIFO_ERRMODE 0xf2000006
+#define F367TER_RCCFGH_0 0xf2000001
+
+/* RCCFGM */
+#define R367TER_RCCFGM 0xf201
+#define F367TER_TSRCFIFO_MANSPEED 0xf20100c0
+#define F367TER_TSRCFIFO_PERMDATA 0xf2010020
+#define F367TER_TSRCFIFO_NONEWSGNL 0xf2010010
+#define F367TER_RCBYTE_OVERSAMPLING 0xf201000e
+#define F367TER_TSRCFIFO_INVDATA 0xf2010001
+
+/* RCCFGL */
+#define R367TER_RCCFGL 0xf202
+#define F367TER_TSRCFIFO_BCLKDEL1cK 0xf20200c0
+#define F367TER_RCCFGL_5 0xf2020020
+#define F367TER_TSRCFIFO_DUTY50 0xf2020010
+#define F367TER_TSRCFIFO_NSGNL2dATA 0xf2020008
+#define F367TER_TSRCFIFO_DISSERMUX 0xf2020004
+#define F367TER_RCCFGL_1 0xf2020002
+#define F367TER_TSRCFIFO_STOPCKDIS 0xf2020001
+
+/* RCINSDELH */
+#define R367TER_RCINSDELH 0xf203
+#define F367TER_TSRCDEL_SYNCBYTE 0xf2030080
+#define F367TER_TSRCDEL_XXHEADER 0xf2030040
+#define F367TER_TSRCDEL_BBHEADER 0xf2030020
+#define F367TER_TSRCDEL_DATAFIELD 0xf2030010
+#define F367TER_TSRCINSDEL_ISCR 0xf2030008
+#define F367TER_TSRCINSDEL_NPD 0xf2030004
+#define F367TER_TSRCINSDEL_RSPARITY 0xf2030002
+#define F367TER_TSRCINSDEL_CRC8 0xf2030001
+
+/* RCINSDELM */
+#define R367TER_RCINSDELM 0xf204
+#define F367TER_TSRCINS_BBPADDING 0xf2040080
+#define F367TER_TSRCINS_BCHFEC 0xf2040040
+#define F367TER_TSRCINS_LDPCFEC 0xf2040020
+#define F367TER_TSRCINS_EMODCOD 0xf2040010
+#define F367TER_TSRCINS_TOKEN 0xf2040008
+#define F367TER_TSRCINS_XXXERR 0xf2040004
+#define F367TER_TSRCINS_MATYPE 0xf2040002
+#define F367TER_TSRCINS_UPL 0xf2040001
+
+/* RCINSDELL */
+#define R367TER_RCINSDELL 0xf205
+#define F367TER_TSRCINS_DFL 0xf2050080
+#define F367TER_TSRCINS_SYNCD 0xf2050040
+#define F367TER_TSRCINS_BLOCLEN 0xf2050020
+#define F367TER_TSRCINS_SIGPCOUNT 0xf2050010
+#define F367TER_TSRCINS_FIFO 0xf2050008
+#define F367TER_TSRCINS_REALPACK 0xf2050004
+#define F367TER_TSRCINS_TSCONFIG 0xf2050002
+#define F367TER_TSRCINS_LATENCY 0xf2050001
+
+/* RCSTATUS */
+#define R367TER_RCSTATUS 0xf206
+#define F367TER_TSRCFIFO_LINEOK 0xf2060080
+#define F367TER_TSRCFIFO_ERROR 0xf2060040
+#define F367TER_TSRCFIFO_DATA7 0xf2060020
+#define F367TER_RCSTATUS_4 0xf2060010
+#define F367TER_TSRCFIFO_DEMODSEL 0xf2060008
+#define F367TER_TSRC1FIFOSPEED_STORE 0xf2060004
+#define F367TER_RCSTATUS_1 0xf2060002
+#define F367TER_TSRCSERIAL_IMPOSSIBLE 0xf2060001
+
+/* RCSPEED */
+#define R367TER_RCSPEED 0xf207
+#define F367TER_TSRCFIFO_OUTSPEED 0xf20700ff
+
+/* RCDEBUGM */
+#define R367TER_RCDEBUGM 0xf208
+#define F367TER_SD_UNSYNC 0xf2080080
+#define F367TER_ULFLOCK_DETECTM 0xf2080040
+#define F367TER_SUL_SELECTOS 0xf2080020
+#define F367TER_DILUL_NOSCRBLE 0xf2080010
+#define F367TER_NUL_SCRB 0xf2080008
+#define F367TER_UL_SCRB 0xf2080004
+#define F367TER_SCRAULBAD 0xf2080002
+#define F367TER_SCRAUL_UNSYNC 0xf2080001
+
+/* RCDEBUGL */
+#define R367TER_RCDEBUGL 0xf209
+#define F367TER_RS_ERR 0xf2090080
+#define F367TER_LLFLOCK_DETECTM 0xf2090040
+#define F367TER_NOT_SUL_SELECTOS 0xf2090020
+#define F367TER_DILLL_NOSCRBLE 0xf2090010
+#define F367TER_NLL_SCRB 0xf2090008
+#define F367TER_LL_SCRB 0xf2090004
+#define F367TER_SCRALLBAD 0xf2090002
+#define F367TER_SCRALL_UNSYNC 0xf2090001
+
+/* RCOBSCFG */
+#define R367TER_RCOBSCFG 0xf20a
+#define F367TER_TSRCFIFO_OBSCFG 0xf20a00ff
+
+/* RCOBSM */
+#define R367TER_RCOBSM 0xf20b
+#define F367TER_TSRCFIFO_OBSDATA_HI 0xf20b00ff
+
+/* RCOBSL */
+#define R367TER_RCOBSL 0xf20c
+#define F367TER_TSRCFIFO_OBSDATA_LO 0xf20c00ff
+
+/* RCFECSPY */
+#define R367TER_RCFECSPY 0xf210
+#define F367TER_SPYRC_ENABLE 0xf2100080
+#define F367TER_RCNO_SYNCBYTE 0xf2100040
+#define F367TER_RCSERIAL_MODE 0xf2100020
+#define F367TER_RCUNUSUAL_PACKET 0xf2100010
+#define F367TER_BERRCMETER_DATAMODE 0xf210000c
+#define F367TER_BERRCMETER_LMODE 0xf2100002
+#define F367TER_BERRCMETER_RESET 0xf2100001
+
+/* RCFSPYCFG */
+#define R367TER_RCFSPYCFG 0xf211
+#define F367TER_FECSPYRC_INPUT 0xf21100c0
+#define F367TER_RCRST_ON_ERROR 0xf2110020
+#define F367TER_RCONE_SHOT 0xf2110010
+#define F367TER_RCI2C_MODE 0xf211000c
+#define F367TER_SPYRC_HSTERESIS 0xf2110003
+
+/* RCFSPYDATA */
+#define R367TER_RCFSPYDATA 0xf212
+#define F367TER_SPYRC_STUFFING 0xf2120080
+#define F367TER_RCNOERR_PKTJITTER 0xf2120040
+#define F367TER_SPYRC_CNULLPKT 0xf2120020
+#define F367TER_SPYRC_OUTDATA_MODE 0xf212001f
+
+/* RCFSPYOUT */
+#define R367TER_RCFSPYOUT 0xf213
+#define F367TER_FSPYRC_DIRECT 0xf2130080
+#define F367TER_RCFSPYOUT_6 0xf2130040
+#define F367TER_SPYRC_OUTDATA_BUS 0xf2130038
+#define F367TER_RCSTUFF_MODE 0xf2130007
+
+/* RCFSTATUS */
+#define R367TER_RCFSTATUS 0xf214
+#define F367TER_SPYRC_ENDSIM 0xf2140080
+#define F367TER_RCVALID_SIM 0xf2140040
+#define F367TER_RCFOUND_SIGNAL 0xf2140020
+#define F367TER_RCDSS_SYNCBYTE 0xf2140010
+#define F367TER_RCRESULT_STATE 0xf214000f
+
+/* RCFGOODPACK */
+#define R367TER_RCFGOODPACK 0xf215
+#define F367TER_RCGOOD_PACKET 0xf21500ff
+
+/* RCFPACKCNT */
+#define R367TER_RCFPACKCNT 0xf216
+#define F367TER_RCPACKET_COUNTER 0xf21600ff
+
+/* RCFSPYMISC */
+#define R367TER_RCFSPYMISC 0xf217
+#define F367TER_RCLABEL_COUNTER 0xf21700ff
+
+/* RCFBERCPT4 */
+#define R367TER_RCFBERCPT4 0xf218
+#define F367TER_FBERRCMETER_CPT_MMMMSB 0xf21800ff
+
+/* RCFBERCPT3 */
+#define R367TER_RCFBERCPT3 0xf219
+#define F367TER_FBERRCMETER_CPT_MMMSB 0xf21900ff
+
+/* RCFBERCPT2 */
+#define R367TER_RCFBERCPT2 0xf21a
+#define F367TER_FBERRCMETER_CPT_MMSB 0xf21a00ff
+
+/* RCFBERCPT1 */
+#define R367TER_RCFBERCPT1 0xf21b
+#define F367TER_FBERRCMETER_CPT_MSB 0xf21b00ff
+
+/* RCFBERCPT0 */
+#define R367TER_RCFBERCPT0 0xf21c
+#define F367TER_FBERRCMETER_CPT_LSB 0xf21c00ff
+
+/* RCFBERERR2 */
+#define R367TER_RCFBERERR2 0xf21d
+#define F367TER_FBERRCMETER_ERR_HI 0xf21d00ff
+
+/* RCFBERERR1 */
+#define R367TER_RCFBERERR1 0xf21e
+#define F367TER_FBERRCMETER_ERR 0xf21e00ff
+
+/* RCFBERERR0 */
+#define R367TER_RCFBERERR0 0xf21f
+#define F367TER_FBERRCMETER_ERR_LO 0xf21f00ff
+
+/* RCFSTATESM */
+#define R367TER_RCFSTATESM 0xf220
+#define F367TER_RCRSTATE_F 0xf2200080
+#define F367TER_RCRSTATE_E 0xf2200040
+#define F367TER_RCRSTATE_D 0xf2200020
+#define F367TER_RCRSTATE_C 0xf2200010
+#define F367TER_RCRSTATE_B 0xf2200008
+#define F367TER_RCRSTATE_A 0xf2200004
+#define F367TER_RCRSTATE_9 0xf2200002
+#define F367TER_RCRSTATE_8 0xf2200001
+
+/* RCFSTATESL */
+#define R367TER_RCFSTATESL 0xf221
+#define F367TER_RCRSTATE_7 0xf2210080
+#define F367TER_RCRSTATE_6 0xf2210040
+#define F367TER_RCRSTATE_5 0xf2210020
+#define F367TER_RCRSTATE_4 0xf2210010
+#define F367TER_RCRSTATE_3 0xf2210008
+#define F367TER_RCRSTATE_2 0xf2210004
+#define F367TER_RCRSTATE_1 0xf2210002
+#define F367TER_RCRSTATE_0 0xf2210001
+
+/* RCFSPYBER */
+#define R367TER_RCFSPYBER 0xf222
+#define F367TER_RCFSPYBER_7 0xf2220080
+#define F367TER_SPYRCOBS_XORREAD 0xf2220040
+#define F367TER_FSPYRCBER_OBSMODE 0xf2220020
+#define F367TER_FSPYRCBER_SYNCBYT 0xf2220010
+#define F367TER_FSPYRCBER_UNSYNC 0xf2220008
+#define F367TER_FSPYRCBER_CTIME 0xf2220007
+
+/* RCFSPYDISTM */
+#define R367TER_RCFSPYDISTM 0xf223
+#define F367TER_RCPKTTIME_DISTANCE_HI 0xf22300ff
+
+/* RCFSPYDISTL */
+#define R367TER_RCFSPYDISTL 0xf224
+#define F367TER_RCPKTTIME_DISTANCE_LO 0xf22400ff
+
+/* RCFSPYOBS7 */
+#define R367TER_RCFSPYOBS7 0xf228
+#define F367TER_RCSPYOBS_SPYFAIL 0xf2280080
+#define F367TER_RCSPYOBS_SPYFAIL1 0xf2280040
+#define F367TER_RCSPYOBS_ERROR 0xf2280020
+#define F367TER_RCSPYOBS_STROUT 0xf2280010
+#define F367TER_RCSPYOBS_RESULTSTATE1 0xf228000f
+
+/* RCFSPYOBS6 */
+#define R367TER_RCFSPYOBS6 0xf229
+#define F367TER_RCSPYOBS_RESULTSTATe0 0xf22900f0
+#define F367TER_RCSPYOBS_RESULTSTATEM1 0xf229000f
+
+/* RCFSPYOBS5 */
+#define R367TER_RCFSPYOBS5 0xf22a
+#define F367TER_RCSPYOBS_BYTEOFPACKET1 0xf22a00ff
+
+/* RCFSPYOBS4 */
+#define R367TER_RCFSPYOBS4 0xf22b
+#define F367TER_RCSPYOBS_BYTEVALUE1 0xf22b00ff
+
+/* RCFSPYOBS3 */
+#define R367TER_RCFSPYOBS3 0xf22c
+#define F367TER_RCSPYOBS_DATA1 0xf22c00ff
+
+/* RCFSPYOBS2 */
+#define R367TER_RCFSPYOBS2 0xf22d
+#define F367TER_RCSPYOBS_DATa0 0xf22d00ff
+
+/* RCFSPYOBS1 */
+#define R367TER_RCFSPYOBS1 0xf22e
+#define F367TER_RCSPYOBS_DATAM1 0xf22e00ff
+
+/* RCFSPYOBS0 */
+#define R367TER_RCFSPYOBS0 0xf22f
+#define F367TER_RCSPYOBS_DATAM2 0xf22f00ff
+
+/* TSGENERAL */
+#define R367TER_TSGENERAL 0xf230
+#define F367TER_TSGENERAL_7 0xf2300080
+#define F367TER_TSGENERAL_6 0xf2300040
+#define F367TER_TSFIFO_BCLK1aLL 0xf2300020
+#define F367TER_TSGENERAL_4 0xf2300010
+#define F367TER_MUXSTREAM_OUTMODE 0xf2300008
+#define F367TER_TSFIFO_PERMPARAL 0xf2300006
+#define F367TER_RST_REEDSOLO 0xf2300001
+
+/* RC1SPEED */
+#define R367TER_RC1SPEED 0xf231
+#define F367TER_TSRCFIFO1_OUTSPEED 0xf23100ff
+
+/* TSGSTATUS */
+#define R367TER_TSGSTATUS 0xf232
+#define F367TER_TSGSTATUS_7 0xf2320080
+#define F367TER_TSGSTATUS_6 0xf2320040
+#define F367TER_RSMEM_FULL 0xf2320020
+#define F367TER_RS_MULTCALC 0xf2320010
+#define F367TER_RSIN_OVERTIME 0xf2320008
+#define F367TER_TSFIFO3_DEMODSEL 0xf2320004
+#define F367TER_TSFIFO2_DEMODSEL 0xf2320002
+#define F367TER_TSFIFO1_DEMODSEL 0xf2320001
+
+
+/* FECM */
+#define R367TER_FECM 0xf233
+#define F367TER_DSS_DVB 0xf2330080
+#define F367TER_DEMOD_BYPASS 0xf2330040
+#define F367TER_CMP_SLOWMODE 0xf2330020
+#define F367TER_DSS_SRCH 0xf2330010
+#define F367TER_FECM_3 0xf2330008
+#define F367TER_DIFF_MODEVIT 0xf2330004
+#define F367TER_SYNCVIT 0xf2330002
+#define F367TER_I2CSYM 0xf2330001
+
+/* VTH12 */
+#define R367TER_VTH12 0xf234
+#define F367TER_VTH_12 0xf23400ff
+
+/* VTH23 */
+#define R367TER_VTH23 0xf235
+#define F367TER_VTH_23 0xf23500ff
+
+/* VTH34 */
+#define R367TER_VTH34 0xf236
+#define F367TER_VTH_34 0xf23600ff
+
+/* VTH56 */
+#define R367TER_VTH56 0xf237
+#define F367TER_VTH_56 0xf23700ff
+
+/* VTH67 */
+#define R367TER_VTH67 0xf238
+#define F367TER_VTH_67 0xf23800ff
+
+/* VTH78 */
+#define R367TER_VTH78 0xf239
+#define F367TER_VTH_78 0xf23900ff
+
+/* VITCURPUN */
+#define R367TER_VITCURPUN 0xf23a
+#define F367TER_VIT_MAPPING 0xf23a00e0
+#define F367TER_VIT_CURPUN 0xf23a001f
+
+/* VERROR */
+#define R367TER_VERROR 0xf23b
+#define F367TER_REGERR_VIT 0xf23b00ff
+
+/* PRVIT */
+#define R367TER_PRVIT 0xf23c
+#define F367TER_PRVIT_7 0xf23c0080
+#define F367TER_DIS_VTHLOCK 0xf23c0040
+#define F367TER_E7_8VIT 0xf23c0020
+#define F367TER_E6_7VIT 0xf23c0010
+#define F367TER_E5_6VIT 0xf23c0008
+#define F367TER_E3_4VIT 0xf23c0004
+#define F367TER_E2_3VIT 0xf23c0002
+#define F367TER_E1_2VIT 0xf23c0001
+
+/* VAVSRVIT */
+#define R367TER_VAVSRVIT 0xf23d
+#define F367TER_AMVIT 0xf23d0080
+#define F367TER_FROZENVIT 0xf23d0040
+#define F367TER_SNVIT 0xf23d0030
+#define F367TER_TOVVIT 0xf23d000c
+#define F367TER_HYPVIT 0xf23d0003
+
+/* VSTATUSVIT */
+#define R367TER_VSTATUSVIT 0xf23e
+#define F367TER_VITERBI_ON 0xf23e0080
+#define F367TER_END_LOOPVIT 0xf23e0040
+#define F367TER_VITERBI_DEPRF 0xf23e0020
+#define F367TER_PRFVIT 0xf23e0010
+#define F367TER_LOCKEDVIT 0xf23e0008
+#define F367TER_VITERBI_DELOCK 0xf23e0004
+#define F367TER_VIT_DEMODSEL 0xf23e0002
+#define F367TER_VITERBI_COMPOUT 0xf23e0001
+
+/* VTHINUSE */
+#define R367TER_VTHINUSE 0xf23f
+#define F367TER_VIT_INUSE 0xf23f00ff
+
+/* KDIV12 */
+#define R367TER_KDIV12 0xf240
+#define F367TER_KDIV12_MANUAL 0xf2400080
+#define F367TER_K_DIVIDER_12 0xf240007f
+
+/* KDIV23 */
+#define R367TER_KDIV23 0xf241
+#define F367TER_KDIV23_MANUAL 0xf2410080
+#define F367TER_K_DIVIDER_23 0xf241007f
+
+/* KDIV34 */
+#define R367TER_KDIV34 0xf242
+#define F367TER_KDIV34_MANUAL 0xf2420080
+#define F367TER_K_DIVIDER_34 0xf242007f
+
+/* KDIV56 */
+#define R367TER_KDIV56 0xf243
+#define F367TER_KDIV56_MANUAL 0xf2430080
+#define F367TER_K_DIVIDER_56 0xf243007f
+
+/* KDIV67 */
+#define R367TER_KDIV67 0xf244
+#define F367TER_KDIV67_MANUAL 0xf2440080
+#define F367TER_K_DIVIDER_67 0xf244007f
+
+/* KDIV78 */
+#define R367TER_KDIV78 0xf245
+#define F367TER_KDIV78_MANUAL 0xf2450080
+#define F367TER_K_DIVIDER_78 0xf245007f
+
+/* SIGPOWER */
+#define R367TER_SIGPOWER 0xf246
+#define F367TER_SIGPOWER_MANUAL 0xf2460080
+#define F367TER_SIG_POWER 0xf246007f
+
+/* DEMAPVIT */
+#define R367TER_DEMAPVIT 0xf247
+#define F367TER_DEMAPVIT_7 0xf2470080
+#define F367TER_K_DIVIDER_VIT 0xf247007f
+
+/* VITSCALE */
+#define R367TER_VITSCALE 0xf248
+#define F367TER_NVTH_NOSRANGE 0xf2480080
+#define F367TER_VERROR_MAXMODE 0xf2480040
+#define F367TER_KDIV_MODE 0xf2480030
+#define F367TER_NSLOWSN_LOCKED 0xf2480008
+#define F367TER_DELOCK_PRFLOSS 0xf2480004
+#define F367TER_DIS_RSFLOCK 0xf2480002
+#define F367TER_VITSCALE_0 0xf2480001
+
+/* FFEC1PRG */
+#define R367TER_FFEC1PRG 0xf249
+#define F367TER_FDSS_DVB 0xf2490080
+#define F367TER_FDSS_SRCH 0xf2490040
+#define F367TER_FFECPROG_5 0xf2490020
+#define F367TER_FFECPROG_4 0xf2490010
+#define F367TER_FFECPROG_3 0xf2490008
+#define F367TER_FFECPROG_2 0xf2490004
+#define F367TER_FTS1_DISABLE 0xf2490002
+#define F367TER_FTS2_DISABLE 0xf2490001
+
+/* FVITCURPUN */
+#define R367TER_FVITCURPUN 0xf24a
+#define F367TER_FVIT_MAPPING 0xf24a00e0
+#define F367TER_FVIT_CURPUN 0xf24a001f
+
+/* FVERROR */
+#define R367TER_FVERROR 0xf24b
+#define F367TER_FREGERR_VIT 0xf24b00ff
+
+/* FVSTATUSVIT */
+#define R367TER_FVSTATUSVIT 0xf24c
+#define F367TER_FVITERBI_ON 0xf24c0080
+#define F367TER_F1END_LOOPVIT 0xf24c0040
+#define F367TER_FVITERBI_DEPRF 0xf24c0020
+#define F367TER_FPRFVIT 0xf24c0010
+#define F367TER_FLOCKEDVIT 0xf24c0008
+#define F367TER_FVITERBI_DELOCK 0xf24c0004
+#define F367TER_FVIT_DEMODSEL 0xf24c0002
+#define F367TER_FVITERBI_COMPOUT 0xf24c0001
+
+/* DEBUG_LT1 */
+#define R367TER_DEBUG_LT1 0xf24d
+#define F367TER_DBG_LT1 0xf24d00ff
+
+/* DEBUG_LT2 */
+#define R367TER_DEBUG_LT2 0xf24e
+#define F367TER_DBG_LT2 0xf24e00ff
+
+/* DEBUG_LT3 */
+#define R367TER_DEBUG_LT3 0xf24f
+#define F367TER_DBG_LT3 0xf24f00ff
+
+/* TSTSFMET */
+#define R367TER_TSTSFMET 0xf250
+#define F367TER_TSTSFEC_METRIQUES 0xf25000ff
+
+/* SELOUT */
+#define R367TER_SELOUT 0xf252
+#define F367TER_EN_SYNC 0xf2520080
+#define F367TER_EN_TBUSDEMAP 0xf2520040
+#define F367TER_SELOUT_5 0xf2520020
+#define F367TER_SELOUT_4 0xf2520010
+#define F367TER_TSTSYNCHRO_MODE 0xf2520002
+
+/* TSYNC */
+#define R367TER_TSYNC 0xf253
+#define F367TER_CURPUN_INCMODE 0xf2530080
+#define F367TER_CERR_TSTMODE 0xf2530040
+#define F367TER_SHIFTSOF_MODE 0xf2530030
+#define F367TER_SLOWPHA_MODE 0xf2530008
+#define F367TER_PXX_BYPALL 0xf2530004
+#define F367TER_FROTA45_FIRST 0xf2530002
+#define F367TER_TST_BCHERROR 0xf2530001
+
+/* TSTERR */
+#define R367TER_TSTERR 0xf254
+#define F367TER_TST_LONGPKT 0xf2540080
+#define F367TER_TST_ISSYION 0xf2540040
+#define F367TER_TST_NPDON 0xf2540020
+#define F367TER_TSTERR_4 0xf2540010
+#define F367TER_TRACEBACK_MODE 0xf2540008
+#define F367TER_TST_RSPARITY 0xf2540004
+#define F367TER_METRIQUE_MODE 0xf2540003
+
+/* TSFSYNC */
+#define R367TER_TSFSYNC 0xf255
+#define F367TER_EN_SFECSYNC 0xf2550080
+#define F367TER_EN_SFECDEMAP 0xf2550040
+#define F367TER_SFCERR_TSTMODE 0xf2550020
+#define F367TER_SFECPXX_BYPALL 0xf2550010
+#define F367TER_SFECTSTSYNCHRO_MODE 0xf255000f
+
+/* TSTSFERR */
+#define R367TER_TSTSFERR 0xf256
+#define F367TER_TSTSTERR_7 0xf2560080
+#define F367TER_TSTSTERR_6 0xf2560040
+#define F367TER_TSTSTERR_5 0xf2560020
+#define F367TER_TSTSTERR_4 0xf2560010
+#define F367TER_SFECTRACEBACK_MODE 0xf2560008
+#define F367TER_SFEC_NCONVPROG 0xf2560004
+#define F367TER_SFECMETRIQUE_MODE 0xf2560003
+
+/* TSTTSSF1 */
+#define R367TER_TSTTSSF1 0xf258
+#define F367TER_TSTERSSF 0xf2580080
+#define F367TER_TSTTSSFEN 0xf2580040
+#define F367TER_SFEC_OUTMODE 0xf2580030
+#define F367TER_XLSF_NOFTHRESHOLD 0xf2580008
+#define F367TER_TSTTSSF_STACKSEL 0xf2580007
+
+/* TSTTSSF2 */
+#define R367TER_TSTTSSF2 0xf259
+#define F367TER_DILSF_DBBHEADER 0xf2590080
+#define F367TER_TSTTSSF_DISBUG 0xf2590040
+#define F367TER_TSTTSSF_NOBADSTART 0xf2590020
+#define F367TER_TSTTSSF_SELECT 0xf259001f
+
+/* TSTTSSF3 */
+#define R367TER_TSTTSSF3 0xf25a
+#define F367TER_TSTTSSF3_7 0xf25a0080
+#define F367TER_TSTTSSF3_6 0xf25a0040
+#define F367TER_TSTTSSF3_5 0xf25a0020
+#define F367TER_TSTTSSF3_4 0xf25a0010
+#define F367TER_TSTTSSF3_3 0xf25a0008
+#define F367TER_TSTTSSF3_2 0xf25a0004
+#define F367TER_TSTTSSF3_1 0xf25a0002
+#define F367TER_DISSF_CLKENABLE 0xf25a0001
+
+/* TSTTS1 */
+#define R367TER_TSTTS1 0xf25c
+#define F367TER_TSTERS 0xf25c0080
+#define F367TER_TSFIFO_DSSSYNCB 0xf25c0040
+#define F367TER_TSTTS_FSPYBEFRS 0xf25c0020
+#define F367TER_NFORCE_SYNCBYTE 0xf25c0010
+#define F367TER_XL_NOFTHRESHOLD 0xf25c0008
+#define F367TER_TSTTS_FRFORCEPKT 0xf25c0004
+#define F367TER_DESCR_NOTAUTO 0xf25c0002
+#define F367TER_TSTTSEN 0xf25c0001
+
+/* TSTTS2 */
+#define R367TER_TSTTS2 0xf25d
+#define F367TER_DIL_DBBHEADER 0xf25d0080
+#define F367TER_TSTTS_NOBADXXX 0xf25d0040
+#define F367TER_TSFIFO_DELSPEEDUP 0xf25d0020
+#define F367TER_TSTTS_SELECT 0xf25d001f
+
+/* TSTTS3 */
+#define R367TER_TSTTS3 0xf25e
+#define F367TER_TSTTS_NOPKTGAIN 0xf25e0080
+#define F367TER_TSTTS_NOPKTENE 0xf25e0040
+#define F367TER_TSTTS_ISOLATION 0xf25e0020
+#define F367TER_TSTTS_DISBUG 0xf25e0010
+#define F367TER_TSTTS_NOBADSTART 0xf25e0008
+#define F367TER_TSTTS_STACKSEL 0xf25e0007
+
+/* TSTTS4 */
+#define R367TER_TSTTS4 0xf25f
+#define F367TER_TSTTS4_7 0xf25f0080
+#define F367TER_TSTTS4_6 0xf25f0040
+#define F367TER_TSTTS4_5 0xf25f0020
+#define F367TER_TSTTS_DISDSTATE 0xf25f0010
+#define F367TER_TSTTS_FASTNOSYNC 0xf25f0008
+#define F367TER_EXT_FECSPYIN 0xf25f0004
+#define F367TER_TSTTS_NODPZERO 0xf25f0002
+#define F367TER_TSTTS_NODIV3 0xf25f0001
+
+/* TSTTSRC */
+#define R367TER_TSTTSRC 0xf26c
+#define F367TER_TSTTSRC_7 0xf26c0080
+#define F367TER_TSRCFIFO_DSSSYNCB 0xf26c0040
+#define F367TER_TSRCFIFO_DPUNACTIVE 0xf26c0020
+#define F367TER_TSRCFIFO_DELSPEEDUP 0xf26c0010
+#define F367TER_TSTTSRC_NODIV3 0xf26c0008
+#define F367TER_TSTTSRC_FRFORCEPKT 0xf26c0004
+#define F367TER_SAT25_SDDORIGINE 0xf26c0002
+#define F367TER_TSTTSRC_INACTIVE 0xf26c0001
+
+/* TSTTSRS */
+#define R367TER_TSTTSRS 0xf26d
+#define F367TER_TSTTSRS_7 0xf26d0080
+#define F367TER_TSTTSRS_6 0xf26d0040
+#define F367TER_TSTTSRS_5 0xf26d0020
+#define F367TER_TSTTSRS_4 0xf26d0010
+#define F367TER_TSTTSRS_3 0xf26d0008
+#define F367TER_TSTTSRS_2 0xf26d0004
+#define F367TER_TSTRS_DISRS2 0xf26d0002
+#define F367TER_TSTRS_DISRS1 0xf26d0001
+
+/* TSSTATEM */
+#define R367TER_TSSTATEM 0xf270
+#define F367TER_TSDIL_ON 0xf2700080
+#define F367TER_TSSKIPRS_ON 0xf2700040
+#define F367TER_TSRS_ON 0xf2700020
+#define F367TER_TSDESCRAMB_ON 0xf2700010
+#define F367TER_TSFRAME_MODE 0xf2700008
+#define F367TER_TS_DISABLE 0xf2700004
+#define F367TER_TSACM_MODE 0xf2700002
+#define F367TER_TSOUT_NOSYNC 0xf2700001
+
+/* TSSTATEL */
+#define R367TER_TSSTATEL 0xf271
+#define F367TER_TSNOSYNCBYTE 0xf2710080
+#define F367TER_TSPARITY_ON 0xf2710040
+#define F367TER_TSSYNCOUTRS_ON 0xf2710020
+#define F367TER_TSDVBS2_MODE 0xf2710010
+#define F367TER_TSISSYI_ON 0xf2710008
+#define F367TER_TSNPD_ON 0xf2710004
+#define F367TER_TSCRC8_ON 0xf2710002
+#define F367TER_TSDSS_PACKET 0xf2710001
+
+/* TSCFGH */
+#define R367TER_TSCFGH 0xf272
+#define F367TER_TSFIFO_DVBCI 0xf2720080
+#define F367TER_TSFIFO_SERIAL 0xf2720040
+#define F367TER_TSFIFO_TEIUPDATE 0xf2720020
+#define F367TER_TSFIFO_DUTY50 0xf2720010
+#define F367TER_TSFIFO_HSGNLOUT 0xf2720008
+#define F367TER_TSFIFO_ERRMODE 0xf2720006
+#define F367TER_RST_HWARE 0xf2720001
+
+/* TSCFGM */
+#define R367TER_TSCFGM 0xf273
+#define F367TER_TSFIFO_MANSPEED 0xf27300c0
+#define F367TER_TSFIFO_PERMDATA 0xf2730020
+#define F367TER_TSFIFO_NONEWSGNL 0xf2730010
+#define F367TER_TSFIFO_BITSPEED 0xf2730008
+#define F367TER_NPD_SPECDVBS2 0xf2730004
+#define F367TER_TSFIFO_STOPCKDIS 0xf2730002
+#define F367TER_TSFIFO_INVDATA 0xf2730001
+
+/* TSCFGL */
+#define R367TER_TSCFGL 0xf274
+#define F367TER_TSFIFO_BCLKDEL1cK 0xf27400c0
+#define F367TER_BCHERROR_MODE 0xf2740030
+#define F367TER_TSFIFO_NSGNL2dATA 0xf2740008
+#define F367TER_TSFIFO_EMBINDVB 0xf2740004
+#define F367TER_TSFIFO_DPUNACT 0xf2740002
+#define F367TER_TSFIFO_NPDOFF 0xf2740001
+
+/* TSSYNC */
+#define R367TER_TSSYNC 0xf275
+#define F367TER_TSFIFO_PERMUTE 0xf2750080
+#define F367TER_TSFIFO_FISCR3B 0xf2750060
+#define F367TER_TSFIFO_SYNCMODE 0xf2750018
+#define F367TER_TSFIFO_SYNCSEL 0xf2750007
+
+/* TSINSDELH */
+#define R367TER_TSINSDELH 0xf276
+#define F367TER_TSDEL_SYNCBYTE 0xf2760080
+#define F367TER_TSDEL_XXHEADER 0xf2760040
+#define F367TER_TSDEL_BBHEADER 0xf2760020
+#define F367TER_TSDEL_DATAFIELD 0xf2760010
+#define F367TER_TSINSDEL_ISCR 0xf2760008
+#define F367TER_TSINSDEL_NPD 0xf2760004
+#define F367TER_TSINSDEL_RSPARITY 0xf2760002
+#define F367TER_TSINSDEL_CRC8 0xf2760001
+
+/* TSINSDELM */
+#define R367TER_TSINSDELM 0xf277
+#define F367TER_TSINS_BBPADDING 0xf2770080
+#define F367TER_TSINS_BCHFEC 0xf2770040
+#define F367TER_TSINS_LDPCFEC 0xf2770020
+#define F367TER_TSINS_EMODCOD 0xf2770010
+#define F367TER_TSINS_TOKEN 0xf2770008
+#define F367TER_TSINS_XXXERR 0xf2770004
+#define F367TER_TSINS_MATYPE 0xf2770002
+#define F367TER_TSINS_UPL 0xf2770001
+
+/* TSINSDELL */
+#define R367TER_TSINSDELL 0xf278
+#define F367TER_TSINS_DFL 0xf2780080
+#define F367TER_TSINS_SYNCD 0xf2780040
+#define F367TER_TSINS_BLOCLEN 0xf2780020
+#define F367TER_TSINS_SIGPCOUNT 0xf2780010
+#define F367TER_TSINS_FIFO 0xf2780008
+#define F367TER_TSINS_REALPACK 0xf2780004
+#define F367TER_TSINS_TSCONFIG 0xf2780002
+#define F367TER_TSINS_LATENCY 0xf2780001
+
+/* TSDIVN */
+#define R367TER_TSDIVN 0xf279
+#define F367TER_TSFIFO_LOWSPEED 0xf2790080
+#define F367TER_BYTE_OVERSAMPLING 0xf2790070
+#define F367TER_TSMANUAL_PACKETNBR 0xf279000f
+
+/* TSDIVPM */
+#define R367TER_TSDIVPM 0xf27a
+#define F367TER_TSMANUAL_P_HI 0xf27a00ff
+
+/* TSDIVPL */
+#define R367TER_TSDIVPL 0xf27b
+#define F367TER_TSMANUAL_P_LO 0xf27b00ff
+
+/* TSDIVQM */
+#define R367TER_TSDIVQM 0xf27c
+#define F367TER_TSMANUAL_Q_HI 0xf27c00ff
+
+/* TSDIVQL */
+#define R367TER_TSDIVQL 0xf27d
+#define F367TER_TSMANUAL_Q_LO 0xf27d00ff
+
+/* TSDILSTKM */
+#define R367TER_TSDILSTKM 0xf27e
+#define F367TER_TSFIFO_DILSTK_HI 0xf27e00ff
+
+/* TSDILSTKL */
+#define R367TER_TSDILSTKL 0xf27f
+#define F367TER_TSFIFO_DILSTK_LO 0xf27f00ff
+
+/* TSSPEED */
+#define R367TER_TSSPEED 0xf280
+#define F367TER_TSFIFO_OUTSPEED 0xf28000ff
+
+/* TSSTATUS */
+#define R367TER_TSSTATUS 0xf281
+#define F367TER_TSFIFO_LINEOK 0xf2810080
+#define F367TER_TSFIFO_ERROR 0xf2810040
+#define F367TER_TSFIFO_DATA7 0xf2810020
+#define F367TER_TSFIFO_NOSYNC 0xf2810010
+#define F367TER_ISCR_INITIALIZED 0xf2810008
+#define F367TER_ISCR_UPDATED 0xf2810004
+#define F367TER_SOFFIFO_UNREGUL 0xf2810002
+#define F367TER_DIL_READY 0xf2810001
+
+/* TSSTATUS2 */
+#define R367TER_TSSTATUS2 0xf282
+#define F367TER_TSFIFO_DEMODSEL 0xf2820080
+#define F367TER_TSFIFOSPEED_STORE 0xf2820040
+#define F367TER_DILXX_RESET 0xf2820020
+#define F367TER_TSSERIAL_IMPOSSIBLE 0xf2820010
+#define F367TER_TSFIFO_UNDERSPEED 0xf2820008
+#define F367TER_BITSPEED_EVENT 0xf2820004
+#define F367TER_UL_SCRAMBDETECT 0xf2820002
+#define F367TER_ULDTV67_FALSELOCK 0xf2820001
+
+/* TSBITRATEM */
+#define R367TER_TSBITRATEM 0xf283
+#define F367TER_TSFIFO_BITRATE_HI 0xf28300ff
+
+/* TSBITRATEL */
+#define R367TER_TSBITRATEL 0xf284
+#define F367TER_TSFIFO_BITRATE_LO 0xf28400ff
+
+/* TSPACKLENM */
+#define R367TER_TSPACKLENM 0xf285
+#define F367TER_TSFIFO_PACKCPT 0xf28500e0
+#define F367TER_DIL_RPLEN_HI 0xf285001f
+
+/* TSPACKLENL */
+#define R367TER_TSPACKLENL 0xf286
+#define F367TER_DIL_RPLEN_LO 0xf28600ff
+
+/* TSBLOCLENM */
+#define R367TER_TSBLOCLENM 0xf287
+#define F367TER_TSFIFO_PFLEN_HI 0xf28700ff
+
+/* TSBLOCLENL */
+#define R367TER_TSBLOCLENL 0xf288
+#define F367TER_TSFIFO_PFLEN_LO 0xf28800ff
+
+/* TSDLYH */
+#define R367TER_TSDLYH 0xf289
+#define F367TER_SOFFIFO_TSTIMEVALID 0xf2890080
+#define F367TER_SOFFIFO_SPEEDUP 0xf2890040
+#define F367TER_SOFFIFO_STOP 0xf2890020
+#define F367TER_SOFFIFO_REGULATED 0xf2890010
+#define F367TER_SOFFIFO_REALSBOFF_HI 0xf289000f
+
+/* TSDLYM */
+#define R367TER_TSDLYM 0xf28a
+#define F367TER_SOFFIFO_REALSBOFF_MED 0xf28a00ff
+
+/* TSDLYL */
+#define R367TER_TSDLYL 0xf28b
+#define F367TER_SOFFIFO_REALSBOFF_LO 0xf28b00ff
+
+/* TSNPDAV */
+#define R367TER_TSNPDAV 0xf28c
+#define F367TER_TSNPD_AVERAGE 0xf28c00ff
+
+/* TSBUFSTATH */
+#define R367TER_TSBUFSTATH 0xf28d
+#define F367TER_TSISCR_3BYTES 0xf28d0080
+#define F367TER_TSISCR_NEWDATA 0xf28d0040
+#define F367TER_TSISCR_BUFSTAT_HI 0xf28d003f
+
+/* TSBUFSTATM */
+#define R367TER_TSBUFSTATM 0xf28e
+#define F367TER_TSISCR_BUFSTAT_MED 0xf28e00ff
+
+/* TSBUFSTATL */
+#define R367TER_TSBUFSTATL 0xf28f
+#define F367TER_TSISCR_BUFSTAT_LO 0xf28f00ff
+
+/* TSDEBUGM */
+#define R367TER_TSDEBUGM 0xf290
+#define F367TER_TSFIFO_ILLPACKET 0xf2900080
+#define F367TER_DIL_NOSYNC 0xf2900040
+#define F367TER_DIL_ISCR 0xf2900020
+#define F367TER_DILOUT_BSYNCB 0xf2900010
+#define F367TER_TSFIFO_EMPTYPKT 0xf2900008
+#define F367TER_TSFIFO_EMPTYRD 0xf2900004
+#define F367TER_SOFFIFO_STOPM 0xf2900002
+#define F367TER_SOFFIFO_SPEEDUPM 0xf2900001
+
+/* TSDEBUGL */
+#define R367TER_TSDEBUGL 0xf291
+#define F367TER_TSFIFO_PACKLENFAIL 0xf2910080
+#define F367TER_TSFIFO_SYNCBFAIL 0xf2910040
+#define F367TER_TSFIFO_VITLIBRE 0xf2910020
+#define F367TER_TSFIFO_BOOSTSPEEDM 0xf2910010
+#define F367TER_TSFIFO_UNDERSPEEDM 0xf2910008
+#define F367TER_TSFIFO_ERROR_EVNT 0xf2910004
+#define F367TER_TSFIFO_FULL 0xf2910002
+#define F367TER_TSFIFO_OVERFLOWM 0xf2910001
+
+/* TSDLYSETH */
+#define R367TER_TSDLYSETH 0xf292
+#define F367TER_SOFFIFO_OFFSET 0xf29200e0
+#define F367TER_SOFFIFO_SYMBOFFSET_HI 0xf292001f
+
+/* TSDLYSETM */
+#define R367TER_TSDLYSETM 0xf293
+#define F367TER_SOFFIFO_SYMBOFFSET_MED 0xf29300ff
+
+/* TSDLYSETL */
+#define R367TER_TSDLYSETL 0xf294
+#define F367TER_SOFFIFO_SYMBOFFSET_LO 0xf29400ff
+
+/* TSOBSCFG */
+#define R367TER_TSOBSCFG 0xf295
+#define F367TER_TSFIFO_OBSCFG 0xf29500ff
+
+/* TSOBSM */
+#define R367TER_TSOBSM 0xf296
+#define F367TER_TSFIFO_OBSDATA_HI 0xf29600ff
+
+/* TSOBSL */
+#define R367TER_TSOBSL 0xf297
+#define F367TER_TSFIFO_OBSDATA_LO 0xf29700ff
+
+/* ERRCTRL1 */
+#define R367TER_ERRCTRL1 0xf298
+#define F367TER_ERR_SRC1 0xf29800f0
+#define F367TER_ERRCTRL1_3 0xf2980008
+#define F367TER_NUM_EVT1 0xf2980007
+
+/* ERRCNT1H */
+#define R367TER_ERRCNT1H 0xf299
+#define F367TER_ERRCNT1_OLDVALUE 0xf2990080
+#define F367TER_ERR_CNT1 0xf299007f
+
+/* ERRCNT1M */
+#define R367TER_ERRCNT1M 0xf29a
+#define F367TER_ERR_CNT1_HI 0xf29a00ff
+
+/* ERRCNT1L */
+#define R367TER_ERRCNT1L 0xf29b
+#define F367TER_ERR_CNT1_LO 0xf29b00ff
+
+/* ERRCTRL2 */
+#define R367TER_ERRCTRL2 0xf29c
+#define F367TER_ERR_SRC2 0xf29c00f0
+#define F367TER_ERRCTRL2_3 0xf29c0008
+#define F367TER_NUM_EVT2 0xf29c0007
+
+/* ERRCNT2H */
+#define R367TER_ERRCNT2H 0xf29d
+#define F367TER_ERRCNT2_OLDVALUE 0xf29d0080
+#define F367TER_ERR_CNT2_HI 0xf29d007f
+
+/* ERRCNT2M */
+#define R367TER_ERRCNT2M 0xf29e
+#define F367TER_ERR_CNT2_MED 0xf29e00ff
+
+/* ERRCNT2L */
+#define R367TER_ERRCNT2L 0xf29f
+#define F367TER_ERR_CNT2_LO 0xf29f00ff
+
+/* FECSPY */
+#define R367TER_FECSPY 0xf2a0
+#define F367TER_SPY_ENABLE 0xf2a00080
+#define F367TER_NO_SYNCBYTE 0xf2a00040
+#define F367TER_SERIAL_MODE 0xf2a00020
+#define F367TER_UNUSUAL_PACKET 0xf2a00010
+#define F367TER_BERMETER_DATAMODE 0xf2a0000c
+#define F367TER_BERMETER_LMODE 0xf2a00002
+#define F367TER_BERMETER_RESET 0xf2a00001
+
+/* FSPYCFG */
+#define R367TER_FSPYCFG 0xf2a1
+#define F367TER_FECSPY_INPUT 0xf2a100c0
+#define F367TER_RST_ON_ERROR 0xf2a10020
+#define F367TER_ONE_SHOT 0xf2a10010
+#define F367TER_I2C_MOD 0xf2a1000c
+#define F367TER_SPY_HYSTERESIS 0xf2a10003
+
+/* FSPYDATA */
+#define R367TER_FSPYDATA 0xf2a2
+#define F367TER_SPY_STUFFING 0xf2a20080
+#define F367TER_NOERROR_PKTJITTER 0xf2a20040
+#define F367TER_SPY_CNULLPKT 0xf2a20020
+#define F367TER_SPY_OUTDATA_MODE 0xf2a2001f
+
+/* FSPYOUT */
+#define R367TER_FSPYOUT 0xf2a3
+#define F367TER_FSPY_DIRECT 0xf2a30080
+#define F367TER_FSPYOUT_6 0xf2a30040
+#define F367TER_SPY_OUTDATA_BUS 0xf2a30038
+#define F367TER_STUFF_MODE 0xf2a30007
+
+/* FSTATUS */
+#define R367TER_FSTATUS 0xf2a4
+#define F367TER_SPY_ENDSIM 0xf2a40080
+#define F367TER_VALID_SIM 0xf2a40040
+#define F367TER_FOUND_SIGNAL 0xf2a40020
+#define F367TER_DSS_SYNCBYTE 0xf2a40010
+#define F367TER_RESULT_STATE 0xf2a4000f
+
+/* FGOODPACK */
+#define R367TER_FGOODPACK 0xf2a5
+#define F367TER_FGOOD_PACKET 0xf2a500ff
+
+/* FPACKCNT */
+#define R367TER_FPACKCNT 0xf2a6
+#define F367TER_FPACKET_COUNTER 0xf2a600ff
+
+/* FSPYMISC */
+#define R367TER_FSPYMISC 0xf2a7
+#define F367TER_FLABEL_COUNTER 0xf2a700ff
+
+/* FBERCPT4 */
+#define R367TER_FBERCPT4 0xf2a8
+#define F367TER_FBERMETER_CPT5 0xf2a800ff
+
+/* FBERCPT3 */
+#define R367TER_FBERCPT3 0xf2a9
+#define F367TER_FBERMETER_CPT4 0xf2a900ff
+
+/* FBERCPT2 */
+#define R367TER_FBERCPT2 0xf2aa
+#define F367TER_FBERMETER_CPT3 0xf2aa00ff
+
+/* FBERCPT1 */
+#define R367TER_FBERCPT1 0xf2ab
+#define F367TER_FBERMETER_CPT2 0xf2ab00ff
+
+/* FBERCPT0 */
+#define R367TER_FBERCPT0 0xf2ac
+#define F367TER_FBERMETER_CPT1 0xf2ac00ff
+
+/* FBERERR2 */
+#define R367TER_FBERERR2 0xf2ad
+#define F367TER_FBERMETER_ERR_HI 0xf2ad00ff
+
+/* FBERERR1 */
+#define R367TER_FBERERR1 0xf2ae
+#define F367TER_FBERMETER_ERR_MED 0xf2ae00ff
+
+/* FBERERR0 */
+#define R367TER_FBERERR0 0xf2af
+#define F367TER_FBERMETER_ERR_LO 0xf2af00ff
+
+/* FSTATESM */
+#define R367TER_FSTATESM 0xf2b0
+#define F367TER_RSTATE_F 0xf2b00080
+#define F367TER_RSTATE_E 0xf2b00040
+#define F367TER_RSTATE_D 0xf2b00020
+#define F367TER_RSTATE_C 0xf2b00010
+#define F367TER_RSTATE_B 0xf2b00008
+#define F367TER_RSTATE_A 0xf2b00004
+#define F367TER_RSTATE_9 0xf2b00002
+#define F367TER_RSTATE_8 0xf2b00001
+
+/* FSTATESL */
+#define R367TER_FSTATESL 0xf2b1
+#define F367TER_RSTATE_7 0xf2b10080
+#define F367TER_RSTATE_6 0xf2b10040
+#define F367TER_RSTATE_5 0xf2b10020
+#define F367TER_RSTATE_4 0xf2b10010
+#define F367TER_RSTATE_3 0xf2b10008
+#define F367TER_RSTATE_2 0xf2b10004
+#define F367TER_RSTATE_1 0xf2b10002
+#define F367TER_RSTATE_0 0xf2b10001
+
+/* FSPYBER */
+#define R367TER_FSPYBER 0xf2b2
+#define F367TER_FSPYBER_7 0xf2b20080
+#define F367TER_FSPYOBS_XORREAD 0xf2b20040
+#define F367TER_FSPYBER_OBSMODE 0xf2b20020
+#define F367TER_FSPYBER_SYNCBYTE 0xf2b20010
+#define F367TER_FSPYBER_UNSYNC 0xf2b20008
+#define F367TER_FSPYBER_CTIME 0xf2b20007
+
+/* FSPYDISTM */
+#define R367TER_FSPYDISTM 0xf2b3
+#define F367TER_PKTTIME_DISTANCE_HI 0xf2b300ff
+
+/* FSPYDISTL */
+#define R367TER_FSPYDISTL 0xf2b4
+#define F367TER_PKTTIME_DISTANCE_LO 0xf2b400ff
+
+/* FSPYOBS7 */
+#define R367TER_FSPYOBS7 0xf2b8
+#define F367TER_FSPYOBS_SPYFAIL 0xf2b80080
+#define F367TER_FSPYOBS_SPYFAIL1 0xf2b80040
+#define F367TER_FSPYOBS_ERROR 0xf2b80020
+#define F367TER_FSPYOBS_STROUT 0xf2b80010
+#define F367TER_FSPYOBS_RESULTSTATE1 0xf2b8000f
+
+/* FSPYOBS6 */
+#define R367TER_FSPYOBS6 0xf2b9
+#define F367TER_FSPYOBS_RESULTSTATe0 0xf2b900f0
+#define F367TER_FSPYOBS_RESULTSTATEM1 0xf2b9000f
+
+/* FSPYOBS5 */
+#define R367TER_FSPYOBS5 0xf2ba
+#define F367TER_FSPYOBS_BYTEOFPACKET1 0xf2ba00ff
+
+/* FSPYOBS4 */
+#define R367TER_FSPYOBS4 0xf2bb
+#define F367TER_FSPYOBS_BYTEVALUE1 0xf2bb00ff
+
+/* FSPYOBS3 */
+#define R367TER_FSPYOBS3 0xf2bc
+#define F367TER_FSPYOBS_DATA1 0xf2bc00ff
+
+/* FSPYOBS2 */
+#define R367TER_FSPYOBS2 0xf2bd
+#define F367TER_FSPYOBS_DATa0 0xf2bd00ff
+
+/* FSPYOBS1 */
+#define R367TER_FSPYOBS1 0xf2be
+#define F367TER_FSPYOBS_DATAM1 0xf2be00ff
+
+/* FSPYOBS0 */
+#define R367TER_FSPYOBS0 0xf2bf
+#define F367TER_FSPYOBS_DATAM2 0xf2bf00ff
+
+/* SFDEMAP */
+#define R367TER_SFDEMAP 0xf2c0
+#define F367TER_SFDEMAP_7 0xf2c00080
+#define F367TER_SFEC_K_DIVIDER_VIT 0xf2c0007f
+
+/* SFERROR */
+#define R367TER_SFERROR 0xf2c1
+#define F367TER_SFEC_REGERR_VIT 0xf2c100ff
+
+/* SFAVSR */
+#define R367TER_SFAVSR 0xf2c2
+#define F367TER_SFEC_SUMERRORS 0xf2c20080
+#define F367TER_SERROR_MAXMODE 0xf2c20040
+#define F367TER_SN_SFEC 0xf2c20030
+#define F367TER_KDIV_MODE_SFEC 0xf2c2000c
+#define F367TER_SFAVSR_1 0xf2c20002
+#define F367TER_SFAVSR_0 0xf2c20001
+
+/* SFECSTATUS */
+#define R367TER_SFECSTATUS 0xf2c3
+#define F367TER_SFEC_ON 0xf2c30080
+#define F367TER_SFSTATUS_6 0xf2c30040
+#define F367TER_SFSTATUS_5 0xf2c30020
+#define F367TER_SFSTATUS_4 0xf2c30010
+#define F367TER_LOCKEDSFEC 0xf2c30008
+#define F367TER_SFEC_DELOCK 0xf2c30004
+#define F367TER_SFEC_DEMODSEL1 0xf2c30002
+#define F367TER_SFEC_OVFON 0xf2c30001
+
+/* SFKDIV12 */
+#define R367TER_SFKDIV12 0xf2c4
+#define F367TER_SFECKDIV12_MAN 0xf2c40080
+#define F367TER_SFEC_K_DIVIDER_12 0xf2c4007f
+
+/* SFKDIV23 */
+#define R367TER_SFKDIV23 0xf2c5
+#define F367TER_SFECKDIV23_MAN 0xf2c50080
+#define F367TER_SFEC_K_DIVIDER_23 0xf2c5007f
+
+/* SFKDIV34 */
+#define R367TER_SFKDIV34 0xf2c6
+#define F367TER_SFECKDIV34_MAN 0xf2c60080
+#define F367TER_SFEC_K_DIVIDER_34 0xf2c6007f
+
+/* SFKDIV56 */
+#define R367TER_SFKDIV56 0xf2c7
+#define F367TER_SFECKDIV56_MAN 0xf2c70080
+#define F367TER_SFEC_K_DIVIDER_56 0xf2c7007f
+
+/* SFKDIV67 */
+#define R367TER_SFKDIV67 0xf2c8
+#define F367TER_SFECKDIV67_MAN 0xf2c80080
+#define F367TER_SFEC_K_DIVIDER_67 0xf2c8007f
+
+/* SFKDIV78 */
+#define R367TER_SFKDIV78 0xf2c9
+#define F367TER_SFECKDIV78_MAN 0xf2c90080
+#define F367TER_SFEC_K_DIVIDER_78 0xf2c9007f
+
+/* SFDILSTKM */
+#define R367TER_SFDILSTKM 0xf2ca
+#define F367TER_SFEC_PACKCPT 0xf2ca00e0
+#define F367TER_SFEC_DILSTK_HI 0xf2ca001f
+
+/* SFDILSTKL */
+#define R367TER_SFDILSTKL 0xf2cb
+#define F367TER_SFEC_DILSTK_LO 0xf2cb00ff
+
+/* SFSTATUS */
+#define R367TER_SFSTATUS 0xf2cc
+#define F367TER_SFEC_LINEOK 0xf2cc0080
+#define F367TER_SFEC_ERROR 0xf2cc0040
+#define F367TER_SFEC_DATA7 0xf2cc0020
+#define F367TER_SFEC_OVERFLOW 0xf2cc0010
+#define F367TER_SFEC_DEMODSEL2 0xf2cc0008
+#define F367TER_SFEC_NOSYNC 0xf2cc0004
+#define F367TER_SFEC_UNREGULA 0xf2cc0002
+#define F367TER_SFEC_READY 0xf2cc0001
+
+/* SFDLYH */
+#define R367TER_SFDLYH 0xf2cd
+#define F367TER_SFEC_TSTIMEVALID 0xf2cd0080
+#define F367TER_SFEC_SPEEDUP 0xf2cd0040
+#define F367TER_SFEC_STOP 0xf2cd0020
+#define F367TER_SFEC_REGULATED 0xf2cd0010
+#define F367TER_SFEC_REALSYMBOFFSET 0xf2cd000f
+
+/* SFDLYM */
+#define R367TER_SFDLYM 0xf2ce
+#define F367TER_SFEC_REALSYMBOFFSET_HI 0xf2ce00ff
+
+/* SFDLYL */
+#define R367TER_SFDLYL 0xf2cf
+#define F367TER_SFEC_REALSYMBOFFSET_LO 0xf2cf00ff
+
+/* SFDLYSETH */
+#define R367TER_SFDLYSETH 0xf2d0
+#define F367TER_SFEC_OFFSET 0xf2d000e0
+#define F367TER_SFECDLYSETH_4 0xf2d00010
+#define F367TER_RST_SFEC 0xf2d00008
+#define F367TER_SFECDLYSETH_2 0xf2d00004
+#define F367TER_SFEC_DISABLE 0xf2d00002
+#define F367TER_SFEC_UNREGUL 0xf2d00001
+
+/* SFDLYSETM */
+#define R367TER_SFDLYSETM 0xf2d1
+#define F367TER_SFECDLYSETM_7 0xf2d10080
+#define F367TER_SFEC_SYMBOFFSET_HI 0xf2d1007f
+
+/* SFDLYSETL */
+#define R367TER_SFDLYSETL 0xf2d2
+#define F367TER_SFEC_SYMBOFFSET_LO 0xf2d200ff
+
+/* SFOBSCFG */
+#define R367TER_SFOBSCFG 0xf2d3
+#define F367TER_SFEC_OBSCFG 0xf2d300ff
+
+/* SFOBSM */
+#define R367TER_SFOBSM 0xf2d4
+#define F367TER_SFEC_OBSDATA_HI 0xf2d400ff
+
+/* SFOBSL */
+#define R367TER_SFOBSL 0xf2d5
+#define F367TER_SFEC_OBSDATA_LO 0xf2d500ff
+
+/* SFECINFO */
+#define R367TER_SFECINFO 0xf2d6
+#define F367TER_SFECINFO_7 0xf2d60080
+#define F367TER_SFEC_SYNCDLSB 0xf2d60070
+#define F367TER_SFCE_S1cPHASE 0xf2d6000f
+
+/* SFERRCTRL */
+#define R367TER_SFERRCTRL 0xf2d8
+#define F367TER_SFEC_ERR_SOURCE 0xf2d800f0
+#define F367TER_SFERRCTRL_3 0xf2d80008
+#define F367TER_SFEC_NUM_EVENT 0xf2d80007
+
+/* SFERRCNTH */
+#define R367TER_SFERRCNTH 0xf2d9
+#define F367TER_SFERRC_OLDVALUE 0xf2d90080
+#define F367TER_SFEC_ERR_CNT 0xf2d9007f
+
+/* SFERRCNTM */
+#define R367TER_SFERRCNTM 0xf2da
+#define F367TER_SFEC_ERR_CNT_HI 0xf2da00ff
+
+/* SFERRCNTL */
+#define R367TER_SFERRCNTL 0xf2db
+#define F367TER_SFEC_ERR_CNT_LO 0xf2db00ff
+
+/* SYMBRATEM */
+#define R367TER_SYMBRATEM 0xf2e0
+#define F367TER_DEFGEN_SYMBRATE_HI 0xf2e000ff
+
+/* SYMBRATEL */
+#define R367TER_SYMBRATEL 0xf2e1
+#define F367TER_DEFGEN_SYMBRATE_LO 0xf2e100ff
+
+/* SYMBSTATUS */
+#define R367TER_SYMBSTATUS 0xf2e2
+#define F367TER_SYMBDLINE2_OFF 0xf2e20080
+#define F367TER_SDDL_REINIT1 0xf2e20040
+#define F367TER_SDD_REINIT1 0xf2e20020
+#define F367TER_TOKENID_ERROR 0xf2e20010
+#define F367TER_SYMBRATE_OVERFLOW 0xf2e20008
+#define F367TER_SYMBRATE_UNDERFLOW 0xf2e20004
+#define F367TER_TOKENID_RSTEVENT 0xf2e20002
+#define F367TER_TOKENID_RESET1 0xf2e20001
+
+/* SYMBCFG */
+#define R367TER_SYMBCFG 0xf2e3
+#define F367TER_SYMBCFG_7 0xf2e30080
+#define F367TER_SYMBCFG_6 0xf2e30040
+#define F367TER_SYMBCFG_5 0xf2e30020
+#define F367TER_SYMBCFG_4 0xf2e30010
+#define F367TER_SYMRATE_FSPEED 0xf2e3000c
+#define F367TER_SYMRATE_SSPEED 0xf2e30003
+
+/* SYMBFIFOM */
+#define R367TER_SYMBFIFOM 0xf2e4
+#define F367TER_SYMBFIFOM_7 0xf2e40080
+#define F367TER_SYMBFIFOM_6 0xf2e40040
+#define F367TER_DEFGEN_SYMFIFO_HI 0xf2e4003f
+
+/* SYMBFIFOL */
+#define R367TER_SYMBFIFOL 0xf2e5
+#define F367TER_DEFGEN_SYMFIFO_LO 0xf2e500ff
+
+/* SYMBOFFSM */
+#define R367TER_SYMBOFFSM 0xf2e6
+#define F367TER_TOKENID_RESET2 0xf2e60080
+#define F367TER_SDDL_REINIT2 0xf2e60040
+#define F367TER_SDD_REINIT2 0xf2e60020
+#define F367TER_SYMBOFFSM_4 0xf2e60010
+#define F367TER_SYMBOFFSM_3 0xf2e60008
+#define F367TER_DEFGEN_SYMBOFFSET_HI 0xf2e60007
+
+/* SYMBOFFSL */
+#define R367TER_SYMBOFFSL 0xf2e7
+#define F367TER_DEFGEN_SYMBOFFSET_LO 0xf2e700ff
+
+/* DEBUG_LT4 */
+#define R367TER_DEBUG_LT4 0xf400
+#define F367TER_F_DEBUG_LT4 0xf40000ff
+
+/* DEBUG_LT5 */
+#define R367TER_DEBUG_LT5 0xf401
+#define F367TER_F_DEBUG_LT5 0xf40100ff
+
+/* DEBUG_LT6 */
+#define R367TER_DEBUG_LT6 0xf402
+#define F367TER_F_DEBUG_LT6 0xf40200ff
+
+/* DEBUG_LT7 */
+#define R367TER_DEBUG_LT7 0xf403
+#define F367TER_F_DEBUG_LT7 0xf40300ff
+
+/* DEBUG_LT8 */
+#define R367TER_DEBUG_LT8 0xf404
+#define F367TER_F_DEBUG_LT8 0xf40400ff
+
+/* DEBUG_LT9 */
+#define R367TER_DEBUG_LT9 0xf405
+#define F367TER_F_DEBUG_LT9 0xf40500ff
+
+#define STV0367TER_NBREGS 445
+
+/* ID */
+#define R367CAB_ID 0xf000
+#define F367CAB_IDENTIFICATIONREGISTER 0xf00000ff
+
+/* I2CRPT */
+#define R367CAB_I2CRPT 0xf001
+#define F367CAB_I2CT_ON 0xf0010080
+#define F367CAB_ENARPT_LEVEL 0xf0010070
+#define F367CAB_SCLT_DELAY 0xf0010008
+#define F367CAB_SCLT_NOD 0xf0010004
+#define F367CAB_STOP_ENABLE 0xf0010002
+#define F367CAB_SDAT_NOD 0xf0010001
+
+/* TOPCTRL */
+#define R367CAB_TOPCTRL 0xf002
+#define F367CAB_STDBY 0xf0020080
+#define F367CAB_STDBY_CORE 0xf0020020
+#define F367CAB_QAM_COFDM 0xf0020010
+#define F367CAB_TS_DIS 0xf0020008
+#define F367CAB_DIR_CLK_216 0xf0020004
+
+/* IOCFG0 */
+#define R367CAB_IOCFG0 0xf003
+#define F367CAB_OP0_SD 0xf0030080
+#define F367CAB_OP0_VAL 0xf0030040
+#define F367CAB_OP0_OD 0xf0030020
+#define F367CAB_OP0_INV 0xf0030010
+#define F367CAB_OP0_DACVALUE_HI 0xf003000f
+
+/* DAc0R */
+#define R367CAB_DAC0R 0xf004
+#define F367CAB_OP0_DACVALUE_LO 0xf00400ff
+
+/* IOCFG1 */
+#define R367CAB_IOCFG1 0xf005
+#define F367CAB_IP0 0xf0050040
+#define F367CAB_OP1_OD 0xf0050020
+#define F367CAB_OP1_INV 0xf0050010
+#define F367CAB_OP1_DACVALUE_HI 0xf005000f
+
+/* DAC1R */
+#define R367CAB_DAC1R 0xf006
+#define F367CAB_OP1_DACVALUE_LO 0xf00600ff
+
+/* IOCFG2 */
+#define R367CAB_IOCFG2 0xf007
+#define F367CAB_OP2_LOCK_CONF 0xf00700e0
+#define F367CAB_OP2_OD 0xf0070010
+#define F367CAB_OP2_VAL 0xf0070008
+#define F367CAB_OP1_LOCK_CONF 0xf0070007
+
+/* SDFR */
+#define R367CAB_SDFR 0xf008
+#define F367CAB_OP0_FREQ 0xf00800f0
+#define F367CAB_OP1_FREQ 0xf008000f
+
+/* AUX_CLK */
+#define R367CAB_AUX_CLK 0xf00a
+#define F367CAB_AUXFEC_CTL 0xf00a00c0
+#define F367CAB_DIS_CKX4 0xf00a0020
+#define F367CAB_CKSEL 0xf00a0018
+#define F367CAB_CKDIV_PROG 0xf00a0006
+#define F367CAB_AUXCLK_ENA 0xf00a0001
+
+/* FREESYS1 */
+#define R367CAB_FREESYS1 0xf00b
+#define F367CAB_FREESYS_1 0xf00b00ff
+
+/* FREESYS2 */
+#define R367CAB_FREESYS2 0xf00c
+#define F367CAB_FREESYS_2 0xf00c00ff
+
+/* FREESYS3 */
+#define R367CAB_FREESYS3 0xf00d
+#define F367CAB_FREESYS_3 0xf00d00ff
+
+/* GPIO_CFG */
+#define R367CAB_GPIO_CFG 0xf00e
+#define F367CAB_GPIO7_OD 0xf00e0080
+#define F367CAB_GPIO7_CFG 0xf00e0040
+#define F367CAB_GPIO6_OD 0xf00e0020
+#define F367CAB_GPIO6_CFG 0xf00e0010
+#define F367CAB_GPIO5_OD 0xf00e0008
+#define F367CAB_GPIO5_CFG 0xf00e0004
+#define F367CAB_GPIO4_OD 0xf00e0002
+#define F367CAB_GPIO4_CFG 0xf00e0001
+
+/* GPIO_CMD */
+#define R367CAB_GPIO_CMD 0xf00f
+#define F367CAB_GPIO7_VAL 0xf00f0008
+#define F367CAB_GPIO6_VAL 0xf00f0004
+#define F367CAB_GPIO5_VAL 0xf00f0002
+#define F367CAB_GPIO4_VAL 0xf00f0001
+
+/* TSTRES */
+#define R367CAB_TSTRES 0xf0c0
+#define F367CAB_FRES_DISPLAY 0xf0c00080
+#define F367CAB_FRES_FIFO_AD 0xf0c00020
+#define F367CAB_FRESRS 0xf0c00010
+#define F367CAB_FRESACS 0xf0c00008
+#define F367CAB_FRESFEC 0xf0c00004
+#define F367CAB_FRES_PRIF 0xf0c00002
+#define F367CAB_FRESCORE 0xf0c00001
+
+/* ANACTRL */
+#define R367CAB_ANACTRL 0xf0c1
+#define F367CAB_BYPASS_XTAL 0xf0c10040
+#define F367CAB_BYPASS_PLLXN 0xf0c1000c
+#define F367CAB_DIS_PAD_OSC 0xf0c10002
+#define F367CAB_STDBY_PLLXN 0xf0c10001
+
+/* TSTBUS */
+#define R367CAB_TSTBUS 0xf0c2
+#define F367CAB_TS_BYTE_CLK_INV 0xf0c20080
+#define F367CAB_CFG_IP 0xf0c20070
+#define F367CAB_CFG_TST 0xf0c2000f
+
+/* RF_AGC1 */
+#define R367CAB_RF_AGC1 0xf0d4
+#define F367CAB_RF_AGC1_LEVEL_HI 0xf0d400ff
+
+/* RF_AGC2 */
+#define R367CAB_RF_AGC2 0xf0d5
+#define F367CAB_REF_ADGP 0xf0d50080
+#define F367CAB_STDBY_ADCGP 0xf0d50020
+#define F367CAB_RF_AGC1_LEVEL_LO 0xf0d50003
+
+/* ANADIGCTRL */
+#define R367CAB_ANADIGCTRL 0xf0d7
+#define F367CAB_SEL_CLKDEM 0xf0d70020
+#define F367CAB_EN_BUFFER_Q 0xf0d70010
+#define F367CAB_EN_BUFFER_I 0xf0d70008
+#define F367CAB_ADC_RIS_EGDE 0xf0d70004
+#define F367CAB_SGN_ADC 0xf0d70002
+#define F367CAB_SEL_AD12_SYNC 0xf0d70001
+
+/* PLLMDIV */
+#define R367CAB_PLLMDIV 0xf0d8
+#define F367CAB_PLL_MDIV 0xf0d800ff
+
+/* PLLNDIV */
+#define R367CAB_PLLNDIV 0xf0d9
+#define F367CAB_PLL_NDIV 0xf0d900ff
+
+/* PLLSETUP */
+#define R367CAB_PLLSETUP 0xf0da
+#define F367CAB_PLL_PDIV 0xf0da0070
+#define F367CAB_PLL_KDIV 0xf0da000f
+
+/* DUAL_AD12 */
+#define R367CAB_DUAL_AD12 0xf0db
+#define F367CAB_FS20M 0xf0db0020
+#define F367CAB_FS50M 0xf0db0010
+#define F367CAB_INMODe0 0xf0db0008
+#define F367CAB_POFFQ 0xf0db0004
+#define F367CAB_POFFI 0xf0db0002
+#define F367CAB_INMODE1 0xf0db0001
+
+/* TSTBIST */
+#define R367CAB_TSTBIST 0xf0dc
+#define F367CAB_TST_BYP_CLK 0xf0dc0080
+#define F367CAB_TST_GCLKENA_STD 0xf0dc0040
+#define F367CAB_TST_GCLKENA 0xf0dc0020
+#define F367CAB_TST_MEMBIST 0xf0dc001f
+
+/* CTRL_1 */
+#define R367CAB_CTRL_1 0xf402
+#define F367CAB_SOFT_RST 0xf4020080
+#define F367CAB_EQU_RST 0xf4020008
+#define F367CAB_CRL_RST 0xf4020004
+#define F367CAB_TRL_RST 0xf4020002
+#define F367CAB_AGC_RST 0xf4020001
+
+/* CTRL_2 */
+#define R367CAB_CTRL_2 0xf403
+#define F367CAB_DEINT_RST 0xf4030008
+#define F367CAB_RS_RST 0xf4030004
+
+/* IT_STATUS1 */
+#define R367CAB_IT_STATUS1 0xf408
+#define F367CAB_SWEEP_OUT 0xf4080080
+#define F367CAB_FSM_CRL 0xf4080040
+#define F367CAB_CRL_LOCK 0xf4080020
+#define F367CAB_MFSM 0xf4080010
+#define F367CAB_TRL_LOCK 0xf4080008
+#define F367CAB_TRL_AGC_LIMIT 0xf4080004
+#define F367CAB_ADJ_AGC_LOCK 0xf4080002
+#define F367CAB_AGC_QAM_LOCK 0xf4080001
+
+/* IT_STATUS2 */
+#define R367CAB_IT_STATUS2 0xf409
+#define F367CAB_TSMF_CNT 0xf4090080
+#define F367CAB_TSMF_EOF 0xf4090040
+#define F367CAB_TSMF_RDY 0xf4090020
+#define F367CAB_FEC_NOCORR 0xf4090010
+#define F367CAB_SYNCSTATE 0xf4090008
+#define F367CAB_DEINT_LOCK 0xf4090004
+#define F367CAB_FADDING_FRZ 0xf4090002
+#define F367CAB_TAPMON_ALARM 0xf4090001
+
+/* IT_EN1 */
+#define R367CAB_IT_EN1 0xf40a
+#define F367CAB_SWEEP_OUTE 0xf40a0080
+#define F367CAB_FSM_CRLE 0xf40a0040
+#define F367CAB_CRL_LOCKE 0xf40a0020
+#define F367CAB_MFSME 0xf40a0010
+#define F367CAB_TRL_LOCKE 0xf40a0008
+#define F367CAB_TRL_AGC_LIMITE 0xf40a0004
+#define F367CAB_ADJ_AGC_LOCKE 0xf40a0002
+#define F367CAB_AGC_LOCKE 0xf40a0001
+
+/* IT_EN2 */
+#define R367CAB_IT_EN2 0xf40b
+#define F367CAB_TSMF_CNTE 0xf40b0080
+#define F367CAB_TSMF_EOFE 0xf40b0040
+#define F367CAB_TSMF_RDYE 0xf40b0020
+#define F367CAB_FEC_NOCORRE 0xf40b0010
+#define F367CAB_SYNCSTATEE 0xf40b0008
+#define F367CAB_DEINT_LOCKE 0xf40b0004
+#define F367CAB_FADDING_FRZE 0xf40b0002
+#define F367CAB_TAPMON_ALARME 0xf40b0001
+
+/* CTRL_STATUS */
+#define R367CAB_CTRL_STATUS 0xf40c
+#define F367CAB_QAMFEC_LOCK 0xf40c0004
+#define F367CAB_TSMF_LOCK 0xf40c0002
+#define F367CAB_TSMF_ERROR 0xf40c0001
+
+/* TEST_CTL */
+#define R367CAB_TEST_CTL 0xf40f
+#define F367CAB_TST_BLK_SEL 0xf40f0060
+#define F367CAB_TST_BUS_SEL 0xf40f001f
+
+/* AGC_CTL */
+#define R367CAB_AGC_CTL 0xf410
+#define F367CAB_AGC_LCK_TH 0xf41000f0
+#define F367CAB_AGC_ACCUMRSTSEL 0xf4100007
+
+/* AGC_IF_CFG */
+#define R367CAB_AGC_IF_CFG 0xf411
+#define F367CAB_AGC_IF_BWSEL 0xf41100f0
+#define F367CAB_AGC_IF_FREEZE 0xf4110002
+
+/* AGC_RF_CFG */
+#define R367CAB_AGC_RF_CFG 0xf412
+#define F367CAB_AGC_RF_BWSEL 0xf4120070
+#define F367CAB_AGC_RF_FREEZE 0xf4120002
+
+/* AGC_PWM_CFG */
+#define R367CAB_AGC_PWM_CFG 0xf413
+#define F367CAB_AGC_RF_PWM_TST 0xf4130080
+#define F367CAB_AGC_RF_PWM_INV 0xf4130040
+#define F367CAB_AGC_IF_PWM_TST 0xf4130008
+#define F367CAB_AGC_IF_PWM_INV 0xf4130004
+#define F367CAB_AGC_PWM_CLKDIV 0xf4130003
+
+/* AGC_PWR_REF_L */
+#define R367CAB_AGC_PWR_REF_L 0xf414
+#define F367CAB_AGC_PWRREF_LO 0xf41400ff
+
+/* AGC_PWR_REF_H */
+#define R367CAB_AGC_PWR_REF_H 0xf415
+#define F367CAB_AGC_PWRREF_HI 0xf4150003
+
+/* AGC_RF_TH_L */
+#define R367CAB_AGC_RF_TH_L 0xf416
+#define F367CAB_AGC_RF_TH_LO 0xf41600ff
+
+/* AGC_RF_TH_H */
+#define R367CAB_AGC_RF_TH_H 0xf417
+#define F367CAB_AGC_RF_TH_HI 0xf417000f
+
+/* AGC_IF_LTH_L */
+#define R367CAB_AGC_IF_LTH_L 0xf418
+#define F367CAB_AGC_IF_THLO_LO 0xf41800ff
+
+/* AGC_IF_LTH_H */
+#define R367CAB_AGC_IF_LTH_H 0xf419
+#define F367CAB_AGC_IF_THLO_HI 0xf419000f
+
+/* AGC_IF_HTH_L */
+#define R367CAB_AGC_IF_HTH_L 0xf41a
+#define F367CAB_AGC_IF_THHI_LO 0xf41a00ff
+
+/* AGC_IF_HTH_H */
+#define R367CAB_AGC_IF_HTH_H 0xf41b
+#define F367CAB_AGC_IF_THHI_HI 0xf41b000f
+
+/* AGC_PWR_RD_L */
+#define R367CAB_AGC_PWR_RD_L 0xf41c
+#define F367CAB_AGC_PWR_WORD_LO 0xf41c00ff
+
+/* AGC_PWR_RD_M */
+#define R367CAB_AGC_PWR_RD_M 0xf41d
+#define F367CAB_AGC_PWR_WORD_ME 0xf41d00ff
+
+/* AGC_PWR_RD_H */
+#define R367CAB_AGC_PWR_RD_H 0xf41e
+#define F367CAB_AGC_PWR_WORD_HI 0xf41e0003
+
+/* AGC_PWM_IFCMD_L */
+#define R367CAB_AGC_PWM_IFCMD_L 0xf420
+#define F367CAB_AGC_IF_PWMCMD_LO 0xf42000ff
+
+/* AGC_PWM_IFCMD_H */
+#define R367CAB_AGC_PWM_IFCMD_H 0xf421
+#define F367CAB_AGC_IF_PWMCMD_HI 0xf421000f
+
+/* AGC_PWM_RFCMD_L */
+#define R367CAB_AGC_PWM_RFCMD_L 0xf422
+#define F367CAB_AGC_RF_PWMCMD_LO 0xf42200ff
+
+/* AGC_PWM_RFCMD_H */
+#define R367CAB_AGC_PWM_RFCMD_H 0xf423
+#define F367CAB_AGC_RF_PWMCMD_HI 0xf423000f
+
+/* IQDEM_CFG */
+#define R367CAB_IQDEM_CFG 0xf424
+#define F367CAB_IQDEM_CLK_SEL 0xf4240004
+#define F367CAB_IQDEM_INVIQ 0xf4240002
+#define F367CAB_IQDEM_A2dTYPE 0xf4240001
+
+/* MIX_NCO_LL */
+#define R367CAB_MIX_NCO_LL 0xf425
+#define F367CAB_MIX_NCO_INC_LL 0xf42500ff
+
+/* MIX_NCO_HL */
+#define R367CAB_MIX_NCO_HL 0xf426
+#define F367CAB_MIX_NCO_INC_HL 0xf42600ff
+
+/* MIX_NCO_HH */
+#define R367CAB_MIX_NCO_HH 0xf427
+#define F367CAB_MIX_NCO_INVCNST 0xf4270080
+#define F367CAB_MIX_NCO_INC_HH 0xf427007f
+
+/* SRC_NCO_LL */
+#define R367CAB_SRC_NCO_LL 0xf428
+#define F367CAB_SRC_NCO_INC_LL 0xf42800ff
+
+/* SRC_NCO_LH */
+#define R367CAB_SRC_NCO_LH 0xf429
+#define F367CAB_SRC_NCO_INC_LH 0xf42900ff
+
+/* SRC_NCO_HL */
+#define R367CAB_SRC_NCO_HL 0xf42a
+#define F367CAB_SRC_NCO_INC_HL 0xf42a00ff
+
+/* SRC_NCO_HH */
+#define R367CAB_SRC_NCO_HH 0xf42b
+#define F367CAB_SRC_NCO_INC_HH 0xf42b007f
+
+/* IQDEM_GAIN_SRC_L */
+#define R367CAB_IQDEM_GAIN_SRC_L 0xf42c
+#define F367CAB_GAIN_SRC_LO 0xf42c00ff
+
+/* IQDEM_GAIN_SRC_H */
+#define R367CAB_IQDEM_GAIN_SRC_H 0xf42d
+#define F367CAB_GAIN_SRC_HI 0xf42d0003
+
+/* IQDEM_DCRM_CFG_LL */
+#define R367CAB_IQDEM_DCRM_CFG_LL 0xf430
+#define F367CAB_DCRM0_DCIN_L 0xf43000ff
+
+/* IQDEM_DCRM_CFG_LH */
+#define R367CAB_IQDEM_DCRM_CFG_LH 0xf431
+#define F367CAB_DCRM1_I_DCIN_L 0xf43100fc
+#define F367CAB_DCRM0_DCIN_H 0xf4310003
+
+/* IQDEM_DCRM_CFG_HL */
+#define R367CAB_IQDEM_DCRM_CFG_HL 0xf432
+#define F367CAB_DCRM1_Q_DCIN_L 0xf43200f0
+#define F367CAB_DCRM1_I_DCIN_H 0xf432000f
+
+/* IQDEM_DCRM_CFG_HH */
+#define R367CAB_IQDEM_DCRM_CFG_HH 0xf433
+#define F367CAB_DCRM1_FRZ 0xf4330080
+#define F367CAB_DCRM0_FRZ 0xf4330040
+#define F367CAB_DCRM1_Q_DCIN_H 0xf433003f
+
+/* IQDEM_ADJ_COEFf0 */
+#define R367CAB_IQDEM_ADJ_COEFF0 0xf434
+#define F367CAB_ADJIIR_COEFF10_L 0xf43400ff
+
+/* IQDEM_ADJ_COEFF1 */
+#define R367CAB_IQDEM_ADJ_COEFF1 0xf435
+#define F367CAB_ADJIIR_COEFF11_L 0xf43500fc
+#define F367CAB_ADJIIR_COEFF10_H 0xf4350003
+
+/* IQDEM_ADJ_COEFF2 */
+#define R367CAB_IQDEM_ADJ_COEFF2 0xf436
+#define F367CAB_ADJIIR_COEFF12_L 0xf43600f0
+#define F367CAB_ADJIIR_COEFF11_H 0xf436000f
+
+/* IQDEM_ADJ_COEFF3 */
+#define R367CAB_IQDEM_ADJ_COEFF3 0xf437
+#define F367CAB_ADJIIR_COEFF20_L 0xf43700c0
+#define F367CAB_ADJIIR_COEFF12_H 0xf437003f
+
+/* IQDEM_ADJ_COEFF4 */
+#define R367CAB_IQDEM_ADJ_COEFF4 0xf438
+#define F367CAB_ADJIIR_COEFF20_H 0xf43800ff
+
+/* IQDEM_ADJ_COEFF5 */
+#define R367CAB_IQDEM_ADJ_COEFF5 0xf439
+#define F367CAB_ADJIIR_COEFF21_L 0xf43900ff
+
+/* IQDEM_ADJ_COEFF6 */
+#define R367CAB_IQDEM_ADJ_COEFF6 0xf43a
+#define F367CAB_ADJIIR_COEFF22_L 0xf43a00fc
+#define F367CAB_ADJIIR_COEFF21_H 0xf43a0003
+
+/* IQDEM_ADJ_COEFF7 */
+#define R367CAB_IQDEM_ADJ_COEFF7 0xf43b
+#define F367CAB_ADJIIR_COEFF22_H 0xf43b000f
+
+/* IQDEM_ADJ_EN */
+#define R367CAB_IQDEM_ADJ_EN 0xf43c
+#define F367CAB_ALLPASSFILT_EN 0xf43c0008
+#define F367CAB_ADJ_AGC_EN 0xf43c0004
+#define F367CAB_ADJ_COEFF_FRZ 0xf43c0002
+#define F367CAB_ADJ_EN 0xf43c0001
+
+/* IQDEM_ADJ_AGC_REF */
+#define R367CAB_IQDEM_ADJ_AGC_REF 0xf43d
+#define F367CAB_ADJ_AGC_REF 0xf43d00ff
+
+/* ALLPASSFILT1 */
+#define R367CAB_ALLPASSFILT1 0xf440
+#define F367CAB_ALLPASSFILT_COEFF1_LO 0xf44000ff
+
+/* ALLPASSFILT2 */
+#define R367CAB_ALLPASSFILT2 0xf441
+#define F367CAB_ALLPASSFILT_COEFF1_ME 0xf44100ff
+
+/* ALLPASSFILT3 */
+#define R367CAB_ALLPASSFILT3 0xf442
+#define F367CAB_ALLPASSFILT_COEFF2_LO 0xf44200c0
+#define F367CAB_ALLPASSFILT_COEFF1_HI 0xf442003f
+
+/* ALLPASSFILT4 */
+#define R367CAB_ALLPASSFILT4 0xf443
+#define F367CAB_ALLPASSFILT_COEFF2_MEL 0xf44300ff
+
+/* ALLPASSFILT5 */
+#define R367CAB_ALLPASSFILT5 0xf444
+#define F367CAB_ALLPASSFILT_COEFF2_MEH 0xf44400ff
+
+/* ALLPASSFILT6 */
+#define R367CAB_ALLPASSFILT6 0xf445
+#define F367CAB_ALLPASSFILT_COEFF3_LO 0xf44500f0
+#define F367CAB_ALLPASSFILT_COEFF2_HI 0xf445000f
+
+/* ALLPASSFILT7 */
+#define R367CAB_ALLPASSFILT7 0xf446
+#define F367CAB_ALLPASSFILT_COEFF3_MEL 0xf44600ff
+
+/* ALLPASSFILT8 */
+#define R367CAB_ALLPASSFILT8 0xf447
+#define F367CAB_ALLPASSFILT_COEFF3_MEH 0xf44700ff
+
+/* ALLPASSFILT9 */
+#define R367CAB_ALLPASSFILT9 0xf448
+#define F367CAB_ALLPASSFILT_COEFF4_LO 0xf44800fc
+#define F367CAB_ALLPASSFILT_COEFF3_HI 0xf4480003
+
+/* ALLPASSFILT10 */
+#define R367CAB_ALLPASSFILT10 0xf449
+#define F367CAB_ALLPASSFILT_COEFF4_ME 0xf44900ff
+
+/* ALLPASSFILT11 */
+#define R367CAB_ALLPASSFILT11 0xf44a
+#define F367CAB_ALLPASSFILT_COEFF4_HI 0xf44a00ff
+
+/* TRL_AGC_CFG */
+#define R367CAB_TRL_AGC_CFG 0xf450
+#define F367CAB_TRL_AGC_FREEZE 0xf4500080
+#define F367CAB_TRL_AGC_REF 0xf450007f
+
+/* TRL_LPF_CFG */
+#define R367CAB_TRL_LPF_CFG 0xf454
+#define F367CAB_NYQPOINT_INV 0xf4540040
+#define F367CAB_TRL_SHIFT 0xf4540030
+#define F367CAB_NYQ_COEFF_SEL 0xf454000c
+#define F367CAB_TRL_LPF_FREEZE 0xf4540002
+#define F367CAB_TRL_LPF_CRT 0xf4540001
+
+/* TRL_LPF_ACQ_GAIN */
+#define R367CAB_TRL_LPF_ACQ_GAIN 0xf455
+#define F367CAB_TRL_GDIR_ACQ 0xf4550070
+#define F367CAB_TRL_GINT_ACQ 0xf4550007
+
+/* TRL_LPF_TRK_GAIN */
+#define R367CAB_TRL_LPF_TRK_GAIN 0xf456
+#define F367CAB_TRL_GDIR_TRK 0xf4560070
+#define F367CAB_TRL_GINT_TRK 0xf4560007
+
+/* TRL_LPF_OUT_GAIN */
+#define R367CAB_TRL_LPF_OUT_GAIN 0xf457
+#define F367CAB_TRL_GAIN_OUT 0xf4570007
+
+/* TRL_LOCKDET_LTH */
+#define R367CAB_TRL_LOCKDET_LTH 0xf458
+#define F367CAB_TRL_LCK_THLO 0xf4580007
+
+/* TRL_LOCKDET_HTH */
+#define R367CAB_TRL_LOCKDET_HTH 0xf459
+#define F367CAB_TRL_LCK_THHI 0xf45900ff
+
+/* TRL_LOCKDET_TRGVAL */
+#define R367CAB_TRL_LOCKDET_TRGVAL 0xf45a
+#define F367CAB_TRL_LCK_TRG 0xf45a00ff
+
+/* IQ_QAM */
+#define R367CAB_IQ_QAM 0xf45c
+#define F367CAB_IQ_INPUT 0xf45c0008
+#define F367CAB_DETECT_MODE 0xf45c0007
+
+/* FSM_STATE */
+#define R367CAB_FSM_STATE 0xf460
+#define F367CAB_CRL_DFE 0xf4600080
+#define F367CAB_DFE_START 0xf4600040
+#define F367CAB_CTRLG_START 0xf4600030
+#define F367CAB_FSM_FORCESTATE 0xf460000f
+
+/* FSM_CTL */
+#define R367CAB_FSM_CTL 0xf461
+#define F367CAB_FEC2_EN 0xf4610040
+#define F367CAB_SIT_EN 0xf4610020
+#define F367CAB_TRL_AHEAD 0xf4610010
+#define F367CAB_TRL2_EN 0xf4610008
+#define F367CAB_FSM_EQA1_EN 0xf4610004
+#define F367CAB_FSM_BKP_DIS 0xf4610002
+#define F367CAB_FSM_FORCE_EN 0xf4610001
+
+/* FSM_STS */
+#define R367CAB_FSM_STS 0xf462
+#define F367CAB_FSM_STATUS 0xf462000f
+
+/* FSM_SNR0_HTH */
+#define R367CAB_FSM_SNR0_HTH 0xf463
+#define F367CAB_SNR0_HTH 0xf46300ff
+
+/* FSM_SNR1_HTH */
+#define R367CAB_FSM_SNR1_HTH 0xf464
+#define F367CAB_SNR1_HTH 0xf46400ff
+
+/* FSM_SNR2_HTH */
+#define R367CAB_FSM_SNR2_HTH 0xf465
+#define F367CAB_SNR2_HTH 0xf46500ff
+
+/* FSM_SNR0_LTH */
+#define R367CAB_FSM_SNR0_LTH 0xf466
+#define F367CAB_SNR0_LTH 0xf46600ff
+
+/* FSM_SNR1_LTH */
+#define R367CAB_FSM_SNR1_LTH 0xf467
+#define F367CAB_SNR1_LTH 0xf46700ff
+
+/* FSM_EQA1_HTH */
+#define R367CAB_FSM_EQA1_HTH 0xf468
+#define F367CAB_SNR3_HTH_LO 0xf46800f0
+#define F367CAB_EQA1_HTH 0xf468000f
+
+/* FSM_TEMPO */
+#define R367CAB_FSM_TEMPO 0xf469
+#define F367CAB_SIT 0xf46900c0
+#define F367CAB_WST 0xf4690038
+#define F367CAB_ELT 0xf4690006
+#define F367CAB_SNR3_HTH_HI 0xf4690001
+
+/* FSM_CONFIG */
+#define R367CAB_FSM_CONFIG 0xf46a
+#define F367CAB_FEC2_DFEOFF 0xf46a0004
+#define F367CAB_PRIT_STATE 0xf46a0002
+#define F367CAB_MODMAP_STATE 0xf46a0001
+
+/* EQU_I_TESTTAP_L */
+#define R367CAB_EQU_I_TESTTAP_L 0xf474
+#define F367CAB_I_TEST_TAP_L 0xf47400ff
+
+/* EQU_I_TESTTAP_M */
+#define R367CAB_EQU_I_TESTTAP_M 0xf475
+#define F367CAB_I_TEST_TAP_M 0xf47500ff
+
+/* EQU_I_TESTTAP_H */
+#define R367CAB_EQU_I_TESTTAP_H 0xf476
+#define F367CAB_I_TEST_TAP_H 0xf476001f
+
+/* EQU_TESTAP_CFG */
+#define R367CAB_EQU_TESTAP_CFG 0xf477
+#define F367CAB_TEST_FFE_DFE_SEL 0xf4770040
+#define F367CAB_TEST_TAP_SELECT 0xf477003f
+
+/* EQU_Q_TESTTAP_L */
+#define R367CAB_EQU_Q_TESTTAP_L 0xf478
+#define F367CAB_Q_TEST_TAP_L 0xf47800ff
+
+/* EQU_Q_TESTTAP_M */
+#define R367CAB_EQU_Q_TESTTAP_M 0xf479
+#define F367CAB_Q_TEST_TAP_M 0xf47900ff
+
+/* EQU_Q_TESTTAP_H */
+#define R367CAB_EQU_Q_TESTTAP_H 0xf47a
+#define F367CAB_Q_TEST_TAP_H 0xf47a001f
+
+/* EQU_TAP_CTRL */
+#define R367CAB_EQU_TAP_CTRL 0xf47b
+#define F367CAB_MTAP_FRZ 0xf47b0010
+#define F367CAB_PRE_FREEZE 0xf47b0008
+#define F367CAB_DFE_TAPMON_EN 0xf47b0004
+#define F367CAB_FFE_TAPMON_EN 0xf47b0002
+#define F367CAB_MTAP_ONLY 0xf47b0001
+
+/* EQU_CTR_CRL_CONTROL_L */
+#define R367CAB_EQU_CTR_CRL_CONTROL_L 0xf47c
+#define F367CAB_EQU_CTR_CRL_CONTROL_LO 0xf47c00ff
+
+/* EQU_CTR_CRL_CONTROL_H */
+#define R367CAB_EQU_CTR_CRL_CONTROL_H 0xf47d
+#define F367CAB_EQU_CTR_CRL_CONTROL_HI 0xf47d00ff
+
+/* EQU_CTR_HIPOW_L */
+#define R367CAB_EQU_CTR_HIPOW_L 0xf47e
+#define F367CAB_CTR_HIPOW_L 0xf47e00ff
+
+/* EQU_CTR_HIPOW_H */
+#define R367CAB_EQU_CTR_HIPOW_H 0xf47f
+#define F367CAB_CTR_HIPOW_H 0xf47f00ff
+
+/* EQU_I_EQU_LO */
+#define R367CAB_EQU_I_EQU_LO 0xf480
+#define F367CAB_EQU_I_EQU_L 0xf48000ff
+
+/* EQU_I_EQU_HI */
+#define R367CAB_EQU_I_EQU_HI 0xf481
+#define F367CAB_EQU_I_EQU_H 0xf4810003
+
+/* EQU_Q_EQU_LO */
+#define R367CAB_EQU_Q_EQU_LO 0xf482
+#define F367CAB_EQU_Q_EQU_L 0xf48200ff
+
+/* EQU_Q_EQU_HI */
+#define R367CAB_EQU_Q_EQU_HI 0xf483
+#define F367CAB_EQU_Q_EQU_H 0xf4830003
+
+/* EQU_MAPPER */
+#define R367CAB_EQU_MAPPER 0xf484
+#define F367CAB_QUAD_AUTO 0xf4840080
+#define F367CAB_QUAD_INV 0xf4840040
+#define F367CAB_QAM_MODE 0xf4840007
+
+/* EQU_SWEEP_RATE */
+#define R367CAB_EQU_SWEEP_RATE 0xf485
+#define F367CAB_SNR_PER 0xf48500c0
+#define F367CAB_SWEEP_RATE 0xf485003f
+
+/* EQU_SNR_LO */
+#define R367CAB_EQU_SNR_LO 0xf486
+#define F367CAB_SNR_LO 0xf48600ff
+
+/* EQU_SNR_HI */
+#define R367CAB_EQU_SNR_HI 0xf487
+#define F367CAB_SNR_HI 0xf48700ff
+
+/* EQU_GAMMA_LO */
+#define R367CAB_EQU_GAMMA_LO 0xf488
+#define F367CAB_GAMMA_LO 0xf48800ff
+
+/* EQU_GAMMA_HI */
+#define R367CAB_EQU_GAMMA_HI 0xf489
+#define F367CAB_GAMMA_ME 0xf48900ff
+
+/* EQU_ERR_GAIN */
+#define R367CAB_EQU_ERR_GAIN 0xf48a
+#define F367CAB_EQA1MU 0xf48a0070
+#define F367CAB_CRL2MU 0xf48a000e
+#define F367CAB_GAMMA_HI 0xf48a0001
+
+/* EQU_RADIUS */
+#define R367CAB_EQU_RADIUS 0xf48b
+#define F367CAB_RADIUS 0xf48b00ff
+
+/* EQU_FFE_MAINTAP */
+#define R367CAB_EQU_FFE_MAINTAP 0xf48c
+#define F367CAB_FFE_MAINTAP_INIT 0xf48c00ff
+
+/* EQU_FFE_LEAKAGE */
+#define R367CAB_EQU_FFE_LEAKAGE 0xf48e
+#define F367CAB_LEAK_PER 0xf48e00f0
+#define F367CAB_EQU_OUTSEL 0xf48e0002
+#define F367CAB_PNT2dFE 0xf48e0001
+
+/* EQU_FFE_MAINTAP_POS */
+#define R367CAB_EQU_FFE_MAINTAP_POS 0xf48f
+#define F367CAB_FFE_LEAK_EN 0xf48f0080
+#define F367CAB_DFE_LEAK_EN 0xf48f0040
+#define F367CAB_FFE_MAINTAP_POS 0xf48f003f
+
+/* EQU_GAIN_WIDE */
+#define R367CAB_EQU_GAIN_WIDE 0xf490
+#define F367CAB_DFE_GAIN_WIDE 0xf49000f0
+#define F367CAB_FFE_GAIN_WIDE 0xf490000f
+
+/* EQU_GAIN_NARROW */
+#define R367CAB_EQU_GAIN_NARROW 0xf491
+#define F367CAB_DFE_GAIN_NARROW 0xf49100f0
+#define F367CAB_FFE_GAIN_NARROW 0xf491000f
+
+/* EQU_CTR_LPF_GAIN */
+#define R367CAB_EQU_CTR_LPF_GAIN 0xf492
+#define F367CAB_CTR_GTO 0xf4920080
+#define F367CAB_CTR_GDIR 0xf4920070
+#define F367CAB_SWEEP_EN 0xf4920008
+#define F367CAB_CTR_GINT 0xf4920007
+
+/* EQU_CRL_LPF_GAIN */
+#define R367CAB_EQU_CRL_LPF_GAIN 0xf493
+#define F367CAB_CRL_GTO 0xf4930080
+#define F367CAB_CRL_GDIR 0xf4930070
+#define F367CAB_SWEEP_DIR 0xf4930008
+#define F367CAB_CRL_GINT 0xf4930007
+
+/* EQU_GLOBAL_GAIN */
+#define R367CAB_EQU_GLOBAL_GAIN 0xf494
+#define F367CAB_CRL_GAIN 0xf49400f8
+#define F367CAB_CTR_INC_GAIN 0xf4940004
+#define F367CAB_CTR_FRAC 0xf4940003
+
+/* EQU_CRL_LD_SEN */
+#define R367CAB_EQU_CRL_LD_SEN 0xf495
+#define F367CAB_CTR_BADPOINT_EN 0xf4950080
+#define F367CAB_CTR_GAIN 0xf4950070
+#define F367CAB_LIMANEN 0xf4950008
+#define F367CAB_CRL_LD_SEN 0xf4950007
+
+/* EQU_CRL_LD_VAL */
+#define R367CAB_EQU_CRL_LD_VAL 0xf496
+#define F367CAB_CRL_BISTH_LIMIT 0xf4960080
+#define F367CAB_CARE_EN 0xf4960040
+#define F367CAB_CRL_LD_PER 0xf4960030
+#define F367CAB_CRL_LD_WST 0xf496000c
+#define F367CAB_CRL_LD_TFS 0xf4960003
+
+/* EQU_CRL_TFR */
+#define R367CAB_EQU_CRL_TFR 0xf497
+#define F367CAB_CRL_LD_TFR 0xf49700ff
+
+/* EQU_CRL_BISTH_LO */
+#define R367CAB_EQU_CRL_BISTH_LO 0xf498
+#define F367CAB_CRL_BISTH_LO 0xf49800ff
+
+/* EQU_CRL_BISTH_HI */
+#define R367CAB_EQU_CRL_BISTH_HI 0xf499
+#define F367CAB_CRL_BISTH_HI 0xf49900ff
+
+/* EQU_SWEEP_RANGE_LO */
+#define R367CAB_EQU_SWEEP_RANGE_LO 0xf49a
+#define F367CAB_SWEEP_RANGE_LO 0xf49a00ff
+
+/* EQU_SWEEP_RANGE_HI */
+#define R367CAB_EQU_SWEEP_RANGE_HI 0xf49b
+#define F367CAB_SWEEP_RANGE_HI 0xf49b00ff
+
+/* EQU_CRL_LIMITER */
+#define R367CAB_EQU_CRL_LIMITER 0xf49c
+#define F367CAB_BISECTOR_EN 0xf49c0080
+#define F367CAB_PHEST128_EN 0xf49c0040
+#define F367CAB_CRL_LIM 0xf49c003f
+
+/* EQU_MODULUS_MAP */
+#define R367CAB_EQU_MODULUS_MAP 0xf49d
+#define F367CAB_PNT_DEPTH 0xf49d00e0
+#define F367CAB_MODULUS_CMP 0xf49d001f
+
+/* EQU_PNT_GAIN */
+#define R367CAB_EQU_PNT_GAIN 0xf49e
+#define F367CAB_PNT_EN 0xf49e0080
+#define F367CAB_MODULUSMAP_EN 0xf49e0040
+#define F367CAB_PNT_GAIN 0xf49e003f
+
+/* FEC_AC_CTR_0 */
+#define R367CAB_FEC_AC_CTR_0 0xf4a8
+#define F367CAB_BE_BYPASS 0xf4a80020
+#define F367CAB_REFRESH47 0xf4a80010
+#define F367CAB_CT_NBST 0xf4a80008
+#define F367CAB_TEI_ENA 0xf4a80004
+#define F367CAB_DS_ENA 0xf4a80002
+#define F367CAB_TSMF_EN 0xf4a80001
+
+/* FEC_AC_CTR_1 */
+#define R367CAB_FEC_AC_CTR_1 0xf4a9
+#define F367CAB_DEINT_DEPTH 0xf4a900ff
+
+/* FEC_AC_CTR_2 */
+#define R367CAB_FEC_AC_CTR_2 0xf4aa
+#define F367CAB_DEINT_M 0xf4aa00f8
+#define F367CAB_DIS_UNLOCK 0xf4aa0004
+#define F367CAB_DESCR_MODE 0xf4aa0003
+
+/* FEC_AC_CTR_3 */
+#define R367CAB_FEC_AC_CTR_3 0xf4ab
+#define F367CAB_DI_UNLOCK 0xf4ab0080
+#define F367CAB_DI_FREEZE 0xf4ab0040
+#define F367CAB_MISMATCH 0xf4ab0030
+#define F367CAB_ACQ_MODE 0xf4ab000c
+#define F367CAB_TRK_MODE 0xf4ab0003
+
+/* FEC_STATUS */
+#define R367CAB_FEC_STATUS 0xf4ac
+#define F367CAB_DEINT_SMCNTR 0xf4ac00e0
+#define F367CAB_DEINT_SYNCSTATE 0xf4ac0018
+#define F367CAB_DEINT_SYNLOST 0xf4ac0004
+#define F367CAB_DESCR_SYNCSTATE 0xf4ac0002
+
+/* RS_COUNTER_0 */
+#define R367CAB_RS_COUNTER_0 0xf4ae
+#define F367CAB_BK_CT_L 0xf4ae00ff
+
+/* RS_COUNTER_1 */
+#define R367CAB_RS_COUNTER_1 0xf4af
+#define F367CAB_BK_CT_H 0xf4af00ff
+
+/* RS_COUNTER_2 */
+#define R367CAB_RS_COUNTER_2 0xf4b0
+#define F367CAB_CORR_CT_L 0xf4b000ff
+
+/* RS_COUNTER_3 */
+#define R367CAB_RS_COUNTER_3 0xf4b1
+#define F367CAB_CORR_CT_H 0xf4b100ff
+
+/* RS_COUNTER_4 */
+#define R367CAB_RS_COUNTER_4 0xf4b2
+#define F367CAB_UNCORR_CT_L 0xf4b200ff
+
+/* RS_COUNTER_5 */
+#define R367CAB_RS_COUNTER_5 0xf4b3
+#define F367CAB_UNCORR_CT_H 0xf4b300ff
+
+/* BERT_0 */
+#define R367CAB_BERT_0 0xf4b4
+#define F367CAB_RS_NOCORR 0xf4b40004
+#define F367CAB_CT_HOLD 0xf4b40002
+#define F367CAB_CT_CLEAR 0xf4b40001
+
+/* BERT_1 */
+#define R367CAB_BERT_1 0xf4b5
+#define F367CAB_BERT_ON 0xf4b50020
+#define F367CAB_BERT_ERR_SRC 0xf4b50010
+#define F367CAB_BERT_ERR_MODE 0xf4b50008
+#define F367CAB_BERT_NBYTE 0xf4b50007
+
+/* BERT_2 */
+#define R367CAB_BERT_2 0xf4b6
+#define F367CAB_BERT_ERRCOUNT_L 0xf4b600ff
+
+/* BERT_3 */
+#define R367CAB_BERT_3 0xf4b7
+#define F367CAB_BERT_ERRCOUNT_H 0xf4b700ff
+
+/* OUTFORMAT_0 */
+#define R367CAB_OUTFORMAT_0 0xf4b8
+#define F367CAB_CLK_POLARITY 0xf4b80080
+#define F367CAB_FEC_TYPE 0xf4b80040
+#define F367CAB_SYNC_STRIP 0xf4b80008
+#define F367CAB_TS_SWAP 0xf4b80004
+#define F367CAB_OUTFORMAT 0xf4b80003
+
+/* OUTFORMAT_1 */
+#define R367CAB_OUTFORMAT_1 0xf4b9
+#define F367CAB_CI_DIVRANGE 0xf4b900ff
+
+/* SMOOTHER_2 */
+#define R367CAB_SMOOTHER_2 0xf4be
+#define F367CAB_FIFO_BYPASS 0xf4be0020
+
+/* TSMF_CTRL_0 */
+#define R367CAB_TSMF_CTRL_0 0xf4c0
+#define F367CAB_TS_NUMBER 0xf4c0001e
+#define F367CAB_SEL_MODE 0xf4c00001
+
+/* TSMF_CTRL_1 */
+#define R367CAB_TSMF_CTRL_1 0xf4c1
+#define F367CAB_CHECK_ERROR_BIT 0xf4c10080
+#define F367CAB_CHCK_F_SYNC 0xf4c10040
+#define F367CAB_H_MODE 0xf4c10008
+#define F367CAB_D_V_MODE 0xf4c10004
+#define F367CAB_MODE 0xf4c10003
+
+/* TSMF_CTRL_3 */
+#define R367CAB_TSMF_CTRL_3 0xf4c3
+#define F367CAB_SYNC_IN_COUNT 0xf4c300f0
+#define F367CAB_SYNC_OUT_COUNT 0xf4c3000f
+
+/* TS_ON_ID_0 */
+#define R367CAB_TS_ON_ID_0 0xf4c4
+#define F367CAB_TS_ID_L 0xf4c400ff
+
+/* TS_ON_ID_1 */
+#define R367CAB_TS_ON_ID_1 0xf4c5
+#define F367CAB_TS_ID_H 0xf4c500ff
+
+/* TS_ON_ID_2 */
+#define R367CAB_TS_ON_ID_2 0xf4c6
+#define F367CAB_ON_ID_L 0xf4c600ff
+
+/* TS_ON_ID_3 */
+#define R367CAB_TS_ON_ID_3 0xf4c7
+#define F367CAB_ON_ID_H 0xf4c700ff
+
+/* RE_STATUS_0 */
+#define R367CAB_RE_STATUS_0 0xf4c8
+#define F367CAB_RECEIVE_STATUS_L 0xf4c800ff
+
+/* RE_STATUS_1 */
+#define R367CAB_RE_STATUS_1 0xf4c9
+#define F367CAB_RECEIVE_STATUS_LH 0xf4c900ff
+
+/* RE_STATUS_2 */
+#define R367CAB_RE_STATUS_2 0xf4ca
+#define F367CAB_RECEIVE_STATUS_HL 0xf4ca00ff
+
+/* RE_STATUS_3 */
+#define R367CAB_RE_STATUS_3 0xf4cb
+#define F367CAB_RECEIVE_STATUS_HH 0xf4cb003f
+
+/* TS_STATUS_0 */
+#define R367CAB_TS_STATUS_0 0xf4cc
+#define F367CAB_TS_STATUS_L 0xf4cc00ff
+
+/* TS_STATUS_1 */
+#define R367CAB_TS_STATUS_1 0xf4cd
+#define F367CAB_TS_STATUS_H 0xf4cd007f
+
+/* TS_STATUS_2 */
+#define R367CAB_TS_STATUS_2 0xf4ce
+#define F367CAB_ERROR 0xf4ce0080
+#define F367CAB_EMERGENCY 0xf4ce0040
+#define F367CAB_CRE_TS 0xf4ce0030
+#define F367CAB_VER 0xf4ce000e
+#define F367CAB_M_LOCK 0xf4ce0001
+
+/* TS_STATUS_3 */
+#define R367CAB_TS_STATUS_3 0xf4cf
+#define F367CAB_UPDATE_READY 0xf4cf0080
+#define F367CAB_END_FRAME_HEADER 0xf4cf0040
+#define F367CAB_CONTCNT 0xf4cf0020
+#define F367CAB_TS_IDENTIFIER_SEL 0xf4cf000f
+
+/* T_O_ID_0 */
+#define R367CAB_T_O_ID_0 0xf4d0
+#define F367CAB_ON_ID_I_L 0xf4d000ff
+
+/* T_O_ID_1 */
+#define R367CAB_T_O_ID_1 0xf4d1
+#define F367CAB_ON_ID_I_H 0xf4d100ff
+
+/* T_O_ID_2 */
+#define R367CAB_T_O_ID_2 0xf4d2
+#define F367CAB_TS_ID_I_L 0xf4d200ff
+
+/* T_O_ID_3 */
+#define R367CAB_T_O_ID_3 0xf4d3
+#define F367CAB_TS_ID_I_H 0xf4d300ff
+
+#define STV0367CAB_NBREGS 187
+
+#endif
diff --git a/drivers/media/dvb/frontends/stv0900.h b/drivers/media/dvb/frontends/stv0900.h
index e3e35d1ce83..91c7ee8b231 100644
--- a/drivers/media/dvb/frontends/stv0900.h
+++ b/drivers/media/dvb/frontends/stv0900.h
@@ -53,6 +53,8 @@ struct stv0900_config {
u8 tun2_type;
/* Set device param to start dma */
int (*set_ts_params)(struct dvb_frontend *fe, int is_punctured);
+ /* Hook for Lock LED */
+ void (*set_lock_led)(struct dvb_frontend *fe, int offon);
};
#if defined(CONFIG_DVB_STV0900) || (defined(CONFIG_DVB_STV0900_MODULE) \
diff --git a/drivers/media/dvb/frontends/stv0900_core.c b/drivers/media/dvb/frontends/stv0900_core.c
index 4f5e7d3a0e6..0ca316d6fff 100644
--- a/drivers/media/dvb/frontends/stv0900_core.c
+++ b/drivers/media/dvb/frontends/stv0900_core.c
@@ -1604,6 +1604,9 @@ static enum dvbfe_search stv0900_search(struct dvb_frontend *fe,
p_search.standard = STV0900_AUTO_SEARCH;
p_search.iq_inversion = STV0900_IQ_AUTO;
p_search.search_algo = STV0900_BLIND_SEARCH;
+ /* Speeds up DVB-S searching */
+ if (c->delivery_system == SYS_DVBS)
+ p_search.standard = STV0900_SEARCH_DVBS1;
intp->srch_standard[demod] = p_search.standard;
intp->symbol_rate[demod] = p_search.symbol_rate;
@@ -1660,8 +1663,14 @@ static int stv0900_read_status(struct dvb_frontend *fe, enum fe_status *status)
| FE_HAS_VITERBI
| FE_HAS_SYNC
| FE_HAS_LOCK;
- } else
+ if (state->config->set_lock_led)
+ state->config->set_lock_led(fe, 1);
+ } else {
+ *status = 0;
+ if (state->config->set_lock_led)
+ state->config->set_lock_led(fe, 0);
dprintk("DEMOD LOCK FAIL\n");
+ }
return 0;
}
@@ -1831,6 +1840,9 @@ static void stv0900_release(struct dvb_frontend *fe)
dprintk("%s\n", __func__);
+ if (state->config->set_lock_led)
+ state->config->set_lock_led(fe, 0);
+
if ((--(state->internal->dmds_used)) <= 0) {
dprintk("%s: Actually removing\n", __func__);
@@ -1842,6 +1854,18 @@ static void stv0900_release(struct dvb_frontend *fe)
kfree(state);
}
+static int stv0900_sleep(struct dvb_frontend *fe)
+{
+ struct stv0900_state *state = fe->demodulator_priv;
+
+ dprintk("%s\n", __func__);
+
+ if (state->config->set_lock_led)
+ state->config->set_lock_led(fe, 0);
+
+ return 0;
+}
+
static int stv0900_get_frontend(struct dvb_frontend *fe,
struct dvb_frontend_parameters *p)
{
@@ -1876,6 +1900,7 @@ static struct dvb_frontend_ops stv0900_ops = {
.release = stv0900_release,
.init = stv0900_init,
.get_frontend = stv0900_get_frontend,
+ .sleep = stv0900_sleep,
.get_frontend_algo = stv0900_frontend_algo,
.i2c_gate_ctrl = stv0900_i2c_gate_ctrl,
.diseqc_send_master_cmd = stv0900_send_master_cmd,
diff --git a/drivers/media/dvb/frontends/stv0900_priv.h b/drivers/media/dvb/frontends/stv0900_priv.h
index b62b0f0a4fe..e0ea74c8e09 100644
--- a/drivers/media/dvb/frontends/stv0900_priv.h
+++ b/drivers/media/dvb/frontends/stv0900_priv.h
@@ -238,7 +238,7 @@ enum fe_stv0900_demod_mode {
};
struct stv0900_init_params{
- u32 dmd_ref_clk;/* Refrence,Input clock for the demod in Hz */
+ u32 dmd_ref_clk;/* Reference,Input clock for the demod in Hz */
/* Demodulator Type (single demod or dual demod) */
enum fe_stv0900_demod_mode demod_mode;
diff --git a/drivers/media/dvb/frontends/stv090x.c b/drivers/media/dvb/frontends/stv090x.c
index 4e0fc2c8a41..52d8712411e 100644
--- a/drivers/media/dvb/frontends/stv090x.c
+++ b/drivers/media/dvb/frontends/stv090x.c
@@ -767,8 +767,12 @@ static int stv090x_i2c_gate_ctrl(struct stv090x_state *state, int enable)
* In case of any error, the lock is unlocked and exit within the
* relevant operations themselves.
*/
- if (enable)
- mutex_lock(&state->internal->tuner_lock);
+ if (enable) {
+ if (state->config->tuner_i2c_lock)
+ state->config->tuner_i2c_lock(&state->frontend, 1);
+ else
+ mutex_lock(&state->internal->tuner_lock);
+ }
reg = STV090x_READ_DEMOD(state, I2CRPT);
if (enable) {
@@ -784,13 +788,20 @@ static int stv090x_i2c_gate_ctrl(struct stv090x_state *state, int enable)
goto err;
}
- if (!enable)
- mutex_unlock(&state->internal->tuner_lock);
+ if (!enable) {
+ if (state->config->tuner_i2c_lock)
+ state->config->tuner_i2c_lock(&state->frontend, 0);
+ else
+ mutex_unlock(&state->internal->tuner_lock);
+ }
return 0;
err:
dprintk(FE_ERROR, 1, "I/O error");
- mutex_unlock(&state->internal->tuner_lock);
+ if (state->config->tuner_i2c_lock)
+ state->config->tuner_i2c_lock(&state->frontend, 0);
+ else
+ mutex_unlock(&state->internal->tuner_lock);
return -1;
}
@@ -1413,7 +1424,7 @@ static int stv090x_start_search(struct stv090x_state *state)
if (STV090x_WRITE_DEMOD(state, CFRLOW0, 0x00) < 0)
goto err;
- /*enlarge the timing bandwith for Low SR*/
+ /*enlarge the timing bandwidth for Low SR*/
if (STV090x_WRITE_DEMOD(state, RTCS2, 0x68) < 0)
goto err;
} else {
@@ -1421,17 +1432,17 @@ static int stv090x_start_search(struct stv090x_state *state)
Set The carrier search up and low to auto mode */
if (STV090x_WRITE_DEMOD(state, CARCFG, 0xc4) < 0)
goto err;
- /*reduce the timing bandwith for high SR*/
+ /*reduce the timing bandwidth for high SR*/
if (STV090x_WRITE_DEMOD(state, RTCS2, 0x44) < 0)
goto err;
}
} else {
/* >= Cut 3 */
if (state->srate <= 5000000) {
- /* enlarge the timing bandwith for Low SR */
+ /* enlarge the timing bandwidth for Low SR */
STV090x_WRITE_DEMOD(state, RTCS2, 0x68);
} else {
- /* reduce timing bandwith for high SR */
+ /* reduce timing bandwidth for high SR */
STV090x_WRITE_DEMOD(state, RTCS2, 0x44);
}
@@ -2471,7 +2482,7 @@ static int stv090x_sw_algo(struct stv090x_state *state)
dvbs2_fly_wheel = STV090x_GETFIELD_Px(reg, FLYWHEEL_CPT_FIELD);
}
if (dvbs2_fly_wheel < 0xd) {
- /*FALSE lock, The demod is loosing lock */
+ /*FALSE lock, The demod is losing lock */
lock = 0;
if (trials < 2) {
if (state->internal->dev_ver >= 0x20) {
@@ -2883,10 +2894,12 @@ static int stv090x_optimize_track(struct stv090x_state *state)
STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1);
if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
goto err;
- if (STV090x_WRITE_DEMOD(state, ACLC, 0) < 0)
- goto err;
- if (STV090x_WRITE_DEMOD(state, BCLC, 0) < 0)
- goto err;
+ if (state->internal->dev_ver >= 0x30) {
+ if (STV090x_WRITE_DEMOD(state, ACLC, 0) < 0)
+ goto err;
+ if (STV090x_WRITE_DEMOD(state, BCLC, 0) < 0)
+ goto err;
+ }
if (state->frame_len == STV090x_LONG_FRAME) {
reg = STV090x_READ_DEMOD(state, DMDMODCOD);
modcod = STV090x_GETFIELD_Px(reg, DEMOD_MODCOD_FIELD);
@@ -3189,7 +3202,7 @@ static enum stv090x_signal_state stv090x_algo(struct stv090x_state *state)
goto err;
if (STV090x_WRITE_DEMOD(state, CORRELMANT, 0x70) < 0)
goto err;
- if (stv090x_set_srate(state, 1000000) < 0) /* inital srate = 1Msps */
+ if (stv090x_set_srate(state, 1000000) < 0) /* initial srate = 1Msps */
goto err;
} else {
/* known srate */
@@ -3846,6 +3859,7 @@ static int stv090x_sleep(struct dvb_frontend *fe)
{
struct stv090x_state *state = fe->demodulator_priv;
u32 reg;
+ u8 full_standby = 0;
if (stv090x_i2c_gate_ctrl(state, 1) < 0)
goto err;
@@ -3858,24 +3872,119 @@ static int stv090x_sleep(struct dvb_frontend *fe)
if (stv090x_i2c_gate_ctrl(state, 0) < 0)
goto err;
- dprintk(FE_DEBUG, 1, "Set %s to sleep",
- state->device == STV0900 ? "STV0900" : "STV0903");
+ dprintk(FE_DEBUG, 1, "Set %s(%d) to sleep",
+ state->device == STV0900 ? "STV0900" : "STV0903",
+ state->demod);
- reg = stv090x_read_reg(state, STV090x_SYNTCTRL);
- STV090x_SETFIELD(reg, STANDBY_FIELD, 0x01);
- if (stv090x_write_reg(state, STV090x_SYNTCTRL, reg) < 0)
- goto err;
+ mutex_lock(&state->internal->demod_lock);
- reg = stv090x_read_reg(state, STV090x_TSTTNR1);
- STV090x_SETFIELD(reg, ADC1_PON_FIELD, 0);
- if (stv090x_write_reg(state, STV090x_TSTTNR1, reg) < 0)
- goto err;
+ switch (state->demod) {
+ case STV090x_DEMODULATOR_0:
+ /* power off ADC 1 */
+ reg = stv090x_read_reg(state, STV090x_TSTTNR1);
+ STV090x_SETFIELD(reg, ADC1_PON_FIELD, 0);
+ if (stv090x_write_reg(state, STV090x_TSTTNR1, reg) < 0)
+ goto err;
+ /* power off DiSEqC 1 */
+ reg = stv090x_read_reg(state, STV090x_TSTTNR2);
+ STV090x_SETFIELD(reg, DISEQC1_PON_FIELD, 0);
+ if (stv090x_write_reg(state, STV090x_TSTTNR2, reg) < 0)
+ goto err;
+
+ /* check whether path 2 is already sleeping, that is when
+ ADC2 is off */
+ reg = stv090x_read_reg(state, STV090x_TSTTNR3);
+ if (STV090x_GETFIELD(reg, ADC2_PON_FIELD) == 0)
+ full_standby = 1;
+
+ /* stop clocks */
+ reg = stv090x_read_reg(state, STV090x_STOPCLK1);
+ /* packet delineator 1 clock */
+ STV090x_SETFIELD(reg, STOP_CLKPKDT1_FIELD, 1);
+ /* ADC 1 clock */
+ STV090x_SETFIELD(reg, STOP_CLKADCI1_FIELD, 1);
+ /* FEC clock is shared between the two paths, only stop it
+ when full standby is possible */
+ if (full_standby)
+ STV090x_SETFIELD(reg, STOP_CLKFEC_FIELD, 1);
+ if (stv090x_write_reg(state, STV090x_STOPCLK1, reg) < 0)
+ goto err;
+ reg = stv090x_read_reg(state, STV090x_STOPCLK2);
+ /* sampling 1 clock */
+ STV090x_SETFIELD(reg, STOP_CLKSAMP1_FIELD, 1);
+ /* viterbi 1 clock */
+ STV090x_SETFIELD(reg, STOP_CLKVIT1_FIELD, 1);
+ /* TS clock is shared between the two paths, only stop it
+ when full standby is possible */
+ if (full_standby)
+ STV090x_SETFIELD(reg, STOP_CLKTS_FIELD, 1);
+ if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0)
+ goto err;
+ break;
+
+ case STV090x_DEMODULATOR_1:
+ /* power off ADC 2 */
+ reg = stv090x_read_reg(state, STV090x_TSTTNR3);
+ STV090x_SETFIELD(reg, ADC2_PON_FIELD, 0);
+ if (stv090x_write_reg(state, STV090x_TSTTNR3, reg) < 0)
+ goto err;
+ /* power off DiSEqC 2 */
+ reg = stv090x_read_reg(state, STV090x_TSTTNR4);
+ STV090x_SETFIELD(reg, DISEQC2_PON_FIELD, 0);
+ if (stv090x_write_reg(state, STV090x_TSTTNR4, reg) < 0)
+ goto err;
+
+ /* check whether path 1 is already sleeping, that is when
+ ADC1 is off */
+ reg = stv090x_read_reg(state, STV090x_TSTTNR1);
+ if (STV090x_GETFIELD(reg, ADC1_PON_FIELD) == 0)
+ full_standby = 1;
+
+ /* stop clocks */
+ reg = stv090x_read_reg(state, STV090x_STOPCLK1);
+ /* packet delineator 2 clock */
+ STV090x_SETFIELD(reg, STOP_CLKPKDT2_FIELD, 1);
+ /* ADC 2 clock */
+ STV090x_SETFIELD(reg, STOP_CLKADCI2_FIELD, 1);
+ /* FEC clock is shared between the two paths, only stop it
+ when full standby is possible */
+ if (full_standby)
+ STV090x_SETFIELD(reg, STOP_CLKFEC_FIELD, 1);
+ if (stv090x_write_reg(state, STV090x_STOPCLK1, reg) < 0)
+ goto err;
+ reg = stv090x_read_reg(state, STV090x_STOPCLK2);
+ /* sampling 2 clock */
+ STV090x_SETFIELD(reg, STOP_CLKSAMP2_FIELD, 1);
+ /* viterbi 2 clock */
+ STV090x_SETFIELD(reg, STOP_CLKVIT2_FIELD, 1);
+ /* TS clock is shared between the two paths, only stop it
+ when full standby is possible */
+ if (full_standby)
+ STV090x_SETFIELD(reg, STOP_CLKTS_FIELD, 1);
+ if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0)
+ goto err;
+ break;
+ default:
+ dprintk(FE_ERROR, 1, "Wrong demodulator!");
+ break;
+ }
+
+ if (full_standby) {
+ /* general power off */
+ reg = stv090x_read_reg(state, STV090x_SYNTCTRL);
+ STV090x_SETFIELD(reg, STANDBY_FIELD, 0x01);
+ if (stv090x_write_reg(state, STV090x_SYNTCTRL, reg) < 0)
+ goto err;
+ }
+
+ mutex_unlock(&state->internal->demod_lock);
return 0;
err_gateoff:
stv090x_i2c_gate_ctrl(state, 0);
err:
+ mutex_unlock(&state->internal->demod_lock);
dprintk(FE_ERROR, 1, "I/O error");
return -1;
}
@@ -3885,21 +3994,94 @@ static int stv090x_wakeup(struct dvb_frontend *fe)
struct stv090x_state *state = fe->demodulator_priv;
u32 reg;
- dprintk(FE_DEBUG, 1, "Wake %s from standby",
- state->device == STV0900 ? "STV0900" : "STV0903");
+ dprintk(FE_DEBUG, 1, "Wake %s(%d) from standby",
+ state->device == STV0900 ? "STV0900" : "STV0903",
+ state->demod);
+
+ mutex_lock(&state->internal->demod_lock);
+ /* general power on */
reg = stv090x_read_reg(state, STV090x_SYNTCTRL);
STV090x_SETFIELD(reg, STANDBY_FIELD, 0x00);
if (stv090x_write_reg(state, STV090x_SYNTCTRL, reg) < 0)
goto err;
- reg = stv090x_read_reg(state, STV090x_TSTTNR1);
- STV090x_SETFIELD(reg, ADC1_PON_FIELD, 1);
- if (stv090x_write_reg(state, STV090x_TSTTNR1, reg) < 0)
- goto err;
+ switch (state->demod) {
+ case STV090x_DEMODULATOR_0:
+ /* power on ADC 1 */
+ reg = stv090x_read_reg(state, STV090x_TSTTNR1);
+ STV090x_SETFIELD(reg, ADC1_PON_FIELD, 1);
+ if (stv090x_write_reg(state, STV090x_TSTTNR1, reg) < 0)
+ goto err;
+ /* power on DiSEqC 1 */
+ reg = stv090x_read_reg(state, STV090x_TSTTNR2);
+ STV090x_SETFIELD(reg, DISEQC1_PON_FIELD, 1);
+ if (stv090x_write_reg(state, STV090x_TSTTNR2, reg) < 0)
+ goto err;
+
+ /* activate clocks */
+ reg = stv090x_read_reg(state, STV090x_STOPCLK1);
+ /* packet delineator 1 clock */
+ STV090x_SETFIELD(reg, STOP_CLKPKDT1_FIELD, 0);
+ /* ADC 1 clock */
+ STV090x_SETFIELD(reg, STOP_CLKADCI1_FIELD, 0);
+ /* FEC clock */
+ STV090x_SETFIELD(reg, STOP_CLKFEC_FIELD, 0);
+ if (stv090x_write_reg(state, STV090x_STOPCLK1, reg) < 0)
+ goto err;
+ reg = stv090x_read_reg(state, STV090x_STOPCLK2);
+ /* sampling 1 clock */
+ STV090x_SETFIELD(reg, STOP_CLKSAMP1_FIELD, 0);
+ /* viterbi 1 clock */
+ STV090x_SETFIELD(reg, STOP_CLKVIT1_FIELD, 0);
+ /* TS clock */
+ STV090x_SETFIELD(reg, STOP_CLKTS_FIELD, 0);
+ if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0)
+ goto err;
+ break;
+ case STV090x_DEMODULATOR_1:
+ /* power on ADC 2 */
+ reg = stv090x_read_reg(state, STV090x_TSTTNR3);
+ STV090x_SETFIELD(reg, ADC2_PON_FIELD, 1);
+ if (stv090x_write_reg(state, STV090x_TSTTNR3, reg) < 0)
+ goto err;
+ /* power on DiSEqC 2 */
+ reg = stv090x_read_reg(state, STV090x_TSTTNR4);
+ STV090x_SETFIELD(reg, DISEQC2_PON_FIELD, 1);
+ if (stv090x_write_reg(state, STV090x_TSTTNR4, reg) < 0)
+ goto err;
+
+ /* activate clocks */
+ reg = stv090x_read_reg(state, STV090x_STOPCLK1);
+ /* packet delineator 2 clock */
+ STV090x_SETFIELD(reg, STOP_CLKPKDT2_FIELD, 0);
+ /* ADC 2 clock */
+ STV090x_SETFIELD(reg, STOP_CLKADCI2_FIELD, 0);
+ /* FEC clock */
+ STV090x_SETFIELD(reg, STOP_CLKFEC_FIELD, 0);
+ if (stv090x_write_reg(state, STV090x_STOPCLK1, reg) < 0)
+ goto err;
+ reg = stv090x_read_reg(state, STV090x_STOPCLK2);
+ /* sampling 2 clock */
+ STV090x_SETFIELD(reg, STOP_CLKSAMP2_FIELD, 0);
+ /* viterbi 2 clock */
+ STV090x_SETFIELD(reg, STOP_CLKVIT2_FIELD, 0);
+ /* TS clock */
+ STV090x_SETFIELD(reg, STOP_CLKTS_FIELD, 0);
+ if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0)
+ goto err;
+ break;
+
+ default:
+ dprintk(FE_ERROR, 1, "Wrong demodulator!");
+ break;
+ }
+
+ mutex_unlock(&state->internal->demod_lock);
return 0;
err:
+ mutex_unlock(&state->internal->demod_lock);
dprintk(FE_ERROR, 1, "I/O error");
return -1;
}
@@ -4169,6 +4351,7 @@ static int stv090x_set_tspath(struct stv090x_state *state)
switch (state->config->ts1_mode) {
case STV090x_TSMODE_PARALLEL_PUNCTURED:
reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
+ STV090x_SETFIELD_Px(reg, TSFIFO_TEIUPDATE_FIELD, state->config->ts1_tei);
STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00);
STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00);
if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
@@ -4177,6 +4360,7 @@ static int stv090x_set_tspath(struct stv090x_state *state)
case STV090x_TSMODE_DVBCI:
reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
+ STV090x_SETFIELD_Px(reg, TSFIFO_TEIUPDATE_FIELD, state->config->ts1_tei);
STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00);
STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01);
if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
@@ -4185,6 +4369,7 @@ static int stv090x_set_tspath(struct stv090x_state *state)
case STV090x_TSMODE_SERIAL_PUNCTURED:
reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
+ STV090x_SETFIELD_Px(reg, TSFIFO_TEIUPDATE_FIELD, state->config->ts1_tei);
STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01);
STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00);
if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
@@ -4193,6 +4378,7 @@ static int stv090x_set_tspath(struct stv090x_state *state)
case STV090x_TSMODE_SERIAL_CONTINUOUS:
reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
+ STV090x_SETFIELD_Px(reg, TSFIFO_TEIUPDATE_FIELD, state->config->ts1_tei);
STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01);
STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01);
if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
@@ -4206,6 +4392,7 @@ static int stv090x_set_tspath(struct stv090x_state *state)
switch (state->config->ts2_mode) {
case STV090x_TSMODE_PARALLEL_PUNCTURED:
reg = stv090x_read_reg(state, STV090x_P2_TSCFGH);
+ STV090x_SETFIELD_Px(reg, TSFIFO_TEIUPDATE_FIELD, state->config->ts2_tei);
STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00);
STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00);
if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
@@ -4214,6 +4401,7 @@ static int stv090x_set_tspath(struct stv090x_state *state)
case STV090x_TSMODE_DVBCI:
reg = stv090x_read_reg(state, STV090x_P2_TSCFGH);
+ STV090x_SETFIELD_Px(reg, TSFIFO_TEIUPDATE_FIELD, state->config->ts2_tei);
STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00);
STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01);
if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
@@ -4222,6 +4410,7 @@ static int stv090x_set_tspath(struct stv090x_state *state)
case STV090x_TSMODE_SERIAL_PUNCTURED:
reg = stv090x_read_reg(state, STV090x_P2_TSCFGH);
+ STV090x_SETFIELD_Px(reg, TSFIFO_TEIUPDATE_FIELD, state->config->ts2_tei);
STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01);
STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00);
if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
@@ -4230,6 +4419,7 @@ static int stv090x_set_tspath(struct stv090x_state *state)
case STV090x_TSMODE_SERIAL_CONTINUOUS:
reg = stv090x_read_reg(state, STV090x_P2_TSCFGH);
+ STV090x_SETFIELD_Px(reg, TSFIFO_TEIUPDATE_FIELD, state->config->ts2_tei);
STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01);
STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01);
if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
@@ -4506,16 +4696,26 @@ static int stv090x_setup(struct dvb_frontend *fe)
if (stv090x_write_reg(state, STV090x_TSTRES0, 0x00) < 0)
goto err;
- /* workaround for stuck DiSEqC output */
- if (config->diseqc_envelope_mode)
- stv090x_send_diseqc_burst(fe, SEC_MINI_A);
-
return 0;
err:
dprintk(FE_ERROR, 1, "I/O error");
return -1;
}
+int stv090x_set_gpio(struct dvb_frontend *fe, u8 gpio, u8 dir, u8 value,
+ u8 xor_value)
+{
+ struct stv090x_state *state = fe->demodulator_priv;
+ u8 reg = 0;
+
+ STV090x_SETFIELD(reg, GPIOx_OPD_FIELD, dir);
+ STV090x_SETFIELD(reg, GPIOx_CONFIG_FIELD, value);
+ STV090x_SETFIELD(reg, GPIOx_XOR_FIELD, xor_value);
+
+ return stv090x_write_reg(state, STV090x_GPIOxCFG(gpio), reg);
+}
+EXPORT_SYMBOL(stv090x_set_gpio);
+
static struct dvb_frontend_ops stv090x_ops = {
.info = {
@@ -4580,39 +4780,35 @@ struct dvb_frontend *stv090x_attach(const struct stv090x_config *config,
state->internal = temp_int->internal;
state->internal->num_used++;
dprintk(FE_INFO, 1, "Found Internal Structure!");
- dprintk(FE_ERROR, 1, "Attaching %s demodulator(%d) Cut=0x%02x",
- state->device == STV0900 ? "STV0900" : "STV0903",
- demod,
- state->internal->dev_ver);
- return &state->frontend;
} else {
state->internal = kmalloc(sizeof(struct stv090x_internal),
GFP_KERNEL);
+ if (!state->internal)
+ goto error;
temp_int = append_internal(state->internal);
+ if (!temp_int) {
+ kfree(state->internal);
+ goto error;
+ }
state->internal->num_used = 1;
state->internal->mclk = 0;
state->internal->dev_ver = 0;
state->internal->i2c_adap = state->i2c;
state->internal->i2c_addr = state->config->address;
dprintk(FE_INFO, 1, "Create New Internal Structure!");
- }
- mutex_init(&state->internal->demod_lock);
- mutex_init(&state->internal->tuner_lock);
+ mutex_init(&state->internal->demod_lock);
+ mutex_init(&state->internal->tuner_lock);
- if (stv090x_sleep(&state->frontend) < 0) {
- dprintk(FE_ERROR, 1, "Error putting device to sleep");
- goto error;
+ if (stv090x_setup(&state->frontend) < 0) {
+ dprintk(FE_ERROR, 1, "Error setting up device");
+ goto err_remove;
+ }
}
- if (stv090x_setup(&state->frontend) < 0) {
- dprintk(FE_ERROR, 1, "Error setting up device");
- goto error;
- }
- if (stv090x_wakeup(&state->frontend) < 0) {
- dprintk(FE_ERROR, 1, "Error waking device");
- goto error;
- }
+ /* workaround for stuck DiSEqC output */
+ if (config->diseqc_envelope_mode)
+ stv090x_send_diseqc_burst(&state->frontend, SEC_MINI_A);
dprintk(FE_ERROR, 1, "Attaching %s demodulator(%d) Cut=0x%02x",
state->device == STV0900 ? "STV0900" : "STV0903",
@@ -4621,6 +4817,9 @@ struct dvb_frontend *stv090x_attach(const struct stv090x_config *config,
return &state->frontend;
+err_remove:
+ remove_dev(state->internal);
+ kfree(state->internal);
error:
kfree(state);
return NULL;
diff --git a/drivers/media/dvb/frontends/stv090x.h b/drivers/media/dvb/frontends/stv090x.h
index dd1b93ae4e9..29cdc2b7131 100644
--- a/drivers/media/dvb/frontends/stv090x.h
+++ b/drivers/media/dvb/frontends/stv090x.h
@@ -78,6 +78,9 @@ struct stv090x_config {
u32 ts1_clk;
u32 ts2_clk;
+ u8 ts1_tei : 1;
+ u8 ts2_tei : 1;
+
enum stv090x_i2crpt repeater_level;
u8 tuner_bbgain; /* default: 10db */
@@ -97,6 +100,7 @@ struct stv090x_config {
int (*tuner_get_bbgain) (struct dvb_frontend *fe, u32 *gain);
int (*tuner_set_refclk) (struct dvb_frontend *fe, u32 refclk);
int (*tuner_get_status) (struct dvb_frontend *fe, u32 *status);
+ void (*tuner_i2c_lock) (struct dvb_frontend *fe, int lock);
};
#if defined(CONFIG_DVB_STV090x) || (defined(CONFIG_DVB_STV090x_MODULE) && defined(MODULE))
@@ -104,6 +108,11 @@ struct stv090x_config {
extern struct dvb_frontend *stv090x_attach(const struct stv090x_config *config,
struct i2c_adapter *i2c,
enum stv090x_demodulator demod);
+
+/* dir = 0 -> output, dir = 1 -> input/open-drain */
+extern int stv090x_set_gpio(struct dvb_frontend *fe, u8 gpio,
+ u8 dir, u8 value, u8 xor_value);
+
#else
static inline struct dvb_frontend *stv090x_attach(const struct stv090x_config *config,
@@ -113,6 +122,13 @@ static inline struct dvb_frontend *stv090x_attach(const struct stv090x_config *c
printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
return NULL;
}
+
+static inline int stv090x_set_gpio(struct dvb_frontend *fe, u8 gpio,
+ u8 opd, u8 value, u8 xor_value)
+{
+ printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
+ return -ENODEV;
+}
#endif /* CONFIG_DVB_STV090x */
#endif /* __STV090x_H */
diff --git a/drivers/media/dvb/frontends/stv090x_reg.h b/drivers/media/dvb/frontends/stv090x_reg.h
index 2502855dd78..93741ee1429 100644
--- a/drivers/media/dvb/frontends/stv090x_reg.h
+++ b/drivers/media/dvb/frontends/stv090x_reg.h
@@ -1327,10 +1327,10 @@
#define STV090x_WIDTH_Px_NOSPLHT_UNNORMED_FIELD 8
#define STV090x_Px_NOSPLHy(__x, __y) (0xf48f - (__x - 1) * 0x200 - __y * 0x1)
-#define STv090x_P1_NOSPLH0 STV090x_Px_NOSPLHy(1, 0)
-#define STv090x_P1_NOSPLH1 STV090x_Px_NOSPLHy(1, 1)
-#define STv090x_P2_NOSPLH0 STV090x_Px_NOSPLHy(2, 0)
-#define STv090x_P2_NOSPLH1 STV090x_Px_NOSPLHy(2, 1)
+#define STV090x_P1_NOSPLH0 STV090x_Px_NOSPLHy(1, 0)
+#define STV090x_P1_NOSPLH1 STV090x_Px_NOSPLHy(1, 1)
+#define STV090x_P2_NOSPLH0 STV090x_Px_NOSPLHy(2, 0)
+#define STV090x_P2_NOSPLH1 STV090x_Px_NOSPLHy(2, 1)
#define STV090x_OFFST_Px_NOSPLH_UNNORMED_FIELD 0
#define STV090x_WIDTH_Px_NOSPLH_UNNORMED_FIELD 8
@@ -1406,7 +1406,7 @@
#define STV090x_Px_BCLC2S28(__x) (0xf49d - (__x - 1) * 0x200)
#define STV090x_P1_BCLC2S28 STV090x_Px_BCLC2S28(1)
-#define STV090x_P2_BCLC2S28 STV090x_Px_BCLC2S28(1)
+#define STV090x_P2_BCLC2S28 STV090x_Px_BCLC2S28(2)
#define STV090x_OFFST_Px_CAR2S2_8_BETA_M_FIELD 4
#define STV090x_WIDTH_Px_CAR2S2_8_BETA_M_FIELD 2
#define STV090x_OFFST_Px_CAR2S2_8_BETA_E_FIELD 0
@@ -1414,7 +1414,7 @@
#define STV090x_Px_BCLC2S216A(__x) (0xf49e - (__x - 1) * 0x200)
#define STV090x_P1_BCLC2S216A STV090x_Px_BCLC2S216A(1)
-#define STV090x_P2_BCLC2S216A STV090x_Px_BCLC2S216A(1)
+#define STV090x_P2_BCLC2S216A STV090x_Px_BCLC2S216A(2)
#define STV090x_OFFST_Px_CAR2S2_16A_BETA_M_FIELD 4
#define STV090x_WIDTH_Px_CAR2S2_16A_BETA_M_FIELD 2
#define STV090x_OFFST_Px_CAR2S2_16A_BETA_E_FIELD 0
@@ -1422,7 +1422,7 @@
#define STV090x_Px_BCLC2S232A(__x) (0xf49f - (__x - 1) * 0x200)
#define STV090x_P1_BCLC2S232A STV090x_Px_BCLC2S232A(1)
-#define STV090x_P2_BCLC2S232A STV090x_Px_BCLC2S232A(1)
+#define STV090x_P2_BCLC2S232A STV090x_Px_BCLC2S232A(2)
#define STV090x_OFFST_Px_CAR2S2_32A_BETA_M_FIELD 4
#define STV090x_WIDTH_Px_CAR2S2_32A_BETA_M_FIELD 2
#define STV090x_OFFST_Px_CAR2S2_32A_BETA_E_FIELD 0
@@ -1602,7 +1602,7 @@
#define STV090x_Px_CCIACC(__x) (0xf4c4 - (__x - 1) * 0x200)
#define STV090x_P1_CCIACC STV090x_Px_CCIACC(1)
-#define STV090x_P2_CCIACC STV090x_Px_CCIACC(1)
+#define STV090x_P2_CCIACC STV090x_Px_CCIACC(2)
#define STV090x_OFFST_Px_CCI_VALUE_FIELD 0
#define STV090x_WIDTH_Px_CCI_VALUE_FIELD 8
diff --git a/drivers/media/dvb/frontends/zl10036.c b/drivers/media/dvb/frontends/zl10036.c
index 4627f491656..81aa984c551 100644
--- a/drivers/media/dvb/frontends/zl10036.c
+++ b/drivers/media/dvb/frontends/zl10036.c
@@ -463,16 +463,16 @@ struct dvb_frontend *zl10036_attach(struct dvb_frontend *fe,
const struct zl10036_config *config,
struct i2c_adapter *i2c)
{
- struct zl10036_state *state = NULL;
+ struct zl10036_state *state;
int ret;
- if (NULL == config) {
+ if (!config) {
printk(KERN_ERR "%s: no config specified", __func__);
- goto error;
+ return NULL;
}
state = kzalloc(sizeof(struct zl10036_state), GFP_KERNEL);
- if (NULL == state)
+ if (!state)
return NULL;
state->config = config;
@@ -507,7 +507,7 @@ struct dvb_frontend *zl10036_attach(struct dvb_frontend *fe,
return fe;
error:
- zl10036_release(fe);
+ kfree(state);
return NULL;
}
EXPORT_SYMBOL(zl10036_attach);