diff options
Diffstat (limited to 'drivers/net/wireless/ath/ath9k/ar9003_phy.h')
| -rw-r--r-- | drivers/net/wireless/ath/ath9k/ar9003_phy.h | 52 |
1 files changed, 36 insertions, 16 deletions
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_phy.h b/drivers/net/wireless/ath/ath9k/ar9003_phy.h index 6cea546a150..2f4023e6608 100644 --- a/drivers/net/wireless/ath/ath9k/ar9003_phy.h +++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.h @@ -325,10 +325,10 @@ #define AR_PHY_RX_OCGAIN (AR_AGC_BASE + 0x200) -#define AR_PHY_CCA_NOM_VAL_9300_2GHZ -110 -#define AR_PHY_CCA_NOM_VAL_9300_5GHZ -115 -#define AR_PHY_CCA_MIN_GOOD_VAL_9300_2GHZ -125 -#define AR_PHY_CCA_MIN_GOOD_VAL_9300_5GHZ -125 +#define AR_PHY_CCA_NOM_VAL_9300_2GHZ (AR_SREV_9462(ah) ? -127 : -110) +#define AR_PHY_CCA_NOM_VAL_9300_5GHZ (AR_SREV_9462(ah) ? -127 : -115) +#define AR_PHY_CCA_MIN_GOOD_VAL_9300_2GHZ (AR_SREV_9462(ah) ? -127 : -125) +#define AR_PHY_CCA_MIN_GOOD_VAL_9300_5GHZ (AR_SREV_9462(ah) ? -127 : -125) #define AR_PHY_CCA_MAX_GOOD_VAL_9300_2GHZ -95 #define AR_PHY_CCA_MAX_GOOD_VAL_9300_5GHZ -100 @@ -572,6 +572,8 @@ #define AR_PHY_TXGAIN_TABLE (AR_SM_BASE + 0x300) +#define AR_PHY_TX_IQCAL_CONTROL_0 (AR_SM_BASE + AR_SREV_9485(ah) ? \ + 0x3c4 : 0x444) #define AR_PHY_TX_IQCAL_CONTROL_1 (AR_SM_BASE + AR_SREV_9485(ah) ? \ 0x3c8 : 0x448) #define AR_PHY_TX_IQCAL_START (AR_SM_BASE + AR_SREV_9485(ah) ? \ @@ -582,8 +584,6 @@ (AR_SREV_9485(ah) ? \ 0x3d0 : 0x450) + ((_i) << 2)) #define AR_PHY_RTT_CTRL (AR_SM_BASE + 0x380) -#define AR_PHY_RTT_TABLE_SW_INTF_B (AR_SM_BASE + 0x384) -#define AR_PHY_RTT_TABLE_SW_INTF_1_B0 (AR_SM_BASE + 0x388) #define AR_PHY_WATCHDOG_STATUS (AR_SM_BASE + 0x5c0) #define AR_PHY_WATCHDOG_CTL_1 (AR_SM_BASE + 0x5c4) @@ -608,9 +608,9 @@ #define AR_PHY_AIC_CTRL_1_B0 (AR_SM_BASE + 0x4b4) #define AR_PHY_AIC_CTRL_2_B0 (AR_SM_BASE + 0x4b8) #define AR_PHY_AIC_CTRL_3_B0 (AR_SM_BASE + 0x4bc) -#define AR_PHY_AIC_STAT_0_B0 (AR_SM_BASE + (AR_SREV_9480_10(ah) ? \ +#define AR_PHY_AIC_STAT_0_B0 (AR_SM_BASE + (AR_SREV_9462_10(ah) ? \ 0x4c0 : 0x4c4)) -#define AR_PHY_AIC_STAT_1_B0 (AR_SM_BASE + (AR_SREV_9480_10(ah) ? \ +#define AR_PHY_AIC_STAT_1_B0 (AR_SM_BASE + (AR_SREV_9462_10(ah) ? \ 0x4c4 : 0x4c8)) #define AR_PHY_AIC_CTRL_4_B0 (AR_SM_BASE + 0x4c0) #define AR_PHY_AIC_STAT_2_B0 (AR_SM_BASE + 0x4cc) @@ -625,7 +625,7 @@ #define AR_PHY_65NM_CH0_RXTX4 0x1610c #define AR_CH0_TOP (AR_SREV_9300(ah) ? 0x16288 : \ - ((AR_SREV_9480(ah) ? 0x1628c : 0x16280))) + ((AR_SREV_9462(ah) ? 0x1628c : 0x16280))) #define AR_CH0_TOP_XPABIASLVL (0x300) #define AR_CH0_TOP_XPABIASLVL_S (8) @@ -638,8 +638,8 @@ #define AR_SWITCH_TABLE_COM_ALL (0xffff) #define AR_SWITCH_TABLE_COM_ALL_S (0) -#define AR_SWITCH_TABLE_COM_AR9480_ALL (0xffffff) -#define AR_SWITCH_TABLE_COM_AR9480_ALL_S (0) +#define AR_SWITCH_TABLE_COM_AR9462_ALL (0xffffff) +#define AR_SWITCH_TABLE_COM_AR9462_ALL_S (0) #define AR_SWITCH_TABLE_COM_SPDT (0x00f00000) #define AR_SWITCH_TABLE_COM_SPDT_ALL (0x0000fff0) #define AR_SWITCH_TABLE_COM_SPDT_ALL_S (4) @@ -679,11 +679,11 @@ #define AR_CH0_XTAL_CAPOUTDAC 0x00fe0000 #define AR_CH0_XTAL_CAPOUTDAC_S 17 -#define AR_PHY_PMU1 (AR_SREV_9480(ah) ? 0x16340 : 0x16c40) +#define AR_PHY_PMU1 (AR_SREV_9462(ah) ? 0x16340 : 0x16c40) #define AR_PHY_PMU1_PWD 0x1 #define AR_PHY_PMU1_PWD_S 0 -#define AR_PHY_PMU2 (AR_SREV_9480(ah) ? 0x16344 : 0x16c44) +#define AR_PHY_PMU2 (AR_SREV_9462(ah) ? 0x16344 : 0x16c44) #define AR_PHY_PMU2_PGM 0x00200000 #define AR_PHY_PMU2_PGM_S 21 @@ -823,6 +823,22 @@ #define AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT 0x01000000 #define AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT_S 24 #define AR_PHY_CHANNEL_STATUS_RX_CLEAR 0x00000004 +#define AR_PHY_RTT_CTRL_ENA_RADIO_RETENTION 0x00000001 +#define AR_PHY_RTT_CTRL_ENA_RADIO_RETENTION_S 0 +#define AR_PHY_RTT_CTRL_RESTORE_MASK 0x0000007E +#define AR_PHY_RTT_CTRL_RESTORE_MASK_S 1 +#define AR_PHY_RTT_CTRL_FORCE_RADIO_RESTORE 0x00000080 +#define AR_PHY_RTT_CTRL_FORCE_RADIO_RESTORE_S 7 +#define AR_PHY_RTT_SW_RTT_TABLE_ACCESS 0x00000001 +#define AR_PHY_RTT_SW_RTT_TABLE_ACCESS_S 0 +#define AR_PHY_RTT_SW_RTT_TABLE_WRITE 0x00000002 +#define AR_PHY_RTT_SW_RTT_TABLE_WRITE_S 1 +#define AR_PHY_RTT_SW_RTT_TABLE_ADDR 0x0000001C +#define AR_PHY_RTT_SW_RTT_TABLE_ADDR_S 2 +#define AR_PHY_RTT_SW_RTT_TABLE_DATA 0xFFFFFFF0 +#define AR_PHY_RTT_SW_RTT_TABLE_DATA_S 4 +#define AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL 0x80000000 +#define AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL_S 31 #define AR_PHY_TX_IQCAL_CONTROL_1_IQCORR_I_Q_COFF_DELPT 0x01fc0000 #define AR_PHY_TX_IQCAL_CONTROL_1_IQCORR_I_Q_COFF_DELPT_S 18 #define AR_PHY_TX_IQCAL_START_DO_CAL 0x00000001 @@ -905,9 +921,9 @@ #define AR_PHY_AIC_CTRL_0_B1 (AR_SM1_BASE + 0x4b0) #define AR_PHY_AIC_CTRL_1_B1 (AR_SM1_BASE + 0x4b4) #define AR_PHY_AIC_CTRL_2_B1 (AR_SM1_BASE + 0x4b8) -#define AR_PHY_AIC_STAT_0_B1 (AR_SM1_BASE + (AR_SREV_9480_10(ah) ? \ +#define AR_PHY_AIC_STAT_0_B1 (AR_SM1_BASE + (AR_SREV_9462_10(ah) ? \ 0x4c0 : 0x4c4)) -#define AR_PHY_AIC_STAT_1_B1 (AR_SM1_BASE + (AR_SREV_9480_10(ah) ? \ +#define AR_PHY_AIC_STAT_1_B1 (AR_SM1_BASE + (AR_SREV_9462_10(ah) ? \ 0x4c4 : 0x4c8)) #define AR_PHY_AIC_CTRL_4_B1 (AR_SM1_BASE + 0x4c0) #define AR_PHY_AIC_STAT_2_B1 (AR_SM1_BASE + 0x4cc) @@ -915,6 +931,10 @@ #define AR_PHY_AIC_SRAM_ADDR_B1 (AR_SM1_BASE + 0x5f0) #define AR_PHY_AIC_SRAM_DATA_B1 (AR_SM1_BASE + 0x5f4) +#define AR_PHY_RTT_TABLE_SW_INTF_B(i) (0x384 + (i) ? \ + AR_SM1_BASE : AR_SM_BASE) +#define AR_PHY_RTT_TABLE_SW_INTF_1_B(i) (0x388 + (i) ? \ + AR_SM1_BASE : AR_SM_BASE) /* * Channel 2 Register Map */ @@ -981,7 +1001,7 @@ #define AR_GLB_BASE 0x20000 #define AR_PHY_GLB_CONTROL (AR_GLB_BASE + 0x44) #define AR_GLB_SCRATCH(_ah) (AR_GLB_BASE + \ - (AR_SREV_9480_20(_ah) ? 0x4c : 0x50)) + (AR_SREV_9462_20(_ah) ? 0x4c : 0x50)) #define AR_GLB_STATUS (AR_GLB_BASE + 0x48) /* |