summaryrefslogtreecommitdiffstats
path: root/include/asm-arm
diff options
context:
space:
mode:
Diffstat (limited to 'include/asm-arm')
-rw-r--r--include/asm-arm/arch-pxa/colibri.h19
-rw-r--r--include/asm-arm/arch-pxa/corgi.h1
-rw-r--r--include/asm-arm/arch-pxa/irqs.h10
-rw-r--r--include/asm-arm/arch-pxa/littleton.h6
-rw-r--r--include/asm-arm/arch-pxa/magician.h111
-rw-r--r--include/asm-arm/arch-pxa/mfp-pxa300.h1
-rw-r--r--include/asm-arm/arch-pxa/mfp-pxa320.h1
-rw-r--r--include/asm-arm/arch-pxa/mfp-pxa3xx.h252
-rw-r--r--include/asm-arm/arch-pxa/mfp.h409
-rw-r--r--include/asm-arm/arch-pxa/mmc.h2
-rw-r--r--include/asm-arm/arch-pxa/pcm027.h75
-rw-r--r--include/asm-arm/arch-pxa/pcm990_baseboard.h275
-rw-r--r--include/asm-arm/arch-pxa/pxa-regs.h370
-rw-r--r--include/asm-arm/arch-pxa/pxa2xx-regs.h84
-rw-r--r--include/asm-arm/arch-pxa/pxa2xx_spi.h24
-rw-r--r--include/asm-arm/arch-pxa/pxa3xx-regs.h86
-rw-r--r--include/asm-arm/arch-pxa/regs-ssp.h112
-rw-r--r--include/asm-arm/arch-pxa/sharpsl.h2
-rw-r--r--include/asm-arm/arch-pxa/spitz.h2
-rw-r--r--include/asm-arm/arch-pxa/ssp.h36
-rw-r--r--include/asm-arm/arch-pxa/uncompress.h14
-rw-r--r--include/asm-arm/arch-pxa/zylonite.h9
22 files changed, 1224 insertions, 677 deletions
diff --git a/include/asm-arm/arch-pxa/colibri.h b/include/asm-arm/arch-pxa/colibri.h
new file mode 100644
index 00000000000..2ae373fb567
--- /dev/null
+++ b/include/asm-arm/arch-pxa/colibri.h
@@ -0,0 +1,19 @@
+#ifndef _COLIBRI_H_
+#define _COLIBRI_H_
+
+/* physical memory regions */
+#define COLIBRI_FLASH_PHYS (PXA_CS0_PHYS) /* Flash region */
+#define COLIBRI_ETH_PHYS (PXA_CS2_PHYS) /* Ethernet DM9000 region */
+#define COLIBRI_SDRAM_BASE 0xa0000000 /* SDRAM region */
+
+/* virtual memory regions */
+#define COLIBRI_DISK_VIRT 0xF0000000 /* Disk On Chip region */
+
+/* size of flash */
+#define COLIBRI_FLASH_SIZE 0x02000000 /* Flash size 32 MB */
+
+/* Ethernet Controller Davicom DM9000 */
+#define GPIO_DM9000 114
+#define COLIBRI_ETH_IRQ IRQ_GPIO(GPIO_DM9000)
+
+#endif /* _COLIBRI_H_ */
diff --git a/include/asm-arm/arch-pxa/corgi.h b/include/asm-arm/arch-pxa/corgi.h
index e554caa0d18..bf856503baf 100644
--- a/include/asm-arm/arch-pxa/corgi.h
+++ b/include/asm-arm/arch-pxa/corgi.h
@@ -104,7 +104,6 @@
*/
extern struct platform_device corgiscoop_device;
extern struct platform_device corgissp_device;
-extern struct platform_device corgifb_device;
#endif /* __ASM_ARCH_CORGI_H */
diff --git a/include/asm-arm/arch-pxa/irqs.h b/include/asm-arm/arch-pxa/irqs.h
index b76ee6d1f5b..c562b972a4a 100644
--- a/include/asm-arm/arch-pxa/irqs.h
+++ b/include/asm-arm/arch-pxa/irqs.h
@@ -180,7 +180,8 @@
#define NR_IRQS (IRQ_LOCOMO_SPI_TEND + 1)
#elif defined(CONFIG_ARCH_LUBBOCK) || \
defined(CONFIG_MACH_LOGICPD_PXA270) || \
- defined(CONFIG_MACH_MAINSTONE)
+ defined(CONFIG_MACH_MAINSTONE) || \
+ defined(CONFIG_MACH_PCM027)
#define NR_IRQS (IRQ_BOARD_END)
#else
#define NR_IRQS (IRQ_BOARD_START)
@@ -227,6 +228,13 @@
#define IRQ_LOCOMO_LT_BASE (IRQ_BOARD_START + 2)
#define IRQ_LOCOMO_SPI_BASE (IRQ_BOARD_START + 3)
+/* phyCORE-PXA270 (PCM027) Interrupts */
+#define PCM027_IRQ(x) (IRQ_BOARD_START + (x))
+#define PCM027_BTDET_IRQ PCM027_IRQ(0)
+#define PCM027_FF_RI_IRQ PCM027_IRQ(1)
+#define PCM027_MMCDET_IRQ PCM027_IRQ(2)
+#define PCM027_PM_5V_IRQ PCM027_IRQ(3)
+
/* ITE8152 irqs */
/* add IT8152 IRQs beyond BOARD_END */
#ifdef CONFIG_PCI_HOST_ITE8152
diff --git a/include/asm-arm/arch-pxa/littleton.h b/include/asm-arm/arch-pxa/littleton.h
new file mode 100644
index 00000000000..79d209b826f
--- /dev/null
+++ b/include/asm-arm/arch-pxa/littleton.h
@@ -0,0 +1,6 @@
+#ifndef __ASM_ARCH_ZYLONITE_H
+#define __ASM_ARCH_ZYLONITE_H
+
+#define LITTLETON_ETH_PHYS 0x30000000
+
+#endif /* __ASM_ARCH_ZYLONITE_H */
diff --git a/include/asm-arm/arch-pxa/magician.h b/include/asm-arm/arch-pxa/magician.h
new file mode 100644
index 00000000000..337f51f06b3
--- /dev/null
+++ b/include/asm-arm/arch-pxa/magician.h
@@ -0,0 +1,111 @@
+/*
+ * GPIO and IRQ definitions for HTC Magician PDA phones
+ *
+ * Copyright (c) 2007 Philipp Zabel
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef _MAGICIAN_H_
+#define _MAGICIAN_H_
+
+#include <asm/arch/pxa-regs.h>
+
+/*
+ * PXA GPIOs
+ */
+
+#define GPIO0_MAGICIAN_KEY_POWER 0
+#define GPIO9_MAGICIAN_UNKNOWN 9
+#define GPIO10_MAGICIAN_GSM_IRQ 10
+#define GPIO11_MAGICIAN_GSM_OUT1 11
+#define GPIO13_MAGICIAN_CPLD_IRQ 13
+#define GPIO18_MAGICIAN_UNKNOWN 18
+#define GPIO22_MAGICIAN_VIBRA_EN 22
+#define GPIO26_MAGICIAN_GSM_POWER 26
+#define GPIO27_MAGICIAN_USBC_PUEN 27
+#define GPIO30_MAGICIAN_nCHARGE_EN 30
+#define GPIO37_MAGICIAN_KEY_HANGUP 37
+#define GPIO38_MAGICIAN_KEY_CONTACTS 38
+#define GPIO40_MAGICIAN_GSM_OUT2 40
+#define GPIO48_MAGICIAN_UNKNOWN 48
+#define GPIO56_MAGICIAN_UNKNOWN 56
+#define GPIO57_MAGICIAN_CAM_RESET 57
+#define GPIO83_MAGICIAN_nIR_EN 83
+#define GPIO86_MAGICIAN_GSM_RESET 86
+#define GPIO87_MAGICIAN_GSM_SELECT 87
+#define GPIO90_MAGICIAN_KEY_CALENDAR 90
+#define GPIO91_MAGICIAN_KEY_CAMERA 91
+#define GPIO93_MAGICIAN_KEY_UP 93
+#define GPIO94_MAGICIAN_KEY_DOWN 94
+#define GPIO95_MAGICIAN_KEY_LEFT 95
+#define GPIO96_MAGICIAN_KEY_RIGHT 96
+#define GPIO97_MAGICIAN_KEY_ENTER 97
+#define GPIO98_MAGICIAN_KEY_RECORD 98
+#define GPIO99_MAGICIAN_HEADPHONE_IN 99
+#define GPIO100_MAGICIAN_KEY_VOL_UP 100
+#define GPIO101_MAGICIAN_KEY_VOL_DOWN 101
+#define GPIO102_MAGICIAN_KEY_PHONE 102
+#define GPIO103_MAGICIAN_LED_KP 103
+#define GPIO104_MAGICIAN_LCD_POWER_1 104
+#define GPIO105_MAGICIAN_LCD_POWER_2 105
+#define GPIO106_MAGICIAN_LCD_POWER_3 106
+#define GPIO107_MAGICIAN_DS1WM_IRQ 107
+#define GPIO108_MAGICIAN_GSM_READY 108
+#define GPIO114_MAGICIAN_UNKNOWN 114
+#define GPIO115_MAGICIAN_nPEN_IRQ 115
+#define GPIO116_MAGICIAN_nCAM_EN 116
+#define GPIO119_MAGICIAN_UNKNOWN 119
+#define GPIO120_MAGICIAN_UNKNOWN 120
+
+/*
+ * PXA GPIO alternate function mode & direction
+ */
+
+#define GPIO0_MAGICIAN_KEY_POWER_MD (0 | GPIO_IN)
+#define GPIO9_MAGICIAN_UNKNOWN_MD (9 | GPIO_IN)
+#define GPIO10_MAGICIAN_GSM_IRQ_MD (10 | GPIO_IN)
+#define GPIO11_MAGICIAN_GSM_OUT1_MD (11 | GPIO_OUT)
+#define GPIO13_MAGICIAN_CPLD_IRQ_MD (13 | GPIO_IN)
+#define GPIO18_MAGICIAN_UNKNOWN_MD (18 | GPIO_OUT)
+#define GPIO22_MAGICIAN_VIBRA_EN_MD (22 | GPIO_OUT)
+#define GPIO26_MAGICIAN_GSM_POWER_MD (26 | GPIO_OUT)
+#define GPIO27_MAGICIAN_USBC_PUEN_MD (27 | GPIO_OUT)
+#define GPIO30_MAGICIAN_nCHARGE_EN_MD (30 | GPIO_OUT)
+#define GPIO37_MAGICIAN_KEY_HANGUP_MD (37 | GPIO_OUT)
+#define GPIO38_MAGICIAN_KEY_CONTACTS_MD (38 | GPIO_OUT)
+#define GPIO40_MAGICIAN_GSM_OUT2_MD (40 | GPIO_OUT)
+#define GPIO48_MAGICIAN_UNKNOWN_MD (48 | GPIO_OUT)
+#define GPIO56_MAGICIAN_UNKNOWN_MD (56 | GPIO_OUT)
+#define GPIO57_MAGICIAN_CAM_RESET_MD (57 | GPIO_OUT)
+#define GPIO83_MAGICIAN_nIR_EN_MD (83 | GPIO_OUT)
+#define GPIO86_MAGICIAN_GSM_RESET_MD (86 | GPIO_OUT)
+#define GPIO87_MAGICIAN_GSM_SELECT_MD (87 | GPIO_OUT)
+#define GPIO90_MAGICIAN_KEY_CALENDAR_MD (90 | GPIO_OUT)
+#define GPIO91_MAGICIAN_KEY_CAMERA_MD (91 | GPIO_OUT)
+#define GPIO93_MAGICIAN_KEY_UP_MD (93 | GPIO_IN)
+#define GPIO94_MAGICIAN_KEY_DOWN_MD (94 | GPIO_IN)
+#define GPIO95_MAGICIAN_KEY_LEFT_MD (95 | GPIO_IN)
+#define GPIO96_MAGICIAN_KEY_RIGHT_MD (96 | GPIO_IN)
+#define GPIO97_MAGICIAN_KEY_ENTER_MD (97 | GPIO_IN)
+#define GPIO98_MAGICIAN_KEY_RECORD_MD (98 | GPIO_IN)
+#define GPIO99_MAGICIAN_HEADPHONE_IN_MD (99 | GPIO_IN)
+#define GPIO100_MAGICIAN_KEY_VOL_UP_MD (100 | GPIO_IN)
+#define GPIO101_MAGICIAN_KEY_VOL_DOWN_MD (101 | GPIO_IN)
+#define GPIO102_MAGICIAN_KEY_PHONE_MD (102 | GPIO_IN)
+#define GPIO103_MAGICIAN_LED_KP_MD (103 | GPIO_OUT)
+#define GPIO104_MAGICIAN_LCD_POWER_1_MD (104 | GPIO_OUT)
+#define GPIO105_MAGICIAN_LCD_POWER_2_MD (105 | GPIO_OUT)
+#define GPIO106_MAGICIAN_LCD_POWER_3_MD (106 | GPIO_OUT)
+#define GPIO107_MAGICIAN_DS1WM_IRQ_MD (107 | GPIO_IN)
+#define GPIO108_MAGICIAN_GSM_READY_MD (108 | GPIO_IN)
+#define GPIO114_MAGICIAN_UNKNOWN_MD (114 | GPIO_OUT)
+#define GPIO115_MAGICIAN_nPEN_IRQ_MD (115 | GPIO_IN)
+#define GPIO116_MAGICIAN_nCAM_EN_MD (116 | GPIO_OUT)
+#define GPIO119_MAGICIAN_UNKNOWN_MD (119 | GPIO_OUT)
+#define GPIO120_MAGICIAN_UNKNOWN_MD (120 | GPIO_OUT)
+
+#endif /* _MAGICIAN_H_ */
diff --git a/include/asm-arm/arch-pxa/mfp-pxa300.h b/include/asm-arm/arch-pxa/mfp-pxa300.h
index a2099664988..bb410313556 100644
--- a/include/asm-arm/arch-pxa/mfp-pxa300.h
+++ b/include/asm-arm/arch-pxa/mfp-pxa300.h
@@ -16,6 +16,7 @@
#define __ASM_ARCH_MFP_PXA300_H
#include <asm/arch/mfp.h>
+#include <asm/arch/mfp-pxa3xx.h>
/* GPIO */
#define GPIO46_GPIO MFP_CFG(GPIO46, AF1)
diff --git a/include/asm-arm/arch-pxa/mfp-pxa320.h b/include/asm-arm/arch-pxa/mfp-pxa320.h
index 52deedcaf3b..576aa46d90f 100644
--- a/include/asm-arm/arch-pxa/mfp-pxa320.h
+++ b/include/asm-arm/arch-pxa/mfp-pxa320.h
@@ -16,6 +16,7 @@
#define __ASM_ARCH_MFP_PXA320_H
#include <asm/arch/mfp.h>
+#include <asm/arch/mfp-pxa3xx.h>
/* GPIO */
#define GPIO46_GPIO MFP_CFG(GPIO46, AF0)
diff --git a/include/asm-arm/arch-pxa/mfp-pxa3xx.h b/include/asm-arm/arch-pxa/mfp-pxa3xx.h
new file mode 100644
index 00000000000..1f6b35c015d
--- /dev/null
+++ b/include/asm-arm/arch-pxa/mfp-pxa3xx.h
@@ -0,0 +1,252 @@
+#ifndef __ASM_ARCH_MFP_PXA3XX_H
+#define __ASM_ARCH_MFP_PXA3XX_H
+
+#define MFPR_BASE (0x40e10000)
+#define MFPR_SIZE (PAGE_SIZE)
+
+/* MFPR register bit definitions */
+#define MFPR_PULL_SEL (0x1 << 15)
+#define MFPR_PULLUP_EN (0x1 << 14)
+#define MFPR_PULLDOWN_EN (0x1 << 13)
+#define MFPR_SLEEP_SEL (0x1 << 9)
+#define MFPR_SLEEP_OE_N (0x1 << 7)
+#define MFPR_EDGE_CLEAR (0x1 << 6)
+#define MFPR_EDGE_FALL_EN (0x1 << 5)
+#define MFPR_EDGE_RISE_EN (0x1 << 4)
+
+#define MFPR_SLEEP_DATA(x) ((x) << 8)
+#define MFPR_DRIVE(x) (((x) & 0x7) << 10)
+#define MFPR_AF_SEL(x) (((x) & 0x7) << 0)
+
+#define MFPR_EDGE_NONE (0)
+#define MFPR_EDGE_RISE (MFPR_EDGE_RISE_EN)
+#define MFPR_EDGE_FALL (MFPR_EDGE_FALL_EN)
+#define MFPR_EDGE_BOTH (MFPR_EDGE_RISE | MFPR_EDGE_FALL)
+
+/*
+ * Table that determines the low power modes outputs, with actual settings
+ * used in parentheses for don't-care values. Except for the float output,
+ * the configured driven and pulled levels match, so if there is a need for
+ * non-LPM pulled output, the same configuration could probably be used.
+ *
+ * Output value sleep_oe_n sleep_data pullup_en pulldown_en pull_sel
+ * (bit 7) (bit 8) (bit 14) (bit 13) (bit 15)
+ *
+ * Input 0 X(0) X(0) X(0) 0
+ * Drive 0 0 0 0 X(1) 0
+ * Drive 1 0 1 X(1) 0 0
+ * Pull hi (1) 1 X(1) 1 0 0
+ * Pull lo (0) 1 X(0) 0 1 0
+ * Z (float) 1 X(0) 0 0 0
+ */
+#define MFPR_LPM_INPUT (0)
+#define MFPR_LPM_DRIVE_LOW (MFPR_SLEEP_DATA(0) | MFPR_PULLDOWN_EN)
+#define MFPR_LPM_DRIVE_HIGH (MFPR_SLEEP_DATA(1) | MFPR_PULLUP_EN)
+#define MFPR_LPM_PULL_LOW (MFPR_LPM_DRIVE_LOW | MFPR_SLEEP_OE_N)
+#define MFPR_LPM_PULL_HIGH (MFPR_LPM_DRIVE_HIGH | MFPR_SLEEP_OE_N)
+#define MFPR_LPM_FLOAT (MFPR_SLEEP_OE_N)
+#define MFPR_LPM_MASK (0xe080)
+
+/*
+ * The pullup and pulldown state of the MFP pin at run mode is by default
+ * determined by the selected alternate function. In case that some buggy
+ * devices need to override this default behavior, the definitions below
+ * indicates the setting of corresponding MFPR bits
+ *
+ * Definition pull_sel pullup_en pulldown_en
+ * MFPR_PULL_NONE 0 0 0
+ * MFPR_PULL_LOW 1 0 1
+ * MFPR_PULL_HIGH 1 1 0
+ * MFPR_PULL_BOTH 1 1 1
+ */
+#define MFPR_PULL_NONE (0)
+#define MFPR_PULL_LOW (MFPR_PULL_SEL | MFPR_PULLDOWN_EN)
+#define MFPR_PULL_BOTH (MFPR_PULL_LOW | MFPR_PULLUP_EN)
+#define MFPR_PULL_HIGH (MFPR_PULL_SEL | MFPR_PULLUP_EN)
+
+/* PXA3xx common MFP configurations - processor specific ones defined
+ * in mfp-pxa300.h and mfp-pxa320.h
+ */
+#define GPIO0_GPIO MFP_CFG(GPIO0, AF0)
+#define GPIO1_GPIO MFP_CFG(GPIO1, AF0)
+#define GPIO2_GPIO MFP_CFG(GPIO2, AF0)
+#define GPIO3_GPIO MFP_CFG(GPIO3, AF0)
+#define GPIO4_GPIO MFP_CFG(GPIO4, AF0)
+#define GPIO5_GPIO MFP_CFG(GPIO5, AF0)
+#define GPIO6_GPIO MFP_CFG(GPIO6, AF0)
+#define GPIO7_GPIO MFP_CFG(GPIO7, AF0)
+#define GPIO8_GPIO MFP_CFG(GPIO8, AF0)
+#define GPIO9_GPIO MFP_CFG(GPIO9, AF0)
+#define GPIO10_GPIO MFP_CFG(GPIO10, AF0)
+#define GPIO11_GPIO MFP_CFG(GPIO11, AF0)
+#define GPIO12_GPIO MFP_CFG(GPIO12, AF0)
+#define GPIO13_GPIO MFP_CFG(GPIO13, AF0)
+#define GPIO14_GPIO MFP_CFG(GPIO14, AF0)
+#define GPIO15_GPIO MFP_CFG(GPIO15, AF0)
+#define GPIO16_GPIO MFP_CFG(GPIO16, AF0)
+#define GPIO17_GPIO MFP_CFG(GPIO17, AF0)
+#define GPIO18_GPIO MFP_CFG(GPIO18, AF0)
+#define GPIO19_GPIO MFP_CFG(GPIO19, AF0)
+#define GPIO20_GPIO MFP_CFG(GPIO20, AF0)
+#define GPIO21_GPIO MFP_CFG(GPIO21, AF0)
+#define GPIO22_GPIO MFP_CFG(GPIO22, AF0)
+#define GPIO23_GPIO MFP_CFG(GPIO23, AF0)
+#define GPIO24_GPIO MFP_CFG(GPIO24, AF0)
+#define GPIO25_GPIO MFP_CFG(GPIO25, AF0)
+#define GPIO26_GPIO MFP_CFG(GPIO26, AF0)
+#define GPIO27_GPIO MFP_CFG(GPIO27, AF0)
+#define GPIO28_GPIO MFP_CFG(GPIO28, AF0)
+#define GPIO29_GPIO MFP_CFG(GPIO29, AF0)
+#define GPIO30_GPIO MFP_CFG(GPIO30, AF0)
+#define GPIO31_GPIO MFP_CFG(GPIO31, AF0)
+#define GPIO32_GPIO MFP_CFG(GPIO32, AF0)
+#define GPIO33_GPIO MFP_CFG(GPIO33, AF0)
+#define GPIO34_GPIO MFP_CFG(GPIO34, AF0)
+#define GPIO35_GPIO MFP_CFG(GPIO35, AF0)
+#define GPIO36_GPIO MFP_CFG(GPIO36, AF0)
+#define GPIO37_GPIO MFP_CFG(GPIO37, AF0)
+#define GPIO38_GPIO MFP_CFG(GPIO38, AF0)
+#define GPIO39_GPIO MFP_CFG(GPIO39, AF0)
+#define GPIO40_GPIO MFP_CFG(GPIO40, AF0)
+#define GPIO41_GPIO MFP_CFG(GPIO41, AF0)
+#define GPIO42_GPIO MFP_CFG(GPIO42, AF0)
+#define GPIO43_GPIO MFP_CFG(GPIO43, AF0)
+#define GPIO44_GPIO MFP_CFG(GPIO44, AF0)
+#define GPIO45_GPIO MFP_CFG(GPIO45, AF0)
+
+#define GPIO47_GPIO MFP_CFG(GPIO47, AF0)
+#define GPIO48_GPIO MFP_CFG(GPIO48, AF0)
+
+#define GPIO53_GPIO MFP_CFG(GPIO53, AF0)
+#define GPIO54_GPIO MFP_CFG(GPIO54, AF0)
+#define GPIO55_GPIO MFP_CFG(GPIO55, AF0)
+
+#define GPIO57_GPIO MFP_CFG(GPIO57, AF0)
+
+#define GPIO63_GPIO MFP_CFG(GPIO63, AF0)
+#define GPIO64_GPIO MFP_CFG(GPIO64, AF0)
+#define GPIO65_GPIO MFP_CFG(GPIO65, AF0)
+#define GPIO66_GPIO MFP_CFG(GPIO66, AF0)
+#define GPIO67_GPIO MFP_CFG(GPIO67, AF0)
+#define GPIO68_GPIO MFP_CFG(GPIO68, AF0)
+#define GPIO69_GPIO MFP_CFG(GPIO69, AF0)
+#define GPIO70_GPIO MFP_CFG(GPIO70, AF0)
+#define GPIO71_GPIO MFP_CFG(GPIO71, AF0)
+#define GPIO72_GPIO MFP_CFG(GPIO72, AF0)
+#define GPIO73_GPIO MFP_CFG(GPIO73, AF0)
+#define GPIO74_GPIO MFP_CFG(GPIO74, AF0)
+#define GPIO75_GPIO MFP_CFG(GPIO75, AF0)
+#define GPIO76_GPIO MFP_CFG(GPIO76, AF0)
+#define GPIO77_GPIO MFP_CFG(GPIO77, AF0)
+#define GPIO78_GPIO MFP_CFG(GPIO78, AF0)
+#define GPIO79_GPIO MFP_CFG(GPIO79, AF0)
+#define GPIO80_GPIO MFP_CFG(GPIO80, AF0)
+#define GPIO81_GPIO MFP_CFG(GPIO81, AF0)
+#define GPIO82_GPIO MFP_CFG(GPIO82, AF0)
+#define GPIO83_GPIO MFP_CFG(GPIO83, AF0)
+#define GPIO84_GPIO MFP_CFG(GPIO84, AF0)
+#define GPIO85_GPIO MFP_CFG(GPIO85, AF0)
+#define GPIO86_GPIO MFP_CFG(GPIO86, AF0)
+#define GPIO87_GPIO MFP_CFG(GPIO87, AF0)
+#define GPIO88_GPIO MFP_CFG(GPIO88, AF0)
+#define GPIO89_GPIO MFP_CFG(GPIO89, AF0)
+#define GPIO90_GPIO MFP_CFG(GPIO90, AF0)
+#define GPIO91_GPIO MFP_CFG(GPIO91, AF0)
+#define GPIO92_GPIO MFP_CFG(GPIO92, AF0)
+#define GPIO93_GPIO MFP_CFG(GPIO93, AF0)
+#define GPIO94_GPIO MFP_CFG(GPIO94, AF0)
+#define GPIO95_GPIO MFP_CFG(GPIO95, AF0)
+#define GPIO96_GPIO MFP_CFG(GPIO96, AF0)
+#define GPIO97_GPIO MFP_CFG(GPIO97, AF0)
+#define GPIO98_GPIO MFP_CFG(GPIO98, AF0)
+#define GPIO99_GPIO MFP_CFG(GPIO99, AF0)
+#define GPIO100_GPIO MFP_CFG(GPIO100, AF0)
+#define GPIO101_GPIO MFP_CFG(GPIO101, AF0)
+#define GPIO102_GPIO MFP_CFG(GPIO102, AF0)
+#define GPIO103_GPIO MFP_CFG(GPIO103, AF0)
+#define GPIO104_GPIO MFP_CFG(GPIO104, AF0)
+#define GPIO105_GPIO MFP_CFG(GPIO105, AF0)
+#define GPIO106_GPIO MFP_CFG(GPIO106, AF0)
+#define GPIO107_GPIO MFP_CFG(GPIO107, AF0)
+#define GPIO108_GPIO MFP_CFG(GPIO108, AF0)
+#define GPIO109_GPIO MFP_CFG(GPIO109, AF0)
+#define GPIO110_GPIO MFP_CFG(GPIO110, AF0)
+#define GPIO111_GPIO MFP_CFG(GPIO111, AF0)
+#define GPIO112_GPIO MFP_CFG(GPIO112, AF0)
+#define GPIO113_GPIO MFP_CFG(GPIO113, AF0)
+#define GPIO114_GPIO MFP_CFG(GPIO114, AF0)
+#define GPIO115_GPIO MFP_CFG(GPIO115, AF0)
+#define GPIO116_GPIO MFP_CFG(GPIO116, AF0)
+#define GPIO117_GPIO MFP_CFG(GPIO117, AF0)
+#define GPIO118_GPIO MFP_CFG(GPIO118, AF0)
+#define GPIO119_GPIO MFP_CFG(GPIO119, AF0)
+#define GPIO120_GPIO MFP_CFG(GPIO120, AF0)
+#define GPIO121_GPIO MFP_CFG(GPIO121, AF0)
+#define GPIO122_GPIO MFP_CFG(GPIO122, AF0)
+#define GPIO123_GPIO MFP_CFG(GPIO123, AF0)
+#define GPIO124_GPIO MFP_CFG(GPIO124, AF0)
+#define GPIO125_GPIO MFP_CFG(GPIO125, AF0)
+#define GPIO126_GPIO MFP_CFG(GPIO126, AF0)
+#define GPIO127_GPIO MFP_CFG(GPIO127, AF0)
+
+#define GPIO0_2_GPIO MFP_CFG(GPIO0_2, AF0)
+#define GPIO1_2_GPIO MFP_CFG(GPIO1_2, AF0)
+#define GPIO2_2_GPIO MFP_CFG(GPIO2_2, AF0)
+#define GPIO3_2_GPIO MFP_CFG(GPIO3_2, AF0)
+#define GPIO4_2_GPIO MFP_CFG(GPIO4_2, AF0)
+#define GPIO5_2_GPIO MFP_CFG(GPIO5_2, AF0)
+#define GPIO6_2_GPIO MFP_CFG(GPIO6_2, AF0)
+
+/*
+ * each MFP pin will have a MFPR register, since the offset of the
+ * register varies between processors, the processor specific code
+ * should initialize the pin offsets by pxa3xx_mfp_init_addr()
+ *
+ * pxa3xx_mfp_init_addr - accepts a table of "pxa3xx_mfp_addr_map"
+ * structure, which represents a range of MFP pins from "start" to
+ * "end", with the offset begining at "offset", to define a single
+ * pin, let "end" = -1
+ *
+ * use
+ *
+ * MFP_ADDR_X() to define a range of pins
+ * MFP_ADDR() to define a single pin
+ * MFP_ADDR_END to signal the end of pin offset definitions
+ */
+struct pxa3xx_mfp_addr_map {
+ unsigned int start;
+ unsigned int end;
+ unsigned long offset;
+};
+
+#define MFP_ADDR_X(start, end, offset) \
+ { MFP_PIN_##start, MFP_PIN_##end, offset }
+
+#define MFP_ADDR(pin, offset) \
+ { MFP_PIN_##pin, -1, offset }
+
+#define MFP_ADDR_END { MFP_PIN_INVALID, 0 }
+
+/*
+ * pxa3xx_mfp_read()/pxa3xx_mfp_write() - for direct read/write access
+ * to the MFPR register
+ */
+unsigned long pxa3xx_mfp_read(int mfp);
+void pxa3xx_mfp_write(int mfp, unsigned long mfpr_val);
+
+/*
+ * pxa3xx_mfp_config - configure the MFPR registers
+ *
+ * used by board specific initialization code
+ */
+void pxa3xx_mfp_config(unsigned long *mfp_cfgs, int num);
+
+/*
+ * pxa3xx_mfp_init_addr() - initialize the mapping between mfp pin
+ * index and MFPR register offset
+ *
+ * used by processor specific code
+ */
+void __init pxa3xx_mfp_init_addr(struct pxa3xx_mfp_addr_map *);
+void __init pxa3xx_init_mfp(void);
+#endif /* __ASM_ARCH_MFP_PXA3XX_H */
diff --git a/include/asm-arm/arch-pxa/mfp.h b/include/asm-arm/arch-pxa/mfp.h
index 03c508d94f0..02f6157396d 100644
--- a/include/asm-arm/arch-pxa/mfp.h
+++ b/include/asm-arm/arch-pxa/mfp.h
@@ -16,9 +16,6 @@
#ifndef __ASM_ARCH_MFP_H
#define __ASM_ARCH_MFP_H
-#define MFPR_BASE (0x40e10000)
-#define MFPR_SIZE (PAGE_SIZE)
-
#define mfp_to_gpio(m) ((m) % 128)
/* list of all the configurable MFP pins */
@@ -217,114 +214,21 @@ enum {
};
/*
- * Table that determines the low power modes outputs, with actual settings
- * used in parentheses for don't-care values. Except for the float output,
- * the configured driven and pulled levels match, so if there is a need for
- * non-LPM pulled output, the same configuration could probably be used.
- *
- * Output value sleep_oe_n sleep_data pullup_en pulldown_en pull_sel
- * (bit 7) (bit 8) (bit 14d) (bit 13d)
- *
- * Drive 0 0 0 0 X (1) 0
- * Drive 1 0 1 X (1) 0 0
- * Pull hi (1) 1 X(1) 1 0 0
- * Pull lo (0) 1 X(0) 0 1 0
- * Z (float) 1 X(0) 0 0 0
- */
-#define MFP_LPM_DRIVE_LOW 0x8
-#define MFP_LPM_DRIVE_HIGH 0x6
-#define MFP_LPM_PULL_HIGH 0x7
-#define MFP_LPM_PULL_LOW 0x9
-#define MFP_LPM_FLOAT 0x1
-#define MFP_LPM_PULL_NEITHER 0x0
-
-/*
- * The pullup and pulldown state of the MFP pin is by default determined by
- * selected alternate function. In case some buggy devices need to override
- * this default behavior, pxa3xx_mfp_set_pull() can be invoked with one of
- * the following definition as the parameter.
- *
- * Definition pull_sel pullup_en pulldown_en
- * MFP_PULL_HIGH 1 1 0
- * MFP_PULL_LOW 1 0 1
- * MFP_PULL_BOTH 1 1 1
- * MFP_PULL_NONE 1 0 0
- * MFP_PULL_DEFAULT 0 X X
- *
- * NOTE: pxa3xx_mfp_set_pull() will modify the PULLUP_EN and PULLDOWN_EN
- * bits, which will cause potential conflicts with the low power mode
- * setting, device drivers should take care of this
- */
-#define MFP_PULL_BOTH (0x7u)
-#define MFP_PULL_HIGH (0x6u)
-#define MFP_PULL_LOW (0x5u)
-#define MFP_PULL_NONE (0x4u)
-#define MFP_PULL_DEFAULT (0x0u)
-
-#define MFP_AF0 (0)
-#define MFP_AF1 (1)
-#define MFP_AF2 (2)
-#define MFP_AF3 (3)
-#define MFP_AF4 (4)
-#define MFP_AF5 (5)
-#define MFP_AF6 (6)
-#define MFP_AF7 (7)
-
-#define MFP_DS01X (0)
-#define MFP_DS02X (1)
-#define MFP_DS03X (2)
-#define MFP_DS04X (3)
-#define MFP_DS06X (4)
-#define MFP_DS08X (5)
-#define MFP_DS10X (6)
-#define MFP_DS12X (7)
-
-#define MFP_EDGE_BOTH 0x3
-#define MFP_EDGE_RISE 0x2
-#define MFP_EDGE_FALL 0x1
-#define MFP_EDGE_NONE 0x0
-
-#define MFPR_AF_MASK 0x0007
-#define MFPR_DRV_MASK 0x1c00
-#define MFPR_RDH_MASK 0x0200
-#define MFPR_LPM_MASK 0xe180
-#define MFPR_PULL_MASK 0xe000
-#define MFPR_EDGE_MASK 0x0070
-
-#define MFPR_ALT_OFFSET 0
-#define MFPR_ERE_OFFSET 4
-#define MFPR_EFE_OFFSET 5
-#define MFPR_EC_OFFSET 6
-#define MFPR_SON_OFFSET 7
-#define MFPR_SD_OFFSET 8
-#define MFPR_SS_OFFSET 9
-#define MFPR_DRV_OFFSET 10
-#define MFPR_PD_OFFSET 13
-#define MFPR_PU_OFFSET 14
-#define MFPR_PS_OFFSET 15
-
-#define MFPR(af, drv, rdh, lpm, edge) \
- (((af) & 0x7) | (((drv) & 0x7) << 10) |\
- (((rdh) & 0x1) << 9) |\
- (((lpm) & 0x3) << 7) |\
- (((lpm) & 0x4) << 12)|\
- (((lpm) & 0x8) << 10)|\
- ((!(edge)) << 6) |\
- (((edge) & 0x1) << 5) |\
- (((edge) & 0x2) << 3))
-
-/*
* a possible MFP configuration is represented by a 32-bit integer
- * bit 0..15 - MFPR value (16-bit)
- * bit 16..31 - mfp pin index (used to obtain the MFPR offset)
+ *
+ * bit 0.. 9 - MFP Pin Number (1024 Pins Maximum)
+ * bit 10..12 - Alternate Function Selection
+ * bit 13..15 - Drive Strength
+ * bit 16..18 - Low Power Mode State
+ * bit 19..20 - Low Power Mode Edge Detection
+ * bit 21..22 - Run Mode Pull State
*
* to facilitate the definition, the following macros are provided
*
- * MFPR_DEFAULT - default MFPR value, with
+ * MFP_CFG_DEFAULT - default MFP configuration value, with
* alternate function = 0,
- * drive strength = fast 1mA (MFP_DS01X)
+ * drive strength = fast 3mA (MFP_DS03X)
* low power mode = default
- * release dalay hold = false (RDH bit)
* edge detection = none
*
* MFP_CFG - default MFPR value with alternate function
@@ -334,251 +238,74 @@ enum {
* low power mode
* MFP_CFG_X - default MFPR value with alternate function,
* pin drive strength and low power mode
- *
- * use
- *
- * MFP_CFG_PIN - to get the MFP pin index
- * MFP_CFG_VAL - to get the corresponding MFPR value
*/
-typedef uint32_t mfp_cfg_t;
-
-#define MFP_CFG_PIN(mfp_cfg) (((mfp_cfg) >> 16) & 0xffff)
-#define MFP_CFG_VAL(mfp_cfg) ((mfp_cfg) & 0xffff)
-
-/*
- * MFP register defaults to
- * drive strength fast 3mA (010'b)
- * edge detection logic disabled
- * alternate function 0
- */
-#define MFPR_DEFAULT (0x0840)
+typedef unsigned long mfp_cfg_t;
+
+#define MFP_PIN(x) ((x) & 0x3ff)
+
+#define MFP_AF0 (0x0 << 10)
+#define MFP_AF1 (0x1 << 10)
+#define MFP_AF2 (0x2 << 10)
+#define MFP_AF3 (0x3 << 10)
+#define MFP_AF4 (0x4 << 10)
+#define MFP_AF5 (0x5 << 10)
+#define MFP_AF6 (0x6 << 10)
+#define MFP_AF7 (0x7 << 10)
+#define MFP_AF_MASK (0x7 << 10)
+#define MFP_AF(x) (((x) >> 10) & 0x7)
+
+#define MFP_DS01X (0x0 << 13)
+#define MFP_DS02X (0x1 << 13)
+#define MFP_DS03X (0x2 << 13)
+#define MFP_DS04X (0x3 << 13)
+#define MFP_DS06X (0x4 << 13)
+#define MFP_DS08X (0x5 << 13)
+#define MFP_DS10X (0x6 << 13)
+#define MFP_DS13X (0x7 << 13)
+#define MFP_DS_MASK (0x7 << 13)
+#define MFP_DS(x) (((x) >> 13) & 0x7)
+
+#define MFP_LPM_INPUT (0x0 << 16)
+#define MFP_LPM_DRIVE_LOW (0x1 << 16)
+#define MFP_LPM_DRIVE_HIGH (0x2 << 16)
+#define MFP_LPM_PULL_LOW (0x3 << 16)
+#define MFP_LPM_PULL_HIGH (0x4 << 16)
+#define MFP_LPM_FLOAT (0x5 << 16)
+#define MFP_LPM_STATE_MASK (0x7 << 16)
+#define MFP_LPM_STATE(x) (((x) >> 16) & 0x7)
+
+#define MFP_LPM_EDGE_NONE (0x0 << 19)
+#define MFP_LPM_EDGE_RISE (0x1 << 19)
+#define MFP_LPM_EDGE_FALL (0x2 << 19)
+#define MFP_LPM_EDGE_BOTH (0x3 << 19)
+#define MFP_LPM_EDGE_MASK (0x3 << 19)
+#define MFP_LPM_EDGE(x) (((x) >> 19) & 0x3)
+
+#define MFP_PULL_NONE (0x0 << 21)
+#define MFP_PULL_LOW (0x1 << 21)
+#define MFP_PULL_HIGH (0x2 << 21)
+#define MFP_PULL_BOTH (0x3 << 21)
+#define MFP_PULL_MASK (0x3 << 21)
+#define MFP_PULL(x) (((x) >> 21) & 0x3)
+
+#define MFP_CFG_DEFAULT (MFP_AF0 | MFP_DS03X | MFP_LPM_INPUT |\
+ MFP_LPM_EDGE_NONE | MFP_PULL_NONE)
#define MFP_CFG(pin, af) \
- ((MFP_PIN_##pin << 16) | MFPR_DEFAULT | (MFP_##af))
+ ((MFP_CFG_DEFAULT & ~MFP_AF_MASK) |\
+ (MFP_PIN(MFP_PIN_##pin) | MFP_##af))
#define MFP_CFG_DRV(pin, af, drv) \
- ((MFP_PIN_##pin << 16) | (MFPR_DEFAULT & ~MFPR_DRV_MASK) |\
- ((MFP_##drv) << 10) | (MFP_##af))
+ ((MFP_CFG_DEFAULT & ~(MFP_AF_MASK | MFP_DS_MASK)) |\
+ (MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_##drv))
#define MFP_CFG_LPM(pin, af, lpm) \
- ((MFP_PIN_##pin << 16) | (MFPR_DEFAULT & ~MFPR_LPM_MASK) |\
- (((MFP_LPM_##lpm) & 0x3) << 7) |\
- (((MFP_LPM_##lpm) & 0x4) << 12) |\
- (((MFP_LPM_##lpm) & 0x8) << 10) |\
- (MFP_##af))
+ ((MFP_CFG_DEFAULT & ~(MFP_AF_MASK | MFP_LPM_STATE_MASK)) |\
+ (MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_LPM_##lpm))
#define MFP_CFG_X(pin, af, drv, lpm) \
- ((MFP_PIN_##pin << 16) |\
- (MFPR_DEFAULT & ~(MFPR_DRV_MASK | MFPR_LPM_MASK)) |\
- ((MFP_##drv) << 10) | (MFP_##af) |\
- (((MFP_LPM_##lpm) & 0x3) << 7) |\
- (((MFP_LPM_##lpm) & 0x4) << 12) |\
- (((MFP_LPM_##lpm) & 0x8) << 10))
-
-/* common MFP configurations - processor specific ones defined
- * in mfp-pxa3xx.h
- */
-#define GPIO0_GPIO MFP_CFG(GPIO0, AF0)
-#define GPIO1_GPIO MFP_CFG(GPIO1, AF0)
-#define GPIO2_GPIO MFP_CFG(GPIO2, AF0)
-#define GPIO3_GPIO MFP_CFG(GPIO3, AF0)
-#define GPIO4_GPIO MFP_CFG(GPIO4, AF0)
-#define GPIO5_GPIO MFP_CFG(GPIO5, AF0)
-#define GPIO6_GPIO MFP_CFG(GPIO6, AF0)
-#define GPIO7_GPIO MFP_CFG(GPIO7, AF0)
-#define GPIO8_GPIO MFP_CFG(GPIO8, AF0)
-#define GPIO9_GPIO MFP_CFG(GPIO9, AF0)
-#define GPIO10_GPIO MFP_CFG(GPIO10, AF0)
-#define GPIO11_GPIO MFP_CFG(GPIO11, AF0)
-#define GPIO12_GPIO MFP_CFG(GPIO12, AF0)
-#define GPIO13_GPIO MFP_CFG(GPIO13, AF0)
-#define GPIO14_GPIO MFP_CFG(GPIO14, AF0)
-#define GPIO15_GPIO MFP_CFG(GPIO15, AF0)
-#define GPIO16_GPIO MFP_CFG(GPIO16, AF0)
-#define GPIO17_GPIO MFP_CFG(GPIO17, AF0)
-#define GPIO18_GPIO MFP_CFG(GPIO18, AF0)
-#define GPIO19_GPIO MFP_CFG(GPIO19, AF0)
-#define GPIO20_GPIO MFP_CFG(GPIO20, AF0)
-#define GPIO21_GPIO MFP_CFG(GPIO21, AF0)
-#define GPIO22_GPIO MFP_CFG(GPIO22, AF0)
-#define GPIO23_GPIO MFP_CFG(GPIO23, AF0)
-#define GPIO24_GPIO MFP_CFG(GPIO24, AF0)
-#define GPIO25_GPIO MFP_CFG(GPIO25, AF0)
-#define GPIO26_GPIO MFP_CFG(GPIO26, AF0)
-#define GPIO27_GPIO MFP_CFG(GPIO27, AF0)
-#define GPIO28_GPIO MFP_CFG(GPIO28, AF0)
-#define GPIO29_GPIO MFP_CFG(GPIO29, AF0)
-#define GPIO30_GPIO MFP_CFG(GPIO30, AF0)
-#define GPIO31_GPIO MFP_CFG(GPIO31, AF0)
-#define GPIO32_GPIO MFP_CFG(GPIO32, AF0)
-#define GPIO33_GPIO MFP_CFG(GPIO33, AF0)
-#define GPIO34_GPIO MFP_CFG(GPIO34, AF0)
-#define GPIO35_GPIO MFP_CFG(GPIO35, AF0)
-#define GPIO36_GPIO MFP_CFG(GPIO36, AF0)
-#define GPIO37_GPIO MFP_CFG(GPIO37, AF0)
-#define GPIO38_GPIO MFP_CFG(GPIO38, AF0)
-#define GPIO39_GPIO MFP_CFG(GPIO39, AF0)
-#define GPIO40_GPIO MFP_CFG(GPIO40, AF0)
-#define GPIO41_GPIO MFP_CFG(GPIO41, AF0)
-#define GPIO42_GPIO MFP_CFG(GPIO42, AF0)
-#define GPIO43_GPIO MFP_CFG(GPIO43, AF0)
-#define GPIO44_GPIO MFP_CFG(GPIO44, AF0)
-#define GPIO45_GPIO MFP_CFG(GPIO45, AF0)
-
-#define GPIO47_GPIO MFP_CFG(GPIO47, AF0)
-#define GPIO48_GPIO MFP_CFG(GPIO48, AF0)
-
-#define GPIO53_GPIO MFP_CFG(GPIO53, AF0)
-#define GPIO54_GPIO MFP_CFG(GPIO54, AF0)
-#define GPIO55_GPIO MFP_CFG(GPIO55, AF0)
-
-#define GPIO57_GPIO MFP_CFG(GPIO57, AF0)
-
-#define GPIO63_GPIO MFP_CFG(GPIO63, AF0)
-#define GPIO64_GPIO MFP_CFG(GPIO64, AF0)
-#define GPIO65_GPIO MFP_CFG(GPIO65, AF0)
-#define GPIO66_GPIO MFP_CFG(GPIO66, AF0)
-#define GPIO67_GPIO MFP_CFG(GPIO67, AF0)
-#define GPIO68_GPIO MFP_CFG(GPIO68, AF0)
-#define GPIO69_GPIO MFP_CFG(GPIO69, AF0)
-#define GPIO70_GPIO MFP_CFG(GPIO70, AF0)
-#define GPIO71_GPIO MFP_CFG(GPIO71, AF0)
-#define GPIO72_GPIO MFP_CFG(GPIO72, AF0)
-#define GPIO73_GPIO MFP_CFG(GPIO73, AF0)
-#define GPIO74_GPIO MFP_CFG(GPIO74, AF0)
-#define GPIO75_GPIO MFP_CFG(GPIO75, AF0)
-#define GPIO76_GPIO MFP_CFG(GPIO76, AF0)
-#define GPIO77_GPIO MFP_CFG(GPIO77, AF0)
-#define GPIO78_GPIO MFP_CFG(GPIO78, AF0)
-#define GPIO79_GPIO MFP_CFG(GPIO79, AF0)
-#define GPIO80_GPIO MFP_CFG(GPIO80, AF0)
-#define GPIO81_GPIO MFP_CFG(GPIO81, AF0)
-#define GPIO82_GPIO MFP_CFG(GPIO82, AF0)
-#define GPIO83_GPIO MFP_CFG(GPIO83, AF0)
-#define GPIO84_GPIO MFP_CFG(GPIO84, AF0)
-#define GPIO85_GPIO MFP_CFG(GPIO85, AF0)
-#define GPIO86_GPIO MFP_CFG(GPIO86, AF0)
-#define GPIO87_GPIO MFP_CFG(GPIO87, AF0)
-#define GPIO88_GPIO MFP_CFG(GPIO88, AF0)
-#define GPIO89_GPIO MFP_CFG(GPIO89, AF0)
-#define GPIO90_GPIO MFP_CFG(GPIO90, AF0)
-#define GPIO91_GPIO MFP_CFG(GPIO91, AF0)
-#define GPIO92_GPIO MFP_CFG(GPIO92, AF0)
-#define GPIO93_GPIO MFP_CFG(GPIO93, AF0)
-#define GPIO94_GPIO MFP_CFG(GPIO94, AF0)
-#define GPIO95_GPIO MFP_CFG(GPIO95, AF0)
-#define GPIO96_GPIO MFP_CFG(GPIO96, AF0)
-#define GPIO97_GPIO MFP_CFG(GPIO97, AF0)
-#define GPIO98_GPIO MFP_CFG(GPIO98, AF0)
-#define GPIO99_GPIO MFP_CFG(GPIO99, AF0)
-#define GPIO100_GPIO MFP_CFG(GPIO100, AF0)
-#define GPIO101_GPIO MFP_CFG(GPIO101, AF0)
-#define GPIO102_GPIO MFP_CFG(GPIO102, AF0)
-#define GPIO103_GPIO MFP_CFG(GPIO103, AF0)
-#define GPIO104_GPIO MFP_CFG(GPIO104, AF0)
-#define GPIO105_GPIO MFP_CFG(GPIO105, AF0)
-#define GPIO106_GPIO MFP_CFG(GPIO106, AF0)
-#define GPIO107_GPIO MFP_CFG(GPIO107, AF0)
-#define GPIO108_GPIO MFP_CFG(GPIO108, AF0)
-#define GPIO109_GPIO MFP_CFG(GPIO109, AF0)
-#define GPIO110_GPIO MFP_CFG(GPIO110, AF0)
-#define GPIO111_GPIO MFP_CFG(GPIO111, AF0)
-#define GPIO112_GPIO MFP_CFG(GPIO112, AF0)
-#define GPIO113_GPIO MFP_CFG(GPIO113, AF0)
-#define GPIO114_GPIO MFP_CFG(GPIO114, AF0)
-#define GPIO115_GPIO MFP_CFG(GPIO115, AF0)
-#define GPIO116_GPIO MFP_CFG(GPIO116, AF0)
-#define GPIO117_GPIO MFP_CFG(GPIO117, AF0)
-#define GPIO118_GPIO MFP_CFG(GPIO118, AF0)
-#define GPIO119_GPIO MFP_CFG(GPIO119, AF0)
-#define GPIO120_GPIO MFP_CFG(GPIO120, AF0)
-#define GPIO121_GPIO MFP_CFG(GPIO121, AF0)
-#define GPIO122_GPIO MFP_CFG(GPIO122, AF0)
-#define GPIO123_GPIO MFP_CFG(GPIO123, AF0)
-#define GPIO124_GPIO MFP_CFG(GPIO124, AF0)
-#define GPIO125_GPIO MFP_CFG(GPIO125, AF0)
-#define GPIO126_GPIO MFP_CFG(GPIO126, AF0)
-#define GPIO127_GPIO MFP_CFG(GPIO127, AF0)
-
-#define GPIO0_2_GPIO MFP_CFG(GPIO0_2, AF0)
-#define GPIO1_2_GPIO MFP_CFG(GPIO1_2, AF0)
-#define GPIO2_2_GPIO MFP_CFG(GPIO2_2, AF0)
-#define GPIO3_2_GPIO MFP_CFG(GPIO3_2, AF0)
-#define GPIO4_2_GPIO MFP_CFG(GPIO4_2, AF0)
-#define GPIO5_2_GPIO MFP_CFG(GPIO5_2, AF0)
-#define GPIO6_2_GPIO MFP_CFG(GPIO6_2, AF0)
-
-/*
- * each MFP pin will have a MFPR register, since the offset of the
- * register varies between processors, the processor specific code
- * should initialize the pin offsets by pxa3xx_mfp_init_addr()
- *
- * pxa3xx_mfp_init_addr - accepts a table of "pxa3xx_mfp_addr_map"
- * structure, which represents a range of MFP pins from "start" to
- * "end", with the offset begining at "offset", to define a single
- * pin, let "end" = -1
- *
- * use
- *
- * MFP_ADDR_X() to define a range of pins
- * MFP_ADDR() to define a single pin
- * MFP_ADDR_END to signal the end of pin offset definitions
- */
-struct pxa3xx_mfp_addr_map {
- unsigned int start;
- unsigned int end;
- unsigned long offset;
-};
-
-#define MFP_ADDR_X(start, end, offset) \
- { MFP_PIN_##start, MFP_PIN_##end, offset }
-
-#define MFP_ADDR(pin, offset) \
- { MFP_PIN_##pin, -1, offset }
-
-#define MFP_ADDR_END { MFP_PIN_INVALID, 0 }
-
-struct pxa3xx_mfp_pin {
- unsigned long mfpr_off; /* MFPRxx register offset */
- unsigned long mfpr_val; /* MFPRxx register value */
-};
-
-/*
- * pxa3xx_mfp_read()/pxa3xx_mfp_write() - for direct read/write access
- * to the MFPR register
- */
-unsigned long pxa3xx_mfp_read(int mfp);
-void pxa3xx_mfp_write(int mfp, unsigned long mfpr_val);
-
-/*
- * pxa3xx_mfp_set_afds - set MFP alternate function and drive strength
- * pxa3xx_mfp_set_rdh - set MFP release delay hold on/off
- * pxa3xx_mfp_set_lpm - set MFP low power mode state
- * pxa3xx_mfp_set_edge - set MFP edge detection in low power mode
- *
- * use these functions to override/change the default configuration
- * done by pxa3xx_mfp_set_config(s)
- */
-void pxa3xx_mfp_set_afds(int mfp, int af, int ds);
-void pxa3xx_mfp_set_rdh(int mfp, int rdh);
-void pxa3xx_mfp_set_lpm(int mfp, int lpm);
-void pxa3xx_mfp_set_edge(int mfp, int edge);
-
-/*
- * pxa3xx_mfp_config - configure the MFPR registers
- *
- * used by board specific initialization code
- */
-void pxa3xx_mfp_config(mfp_cfg_t *mfp_cfgs, int num);
-
-/*
- * pxa3xx_mfp_init_addr() - initialize the mapping between mfp pin
- * index and MFPR register offset
- *
- * used by processor specific code
- */
-void __init pxa3xx_mfp_init_addr(struct pxa3xx_mfp_addr_map *);
-void __init pxa3xx_init_mfp(void);
+ ((MFP_CFG_DEFAULT & ~(MFP_AF_MASK | MFP_DS_MASK | MFP_LPM_STATE_MASK)) |\
+ (MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_##drv | MFP_LPM_##lpm))
#endif /* __ASM_ARCH_MFP_H */
diff --git a/include/asm-arm/arch-pxa/mmc.h b/include/asm-arm/arch-pxa/mmc.h
index ef4f570381d..6d1304c9270 100644
--- a/include/asm-arm/arch-pxa/mmc.h
+++ b/include/asm-arm/arch-pxa/mmc.h
@@ -17,5 +17,7 @@ struct pxamci_platform_data {
};
extern void pxa_set_mci_info(struct pxamci_platform_data *info);
+extern void pxa3xx_set_mci2_info(struct pxamci_platform_data *info);
+extern void pxa3xx_set_mci3_info(struct pxamci_platform_data *info);
#endif
diff --git a/include/asm-arm/arch-pxa/pcm027.h b/include/asm-arm/arch-pxa/pcm027.h
new file mode 100644
index 00000000000..7beae1472c3
--- /dev/null
+++ b/include/asm-arm/arch-pxa/pcm027.h
@@ -0,0 +1,75 @@
+/*
+ * linux/include/asm-arm/arch-pxa/pcm027.h
+ *
+ * (c) 2003 Phytec Messtechnik GmbH <armlinux@phytec.de>
+ * (c) 2007 Juergen Beisert <j.beisert@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+/*
+ * Definitions of CPU card resources only
+ */
+
+/* I2C RTC */
+#define PCM027_RTC_IRQ_GPIO 0
+#define PCM027_RTC_IRQ IRQ_GPIO(PCM027_RTC_IRQ_GPIO)
+#define PCM027_RTC_IRQ_EDGE IRQ_TYPE_EDGE_FALLING
+#define ADR_PCM027_RTC 0x51 /* I2C address */
+
+/* I2C EEPROM */
+#define ADR_PCM027_EEPROM 0x54 /* I2C address */
+
+/* Ethernet chip (SMSC91C111) */
+#define PCM027_ETH_IRQ_GPIO 52
+#define PCM027_ETH_IRQ IRQ_GPIO(PCM027_ETH_IRQ_GPIO)
+#define PCM027_ETH_IRQ_EDGE IRQ_TYPE_EDGE_RISING
+#define PCM027_ETH_PHYS PXA_CS5_PHYS
+#define PCM027_ETH_SIZE (1*1024*1024)
+
+/* CAN controller SJA1000 (unsupported yet) */
+#define PCM027_CAN_IRQ_GPIO 114
+#define PCM027_CAN_IRQ IRQ_GPIO(PCM027_CAN_IRQ_GPIO)
+#define PCM027_CAN_IRQ_EDGE IRQ_TYPE_EDGE_FALLING
+#define PCM027_CAN_PHYS 0x22000000
+#define PCM027_CAN_SIZE 0x100
+
+/* SPI GPIO expander (unsupported yet) */
+#define PCM027_EGPIO_IRQ_GPIO 27
+#define PCM027_EGPIO_IRQ IRQ_GPIO(PCM027_EGPIO_IRQ_GPIO)
+#define PCM027_EGPIO_IRQ_EDGE IRQ_TYPE_EDGE_FALLING
+#define PCM027_EGPIO_CS 24
+/*
+ * TODO: Switch this pin from dedicated usage to GPIO if
+ * more than the MAX7301 device is connected to this SPI bus
+ */
+#define PCM027_EGPIO_CS_MODE GPIO24_SFRM_MD
+
+/* Flash memory */
+#define PCM027_FLASH_PHYS 0x00000000
+#define PCM027_FLASH_SIZE 0x02000000
+
+/* onboard LEDs connected to GPIO */
+#define PCM027_LED_CPU 90
+#define PCM027_LED_HEARD_BEAT 91
+
+/*
+ * This CPU module needs a baseboard to work. After basic initializing
+ * its own devices, it calls baseboard's init function.
+ * TODO: Add your own basebaord init function and call it from
+ * inside pcm027_init(). This example here is for the developmen board.
+ * Refer pcm990-baseboard.c
+ */
+extern void pcm990_baseboard_init(void);
diff --git a/include/asm-arm/arch-pxa/pcm990_baseboard.h b/include/asm-arm/arch-pxa/pcm990_baseboard.h
new file mode 100644
index 00000000000..b699d0d7bdb
--- /dev/null
+++ b/include/asm-arm/arch-pxa/pcm990_baseboard.h
@@ -0,0 +1,275 @@
+/*
+ * include/asm-arm/arch-pxa/pcm990_baseboard.h
+ *
+ * (c) 2003 Phytec Messtechnik GmbH <armlinux@phytec.de>
+ * (c) 2007 Juergen Beisert <j.beisert@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#include <asm/arch/pcm027.h>
+
+/*
+ * definitions relevant only when the PCM-990
+ * development base board is in use
+ */
+
+/* CPLD's interrupt controller is connected to PCM-027 GPIO 9 */
+#define PCM990_CTRL_INT_IRQ_GPIO 9
+#define PCM990_CTRL_INT_IRQ IRQ_GPIO(PCM990_CTRL_INT_IRQ_GPIO)
+#define PCM990_CTRL_INT_IRQ_EDGE IRQT_RISING
+#define PCM990_CTRL_PHYS PXA_CS1_PHYS /* 16-Bit */
+#define PCM990_CTRL_BASE 0xea000000
+#define PCM990_CTRL_SIZE (1*1024*1024)
+
+#define PCM990_CTRL_PWR_IRQ_GPIO 14
+#define PCM990_CTRL_PWR_IRQ IRQ_GPIO(PCM990_CTRL_PWR_IRQ_GPIO)
+#define PCM990_CTRL_PWR_IRQ_EDGE IRQT_RISING
+
+/* visible CPLD (U7) registers */
+#define PCM990_CTRL_REG0 0x0000 /* RESET REGISTER */
+#define PCM990_CTRL_SYSRES 0x0001 /* System RESET REGISTER */
+#define PCM990_CTRL_RESOUT 0x0002 /* RESETOUT Enable REGISTER */
+#define PCM990_CTRL_RESGPIO 0x0004 /* RESETGPIO Enable REGISTER */
+
+#define PCM990_CTRL_REG1 0x0002 /* Power REGISTER */
+#define PCM990_CTRL_5VOFF 0x0001 /* Disable 5V Regulators */
+#define PCM990_CTRL_CANPWR 0x0004 /* Enable CANPWR ADUM */
+#define PCM990_CTRL_PM_5V 0x0008 /* Read 5V OK */
+
+#define PCM990_CTRL_REG2 0x0004 /* LED REGISTER */
+#define PCM990_CTRL_LEDPWR 0x0001 /* POWER LED enable */
+#define PCM990_CTRL_LEDBAS 0x0002 /* BASIS LED enable */
+#define PCM990_CTRL_LEDUSR 0x0004 /* USER LED enable */
+
+#define PCM990_CTRL_REG3 0x0006 /* LCD CTRL REGISTER 3 */
+#define PCM990_CTRL_LCDPWR 0x0001 /* RW LCD Power on */
+#define PCM990_CTRL_LCDON 0x0002 /* RW LCD Latch on */
+#define PCM990_CTRL_LCDPOS1 0x0004 /* RW POS 1 */
+#define PCM990_CTRL_LCDPOS2 0x0008 /* RW POS 2 */
+
+#define PCM990_CTRL_REG4 0x0008 /* MMC1 CTRL REGISTER 4 */
+#define PCM990_CTRL_MMC1PWR 0x0001 /* RW MMC1 Power on */
+
+#define PCM990_CTRL_REG5 0x000A /* MMC2 CTRL REGISTER 5 */
+#define PCM990_CTRL_MMC2PWR 0x0001 /* RW MMC2 Power on */
+#define PCM990_CTRL_MMC2LED 0x0002 /* RW MMC2 LED */
+#define PCM990_CTRL_MMC2DE 0x0004 /* R MMC2 Card detect */
+#define PCM990_CTRL_MMC2WP 0x0008 /* R MMC2 Card write protect */
+
+#define PCM990_CTRL_REG6 0x000C /* Interrupt Clear REGISTER */
+#define PCM990_CTRL_INTC0 0x0001 /* Clear Reg BT Detect */
+#define PCM990_CTRL_INTC1 0x0002 /* Clear Reg FR RI */
+#define PCM990_CTRL_INTC2 0x0004 /* Clear Reg MMC1 Detect */
+#define PCM990_CTRL_INTC3 0x0008 /* Clear Reg PM_5V off */
+
+#define PCM990_CTRL_REG7 0x000E /* Interrupt Enable REGISTER */
+#define PCM990_CTRL_ENAINT0 0x0001 /* Enable Int BT Detect */
+#define PCM990_CTRL_ENAINT1 0x0002 /* Enable Int FR RI */
+#define PCM990_CTRL_ENAINT2 0x0004 /* Enable Int MMC1 Detect */
+#define PCM990_CTRL_ENAINT3 0x0008 /* Enable Int PM_5V off */
+
+#define PCM990_CTRL_REG8 0x0014 /* Uart REGISTER */
+#define PCM990_CTRL_FFSD 0x0001 /* BT Uart Enable */
+#define PCM990_CTRL_BTSD 0x0002 /* FF Uart Enable */
+#define PCM990_CTRL_FFRI 0x0004 /* FF Uart RI detect */
+#define PCM990_CTRL_BTRX 0x0008 /* BT Uart Rx detect */
+
+#define PCM990_CTRL_REG9 0x0010 /* AC97 Flash REGISTER */
+#define PCM990_CTRL_FLWP 0x0001 /* pC Flash Write Protect */
+#define PCM990_CTRL_FLDIS 0x0002 /* pC Flash Disable */
+#define PCM990_CTRL_AC97ENA 0x0004 /* Enable AC97 Expansion */
+
+#define PCM990_CTRL_REG10 0x0012 /* GPS-REGISTER */
+#define PCM990_CTRL_GPSPWR 0x0004 /* GPS-Modul Power on */
+#define PCM990_CTRL_GPSENA 0x0008 /* GPS-Modul Enable */
+
+#define PCM990_CTRL_REG11 0x0014 /* Accu REGISTER */
+#define PCM990_CTRL_ACENA 0x0001 /* Charge Enable */
+#define PCM990_CTRL_ACSEL 0x0002 /* Charge Akku -> DC Enable */
+#define PCM990_CTRL_ACPRES 0x0004 /* DC Present */
+#define PCM990_CTRL_ACALARM 0x0008 /* Error Akku */
+
+#define PCM990_CTRL_P2V(x) ((x) - PCM990_CTRL_PHYS + PCM990_CTRL_BASE)
+#define PCM990_CTRL_V2P(x) ((x) - PCM990_CTRL_BASE + PCM990_CTRL_PHYS)
+
+#ifndef __ASSEMBLY__
+# define __PCM990_CTRL_REG(x) \
+ (*((volatile unsigned char *)PCM990_CTRL_P2V(x)))
+#else
+# define __PCM990_CTRL_REG(x) PCM990_CTRL_P2V(x)
+#endif
+
+#define PCM990_INTMSKENA __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG7)
+#define PCM990_INTSETCLR __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG6)
+#define PCM990_CTRL0 __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG0)
+#define PCM990_CTRL1 __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG1)
+#define PCM990_CTRL2 __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG2)
+#define PCM990_CTRL3 __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG3)
+#define PCM990_CTRL4 __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG4)
+#define PCM990_CTRL5 __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG5)
+#define PCM990_CTRL6 __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG6)
+#define PCM990_CTRL7 __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG7)
+#define PCM990_CTRL8 __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG8)
+#define PCM990_CTRL9 __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG9)
+#define PCM990_CTRL10 __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG10)
+#define PCM990_CTRL11 __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG11)
+
+
+/*
+ * IDE
+ */
+#define PCM990_IDE_IRQ_GPIO 13
+#define PCM990_IDE_IRQ IRQ_GPIO(PCM990_IDE_IRQ_GPIO)
+#define PCM990_IDE_IRQ_EDGE IRQT_RISING
+#define PCM990_IDE_PLD_PHYS 0x20000000 /* 16 bit wide */
+#define PCM990_IDE_PLD_BASE 0xee000000
+#define PCM990_IDE_PLD_SIZE (1*1024*1024)
+
+/* visible CPLD (U6) registers */
+#define PCM990_IDE_PLD_REG0 0x1000 /* OFFSET IDE REGISTER 0 */
+#define PCM990_IDE_PM5V 0x0004 /* R System VCC_5V */
+#define PCM990_IDE_STBY 0x0008 /* R System StandBy */
+
+#define PCM990_IDE_PLD_REG1 0x1002 /* OFFSET IDE REGISTER 1 */
+#define PCM990_IDE_IDEMODE 0x0001 /* R TrueIDE Mode */
+#define PCM990_IDE_DMAENA 0x0004 /* RW DMA Enable */
+#define PCM990_IDE_DMA1_0 0x0008 /* RW 1=DREQ1 0=DREQ0 */
+
+#define PCM990_IDE_PLD_REG2 0x1004 /* OFFSET IDE REGISTER 2 */
+#define PCM990_IDE_RESENA 0x0001 /* RW IDE Reset Bit enable */
+#define PCM990_IDE_RES 0x0002 /* RW IDE Reset Bit */
+#define PCM990_IDE_RDY 0x0008 /* RDY */
+
+#define PCM990_IDE_PLD_REG3 0x1006 /* OFFSET IDE REGISTER 3 */
+#define PCM990_IDE_IDEOE 0x0001 /* RW Latch on Databus */
+#define PCM990_IDE_IDEON 0x0002 /* RW Latch on Control Address */
+#define PCM990_IDE_IDEIN 0x0004 /* RW Latch on Interrupt usw. */
+
+#define PCM990_IDE_PLD_REG4 0x1008 /* OFFSET IDE REGISTER 4 */
+#define PCM990_IDE_PWRENA 0x0001 /* RW IDE Power enable */
+#define PCM990_IDE_5V 0x0002 /* R IDE Power 5V */
+#define PCM990_IDE_PWG 0x0008 /* R IDE Power is on */
+
+#define PCM990_IDE_PLD_P2V(x) ((x) - PCM990_IDE_PLD_PHYS + PCM990_IDE_PLD_BASE)
+#define PCM990_IDE_PLD_V2P(x) ((x) - PCM990_IDE_PLD_BASE + PCM990_IDE_PLD_PHYS)
+
+#ifndef __ASSEMBLY__
+# define __PCM990_IDE_PLD_REG(x) \
+ (*((volatile unsigned char *)PCM990_IDE_PLD_P2V(x)))
+#else
+# define __PCM990_IDE_PLD_REG(x) PCM990_IDE_PLD_P2V(x)
+#endif
+
+#define PCM990_IDE0 \
+ __PCM990_IDE_PLD_REG(PCM990_IDE_PLD_PHYS + PCM990_IDE_PLD_REG0)
+#define PCM990_IDE1 \
+ __PCM990_IDE_PLD_REG(PCM990_IDE_PLD_PHYS + PCM990_IDE_PLD_REG1)
+#define PCM990_IDE2 \
+ __PCM990_IDE_PLD_REG(PCM990_IDE_PLD_PHYS + PCM990_IDE_PLD_REG2)
+#define PCM990_IDE3 \
+ __PCM990_IDE_PLD_REG(PCM990_IDE_PLD_PHYS + PCM990_IDE_PLD_REG3)
+#define PCM990_IDE4 \
+ __PCM990_IDE_PLD_REG(PCM990_IDE_PLD_PHYS + PCM990_IDE_PLD_REG4)
+
+/*
+ * Compact Flash
+ */
+#define PCM990_CF_IRQ_GPIO 11
+#define PCM990_CF_IRQ IRQ_GPIO(PCM990_CF_IRQ_GPIO)
+#define PCM990_CF_IRQ_EDGE IRQT_RISING
+
+#define PCM990_CF_CD_GPIO 12
+#define PCM990_CF_CD IRQ_GPIO(PCM990_CF_CD_GPIO)
+#define PCM990_CF_CD_EDGE IRQT_RISING
+
+#define PCM990_CF_PLD_PHYS 0x30000000 /* 16 bit wide */
+#define PCM990_CF_PLD_BASE 0xef000000
+#define PCM990_CF_PLD_SIZE (1*1024*1024)
+#define PCM990_CF_PLD_P2V(x) ((x) - PCM990_CF_PLD_PHYS + PCM990_CF_PLD_BASE)
+#define PCM990_CF_PLD_V2P(x) ((x) - PCM990_CF_PLD_BASE + PCM990_CF_PLD_PHYS)
+
+/* visible CPLD (U6) registers */
+#define PCM990_CF_PLD_REG0 0x1000 /* OFFSET CF REGISTER 0 */
+#define PCM990_CF_REG0_LED 0x0001 /* RW LED on */
+#define PCM990_CF_REG0_BLK 0x0002 /* RW LED flash when access */
+#define PCM990_CF_REG0_PM5V 0x0004 /* R System VCC_5V enable */
+#define PCM990_CF_REG0_STBY 0x0008 /* R System StandBy */
+
+#define PCM990_CF_PLD_REG1 0x1002 /* OFFSET CF REGISTER 1 */
+#define PCM990_CF_REG1_IDEMODE 0x0001 /* RW CF card run as TrueIDE */
+#define PCM990_CF_REG1_CF0 0x0002 /* RW CF card at ADDR 0x28000000 */
+
+#define PCM990_CF_PLD_REG2 0x1004 /* OFFSET CF REGISTER 2 */
+#define PCM990_CF_REG2_RES 0x0002 /* RW CF RESET BIT */
+#define PCM990_CF_REG2_RDYENA 0x0004 /* RW Enable CF_RDY */
+#define PCM990_CF_REG2_RDY 0x0008 /* R CF_RDY auf PWAIT */
+
+#define PCM990_CF_PLD_REG3 0x1006 /* OFFSET CF REGISTER 3 */
+#define PCM990_CF_REG3_CFOE 0x0001 /* RW Latch on Databus */
+#define PCM990_CF_REG3_CFON 0x0002 /* RW Latch on Control Address */
+#define PCM990_CF_REG3_CFIN 0x0004 /* RW Latch on Interrupt usw. */
+#define PCM990_CF_REG3_CFCD 0x0008 /* RW Latch on CD1/2 VS1/2 usw */
+
+#define PCM990_CF_PLD_REG4 0x1008 /* OFFSET CF REGISTER 4 */
+#define PCM990_CF_REG4_PWRENA 0x0001 /* RW CF Power on (CD1/2 = "00") */
+#define PCM990_CF_REG4_5_3V 0x0002 /* RW 1 = 5V CF_VCC 0 = 3 V CF_VCC */
+#define PCM990_CF_REG4_3B 0x0004 /* RW 3.0V Backup from VCC (5_3V=0) */
+#define PCM990_CF_REG4_PWG 0x0008 /* R CF-Power is on */
+
+#define PCM990_CF_PLD_REG5 0x100A /* OFFSET CF REGISTER 5 */
+#define PCM990_CF_REG5_BVD1 0x0001 /* R CF /BVD1 */
+#define PCM990_CF_REG5_BVD2 0x0002 /* R CF /BVD2 */
+#define PCM990_CF_REG5_VS1 0x0004 /* R CF /VS1 */
+#define PCM990_CF_REG5_VS2 0x0008 /* R CF /VS2 */
+
+#define PCM990_CF_PLD_REG6 0x100C /* OFFSET CF REGISTER 6 */
+#define PCM990_CF_REG6_CD1 0x0001 /* R CF Card_Detect1 */
+#define PCM990_CF_REG6_CD2 0x0002 /* R CF Card_Detect2 */
+
+#ifndef __ASSEMBLY__
+# define __PCM990_CF_PLD_REG(x) \
+ (*((volatile unsigned char *)PCM990_CF_PLD_P2V(x)))
+#else
+# define __PCM990_CF_PLD_REG(x) PCM990_CF_PLD_P2V(x)
+#endif
+
+#define PCM990_CF0 __PCM990_CF_PLD_REG(PCM990_CF_PLD_PHYS + PCM990_CF_PLD_REG0)
+#define PCM990_CF1 __PCM990_CF_PLD_REG(PCM990_CF_PLD_PHYS + PCM990_CF_PLD_REG1)
+#define PCM990_CF2 __PCM990_CF_PLD_REG(PCM990_CF_PLD_PHYS + PCM990_CF_PLD_REG2)
+#define PCM990_CF3 __PCM990_CF_PLD_REG(PCM990_CF_PLD_PHYS + PCM990_CF_PLD_REG3)
+#define PCM990_CF4 __PCM990_CF_PLD_REG(PCM990_CF_PLD_PHYS + PCM990_CF_PLD_REG4)
+#define PCM990_CF5 __PCM990_CF_PLD_REG(PCM990_CF_PLD_PHYS + PCM990_CF_PLD_REG5)
+#define PCM990_CF6 __PCM990_CF_PLD_REG(PCM990_CF_PLD_PHYS + PCM990_CF_PLD_REG6)
+
+/*
+ * Wolfson AC97 Touch
+ */
+#define PCM990_AC97_IRQ_GPIO 10
+#define PCM990_AC97_IRQ IRQ_GPIO(PCM990_AC97_IRQ_GPIO)
+#define PCM990_AC97_IRQ_EDGE IRQT_RISING
+
+/*
+ * MMC phyCORE
+ */
+#define PCM990_MMC0_IRQ_GPIO 9
+#define PCM990_MMC0_IRQ IRQ_GPIO(PCM990_MMC0_IRQ_GPIO)
+#define PCM990_MMC0_IRQ_EDGE IRQT_FALLING
+
+/*
+ * USB phyCore
+ */
+#define PCM990_USB_OVERCURRENT (88 | GPIO_ALT_FN_1_IN)
+#define PCM990_USB_PWR_EN (89 | GPIO_ALT_FN_2_OUT)
diff --git a/include/asm-arm/arch-pxa/pxa-regs.h b/include/asm-arm/arch-pxa/pxa-regs.h
index 1bd398da07d..442494d71f1 100644
--- a/include/asm-arm/arch-pxa/pxa-regs.h
+++ b/include/asm-arm/arch-pxa/pxa-regs.h
@@ -1597,176 +1597,10 @@
#define PWER_GPIO15 PWER_GPIO (15) /* GPIO [15] wake-up enable */
#define PWER_RTC 0x80000000 /* RTC alarm wake-up enable */
-
/*
- * SSP Serial Port Registers
- * PXA250, PXA255, PXA26x and PXA27x SSP controllers are all slightly different.
- * PXA255, PXA26x and PXA27x have extra ports, registers and bits.
+ * SSP Serial Port Registers - see include/asm-arm/arch-pxa/regs-ssp.h
*/
- /* Common PXA2xx bits first */
-#define SSCR0_DSS (0x0000000f) /* Data Size Select (mask) */
-#define SSCR0_DataSize(x) ((x) - 1) /* Data Size Select [4..16] */
-#define SSCR0_FRF (0x00000030) /* FRame Format (mask) */
-#define SSCR0_Motorola (0x0 << 4) /* Motorola's Serial Peripheral Interface (SPI) */
-#define SSCR0_TI (0x1 << 4) /* Texas Instruments' Synchronous Serial Protocol (SSP) */
-#define SSCR0_National (0x2 << 4) /* National Microwire */
-#define SSCR0_ECS (1 << 6) /* External clock select */
-#define SSCR0_SSE (1 << 7) /* Synchronous Serial Port Enable */
-#if defined(CONFIG_PXA25x)
-#define SSCR0_SCR (0x0000ff00) /* Serial Clock Rate (mask) */
-#define SSCR0_SerClkDiv(x) ((((x) - 2)/2) << 8) /* Divisor [2..512] */
-#elif defined(CONFIG_PXA27x)
-#define SSCR0_SCR (0x000fff00) /* Serial Clock Rate (mask) */
-#define SSCR0_SerClkDiv(x) (((x) - 1) << 8) /* Divisor [1..4096] */
-#define SSCR0_EDSS (1 << 20) /* Extended data size select */
-#define SSCR0_NCS (1 << 21) /* Network clock select */
-#define SSCR0_RIM (1 << 22) /* Receive FIFO overrrun interrupt mask */
-#define SSCR0_TUM (1 << 23) /* Transmit FIFO underrun interrupt mask */
-#define SSCR0_FRDC (0x07000000) /* Frame rate divider control (mask) */
-#define SSCR0_SlotsPerFrm(x) (((x) - 1) << 24) /* Time slots per frame [1..8] */
-#define SSCR0_ADC (1 << 30) /* Audio clock select */
-#define SSCR0_MOD (1 << 31) /* Mode (normal or network) */
-#endif
-
-#define SSCR1_RIE (1 << 0) /* Receive FIFO Interrupt Enable */
-#define SSCR1_TIE (1 << 1) /* Transmit FIFO Interrupt Enable */
-#define SSCR1_LBM (1 << 2) /* Loop-Back Mode */
-#define SSCR1_SPO (1 << 3) /* Motorola SPI SSPSCLK polarity setting */
-#define SSCR1_SPH (1 << 4) /* Motorola SPI SSPSCLK phase setting */
-#define SSCR1_MWDS (1 << 5) /* Microwire Transmit Data Size */
-#define SSCR1_TFT (0x000003c0) /* Transmit FIFO Threshold (mask) */
-#define SSCR1_TxTresh(x) (((x) - 1) << 6) /* level [1..16] */
-#define SSCR1_RFT (0x00003c00) /* Receive FIFO Threshold (mask) */
-#define SSCR1_RxTresh(x) (((x) - 1) << 10) /* level [1..16] */
-
-#define SSSR_TNF (1 << 2) /* Transmit FIFO Not Full */
-#define SSSR_RNE (1 << 3) /* Receive FIFO Not Empty */
-#define SSSR_BSY (1 << 4) /* SSP Busy */
-#define SSSR_TFS (1 << 5) /* Transmit FIFO Service Request */
-#define SSSR_RFS (1 << 6) /* Receive FIFO Service Request */
-#define SSSR_ROR (1 << 7) /* Receive FIFO Overrun */
-
-#define SSCR0_TIM (1 << 23) /* Transmit FIFO Under Run Interrupt Mask */
-#define SSCR0_RIM (1 << 22) /* Receive FIFO Over Run interrupt Mask */
-#define SSCR0_NCS (1 << 21) /* Network Clock Select */
-#define SSCR0_EDSS (1 << 20) /* Extended Data Size Select */
-
-/* extra bits in PXA255, PXA26x and PXA27x SSP ports */
-#define SSCR0_TISSP (1 << 4) /* TI Sync Serial Protocol */
-#define SSCR0_PSP (3 << 4) /* PSP - Programmable Serial Protocol */
-#define SSCR1_TTELP (1 << 31) /* TXD Tristate Enable Last Phase */
-#define SSCR1_TTE (1 << 30) /* TXD Tristate Enable */
-#define SSCR1_EBCEI (1 << 29) /* Enable Bit Count Error interrupt */
-#define SSCR1_SCFR (1 << 28) /* Slave Clock free Running */
-#define SSCR1_ECRA (1 << 27) /* Enable Clock Request A */
-#define SSCR1_ECRB (1 << 26) /* Enable Clock request B */
-#define SSCR1_SCLKDIR (1 << 25) /* Serial Bit Rate Clock Direction */
-#define SSCR1_SFRMDIR (1 << 24) /* Frame Direction */
-#define SSCR1_RWOT (1 << 23) /* Receive Without Transmit */
-#define SSCR1_TRAIL (1 << 22) /* Trailing Byte */
-#define SSCR1_TSRE (1 << 21) /* Transmit Service Request Enable */
-#define SSCR1_RSRE (1 << 20) /* Receive Service Request Enable */
-#define SSCR1_TINTE (1 << 19) /* Receiver Time-out Interrupt enable */
-#define SSCR1_PINTE (1 << 18) /* Peripheral Trailing Byte Interupt Enable */
-#define SSCR1_STRF (1 << 15) /* Select FIFO or EFWR */
-#define SSCR1_EFWR (1 << 14) /* Enable FIFO Write/Read */
-
-#define SSSR_BCE (1 << 23) /* Bit Count Error */
-#define SSSR_CSS (1 << 22) /* Clock Synchronisation Status */
-#define SSSR_TUR (1 << 21) /* Transmit FIFO Under Run */
-#define SSSR_EOC (1 << 20) /* End Of Chain */
-#define SSSR_TINT (1 << 19) /* Receiver Time-out Interrupt */
-#define SSSR_PINT (1 << 18) /* Peripheral Trailing Byte Interrupt */
-
-#define SSPSP_FSRT (1 << 25) /* Frame Sync Relative Timing */
-#define SSPSP_DMYSTOP(x) ((x) << 23) /* Dummy Stop */
-#define SSPSP_SFRMWDTH(x) ((x) << 16) /* Serial Frame Width */
-#define SSPSP_SFRMDLY(x) ((x) << 9) /* Serial Frame Delay */
-#define SSPSP_DMYSTRT(x) ((x) << 7) /* Dummy Start */
-#define SSPSP_STRTDLY(x) ((x) << 4) /* Start Delay */
-#define SSPSP_ETDS (1 << 3) /* End of Transfer data State */
-#define SSPSP_SFRMP (1 << 2) /* Serial Frame Polarity */
-#define SSPSP_SCMODE(x) ((x) << 0) /* Serial Bit Rate Clock Mode */
-
-#define SSACD_SCDB (1 << 3) /* SSPSYSCLK Divider Bypass */
-#define SSACD_ACPS(x) ((x) << 4) /* Audio clock PLL select */
-#define SSACD_ACDS(x) ((x) << 0) /* Audio clock divider select */
-
-#define SSCR0_P1 __REG(0x41000000) /* SSP Port 1 Control Register 0 */
-#define SSCR1_P1 __REG(0x41000004) /* SSP Port 1 Control Register 1 */
-#define SSSR_P1 __REG(0x41000008) /* SSP Port 1 Status Register */
-#define SSITR_P1 __REG(0x4100000C) /* SSP Port 1 Interrupt Test Register */
-#define SSDR_P1 __REG(0x41000010) /* (Write / Read) SSP Port 1 Data Write Register/SSP Data Read Register */
-
-/* Support existing PXA25x drivers */
-#define SSCR0 SSCR0_P1 /* SSP Control Register 0 */
-#define SSCR1 SSCR1_P1 /* SSP Control Register 1 */
-#define SSSR SSSR_P1 /* SSP Status Register */
-#define SSITR SSITR_P1 /* SSP Interrupt Test Register */
-#define SSDR SSDR_P1 /* (Write / Read) SSP Data Write Register/SSP Data Read Register */
-
-/* PXA27x ports */
-#if defined (CONFIG_PXA27x)
-#define SSTO_P1 __REG(0x41000028) /* SSP Port 1 Time Out Register */
-#define SSPSP_P1 __REG(0x4100002C) /* SSP Port 1 Programmable Serial Protocol */
-#define SSTSA_P1 __REG(0x41000030) /* SSP Port 1 Tx Timeslot Active */
-#define SSRSA_P1 __REG(0x41000034) /* SSP Port 1 Rx Timeslot Active */
-#define SSTSS_P1 __REG(0x41000038) /* SSP Port 1 Timeslot Status */
-#define SSACD_P1 __REG(0x4100003C) /* SSP Port 1 Audio Clock Divider */
-#define SSCR0_P2 __REG(0x41700000) /* SSP Port 2 Control Register 0 */
-#define SSCR1_P2 __REG(0x41700004) /* SSP Port 2 Control Register 1 */
-#define SSSR_P2 __REG(0x41700008) /* SSP Port 2 Status Register */
-#define SSITR_P2 __REG(0x4170000C) /* SSP Port 2 Interrupt Test Register */
-#define SSDR_P2 __REG(0x41700010) /* (Write / Read) SSP Port 2 Data Write Register/SSP Data Read Register */
-#define SSTO_P2 __REG(0x41700028) /* SSP Port 2 Time Out Register */
-#define SSPSP_P2 __REG(0x4170002C) /* SSP Port 2 Programmable Serial Protocol */
-#define SSTSA_P2 __REG(0x41700030) /* SSP Port 2 Tx Timeslot Active */
-#define SSRSA_P2 __REG(0x41700034) /* SSP Port 2 Rx Timeslot Active */
-#define SSTSS_P2 __REG(0x41700038) /* SSP Port 2 Timeslot Status */
-#define SSACD_P2 __REG(0x4170003C) /* SSP Port 2 Audio Clock Divider */
-#define SSCR0_P3 __REG(0x41900000) /* SSP Port 3 Control Register 0 */
-#define SSCR1_P3 __REG(0x41900004) /* SSP Port 3 Control Register 1 */
-#define SSSR_P3 __REG(0x41900008) /* SSP Port 3 Status Register */
-#define SSITR_P3 __REG(0x4190000C) /* SSP Port 3 Interrupt Test Register */
-#define SSDR_P3 __REG(0x41900010) /* (Write / Read) SSP Port 3 Data Write Register/SSP Data Read Register */
-#define SSTO_P3 __REG(0x41900028) /* SSP Port 3 Time Out Register */
-#define SSPSP_P3 __REG(0x4190002C) /* SSP Port 3 Programmable Serial Protocol */
-#define SSTSA_P3 __REG(0x41900030) /* SSP Port 3 Tx Timeslot Active */
-#define SSRSA_P3 __REG(0x41900034) /* SSP Port 3 Rx Timeslot Active */
-#define SSTSS_P3 __REG(0x41900038) /* SSP Port 3 Timeslot Status */
-#define SSACD_P3 __REG(0x4190003C) /* SSP Port 3 Audio Clock Divider */
-#else /* PXA255 (only port 2) and PXA26x ports*/
-#define SSTO_P1 __REG(0x41000028) /* SSP Port 1 Time Out Register */
-#define SSPSP_P1 __REG(0x4100002C) /* SSP Port 1 Programmable Serial Protocol */
-#define SSCR0_P2 __REG(0x41400000) /* SSP Port 2 Control Register 0 */
-#define SSCR1_P2 __REG(0x41400004) /* SSP Port 2 Control Register 1 */
-#define SSSR_P2 __REG(0x41400008) /* SSP Port 2 Status Register */
-#define SSITR_P2 __REG(0x4140000C) /* SSP Port 2 Interrupt Test Register */
-#define SSDR_P2 __REG(0x41400010) /* (Write / Read) SSP Port 2 Data Write Register/SSP Data Read Register */
-#define SSTO_P2 __REG(0x41400028) /* SSP Port 2 Time Out Register */
-#define SSPSP_P2 __REG(0x4140002C) /* SSP Port 2 Programmable Serial Protocol */
-#define SSCR0_P3 __REG(0x41500000) /* SSP Port 3 Control Register 0 */
-#define SSCR1_P3 __REG(0x41500004) /* SSP Port 3 Control Register 1 */
-#define SSSR_P3 __REG(0x41500008) /* SSP Port 3 Status Register */
-#define SSITR_P3 __REG(0x4150000C) /* SSP Port 3 Interrupt Test Register */
-#define SSDR_P3 __REG(0x41500010) /* (Write / Read) SSP Port 3 Data Write Register/SSP Data Read Register */
-#define SSTO_P3 __REG(0x41500028) /* SSP Port 3 Time Out Register */
-#define SSPSP_P3 __REG(0x4150002C) /* SSP Port 3 Programmable Serial Protocol */
-#endif
-
-#define SSCR0_P(x) (*(((x) == 1) ? &SSCR0_P1 : ((x) == 2) ? &SSCR0_P2 : ((x) == 3) ? &SSCR0_P3 : NULL))
-#define SSCR1_P(x) (*(((x) == 1) ? &SSCR1_P1 : ((x) == 2) ? &SSCR1_P2 : ((x) == 3) ? &SSCR1_P3 : NULL))
-#define SSSR_P(x) (*(((x) == 1) ? &SSSR_P1 : ((x) == 2) ? &SSSR_P2 : ((x) == 3) ? &SSSR_P3 : NULL))
-#define SSITR_P(x) (*(((x) == 1) ? &SSITR_P1 : ((x) == 2) ? &SSITR_P2 : ((x) == 3) ? &SSITR_P3 : NULL))
-#define SSDR_P(x) (*(((x) == 1) ? &SSDR_P1 : ((x) == 2) ? &SSDR_P2 : ((x) == 3) ? &SSDR_P3 : NULL))
-#define SSTO_P(x) (*(((x) == 1) ? &SSTO_P1 : ((x) == 2) ? &SSTO_P2 : ((x) == 3) ? &SSTO_P3 : NULL))
-#define SSPSP_P(x) (*(((x) == 1) ? &SSPSP_P1 : ((x) == 2) ? &SSPSP_P2 : ((x) == 3) ? &SSPSP_P3 : NULL))
-#define SSTSA_P(x) (*(((x) == 1) ? &SSTSA_P1 : ((x) == 2) ? &SSTSA_P2 : ((x) == 3) ? &SSTSA_P3 : NULL))
-#define SSRSA_P(x) (*(((x) == 1) ? &SSRSA_P1 : ((x) == 2) ? &SSRSA_P2 : ((x) == 3) ? &SSRSA_P3 : NULL))
-#define SSTSS_P(x) (*(((x) == 1) ? &SSTSS_P1 : ((x) == 2) ? &SSTSS_P2 : ((x) == 3) ? &SSTSS_P3 : NULL))
-#define SSACD_P(x) (*(((x) == 1) ? &SSACD_P1 : ((x) == 2) ? &SSACD_P2 : ((x) == 3) ? &SSACD_P3 : NULL))
-
/*
* MultiMediaCard (MMC) controller - see drivers/mmc/host/pxamci.h
*/
@@ -2014,71 +1848,8 @@
#define LDCMD_PAL (1 << 26) /* instructs DMA to load palette buffer */
-/*
- * Memory controller
- */
-
-#define MDCNFG __REG(0x48000000) /* SDRAM Configuration Register 0 */
-#define MDREFR __REG(0x48000004) /* SDRAM Refresh Control Register */
-#define MSC0 __REG(0x48000008) /* Static Memory Control Register 0 */
-#define MSC1 __REG(0x4800000C) /* Static Memory Control Register 1 */
-#define MSC2 __REG(0x48000010) /* Static Memory Control Register 2 */
-#define MECR __REG(0x48000014) /* Expansion Memory (PCMCIA/Compact Flash) Bus Configuration */
-#define SXLCR __REG(0x48000018) /* LCR value to be written to SDRAM-Timing Synchronous Flash */
-#define SXCNFG __REG(0x4800001C) /* Synchronous Static Memory Control Register */
-#define SXMRS __REG(0x48000024) /* MRS value to be written to Synchronous Flash or SMROM */
-#define MCMEM0 __REG(0x48000028) /* Card interface Common Memory Space Socket 0 Timing */
-#define MCMEM1 __REG(0x4800002C) /* Card interface Common Memory Space Socket 1 Timing */
-#define MCATT0 __REG(0x48000030) /* Card interface Attribute Space Socket 0 Timing Configuration */
-#define MCATT1 __REG(0x48000034) /* Card interface Attribute Space Socket 1 Timing Configuration */
-#define MCIO0 __REG(0x48000038) /* Card interface I/O Space Socket 0 Timing Configuration */
-#define MCIO1 __REG(0x4800003C) /* Card interface I/O Space Socket 1 Timing Configuration */
-#define MDMRS __REG(0x48000040) /* MRS value to be written to SDRAM */
-#define BOOT_DEF __REG(0x48000044) /* Read-Only Boot-Time Register. Contains BOOT_SEL and PKG_SEL */
-
-/*
- * More handy macros for PCMCIA
- *
- * Arg is socket number
- */
-#define MCMEM(s) __REG2(0x48000028, (s)<<2 ) /* Card interface Common Memory Space Socket s Timing */
-#define MCATT(s) __REG2(0x48000030, (s)<<2 ) /* Card interface Attribute Space Socket s Timing Configuration */
-#define MCIO(s) __REG2(0x48000038, (s)<<2 ) /* Card interface I/O Space Socket s Timing Configuration */
-
-/* MECR register defines */
-#define MECR_NOS (1 << 0) /* Number Of Sockets: 0 -> 1 sock, 1 -> 2 sock */
-#define MECR_CIT (1 << 1) /* Card Is There: 0 -> no card, 1 -> card inserted */
-
-#define MDREFR_K0DB4 (1 << 29) /* SDCLK0 Divide by 4 Control/Status */
-#define MDREFR_K2FREE (1 << 25) /* SDRAM Free-Running Control */
-#define MDREFR_K1FREE (1 << 24) /* SDRAM Free-Running Control */
-#define MDREFR_K0FREE (1 << 23) /* SDRAM Free-Running Control */
-#define MDREFR_SLFRSH (1 << 22) /* SDRAM Self-Refresh Control/Status */
-#define MDREFR_APD (1 << 20) /* SDRAM/SSRAM Auto-Power-Down Enable */
-#define MDREFR_K2DB2 (1 << 19) /* SDCLK2 Divide by 2 Control/Status */
-#define MDREFR_K2RUN (1 << 18) /* SDCLK2 Run Control/Status */
-#define MDREFR_K1DB2 (1 << 17) /* SDCLK1 Divide by 2 Control/Status */
-#define MDREFR_K1RUN (1 << 16) /* SDCLK1 Run Control/Status */
-#define MDREFR_E1PIN (1 << 15) /* SDCKE1 Level Control/Status */
-#define MDREFR_K0DB2 (1 << 14) /* SDCLK0 Divide by 2 Control/Status */
-#define MDREFR_K0RUN (1 << 13) /* SDCLK0 Run Control/Status */
-#define MDREFR_E0PIN (1 << 12) /* SDCKE0 Level Control/Status */
-
-
#ifdef CONFIG_PXA27x
-#define ARB_CNTRL __REG(0x48000048) /* Arbiter Control Register */
-
-#define ARB_DMA_SLV_PARK (1<<31) /* Be parked with DMA slave when idle */
-#define ARB_CI_PARK (1<<30) /* Be parked with Camera Interface when idle */
-#define ARB_EX_MEM_PARK (1<<29) /* Be parked with external MEMC when idle */
-#define ARB_INT_MEM_PARK (1<<28) /* Be parked with internal MEMC when idle */
-#define ARB_USB_PARK (1<<27) /* Be parked with USB when idle */
-#define ARB_LCD_PARK (1<<26) /* Be parked with LCD when idle */
-#define ARB_DMA_PARK (1<<25) /* Be parked with DMA when idle */
-#define ARB_CORE_PARK (1<<24) /* Be parked with core when idle */
-#define ARB_LOCK_FLAG (1<<23) /* Only Locking masters gain access to the bus */
-
/*
* Keypad
*/
@@ -2135,74 +1906,6 @@
#define KPAS_SO (0x1 << 31)
#define KPASMKPx_SO (0x1 << 31)
-/*
- * UHC: USB Host Controller (OHCI-like) register definitions
- */
-#define UHC_BASE_PHYS (0x4C000000)
-#define UHCREV __REG(0x4C000000) /* UHC HCI Spec Revision */
-#define UHCHCON __REG(0x4C000004) /* UHC Host Control Register */
-#define UHCCOMS __REG(0x4C000008) /* UHC Command Status Register */
-#define UHCINTS __REG(0x4C00000C) /* UHC Interrupt Status Register */
-#define UHCINTE __REG(0x4C000010) /* UHC Interrupt Enable */
-#define UHCINTD __REG(0x4C000014) /* UHC Interrupt Disable */
-#define UHCHCCA __REG(0x4C000018) /* UHC Host Controller Comm. Area */
-#define UHCPCED __REG(0x4C00001C) /* UHC Period Current Endpt Descr */
-#define UHCCHED __REG(0x4C000020) /* UHC Control Head Endpt Descr */
-#define UHCCCED __REG(0x4C000024) /* UHC Control Current Endpt Descr */
-#define UHCBHED __REG(0x4C000028) /* UHC Bulk Head Endpt Descr */
-#define UHCBCED __REG(0x4C00002C) /* UHC Bulk Current Endpt Descr */
-#define UHCDHEAD __REG(0x4C000030) /* UHC Done Head */
-#define UHCFMI __REG(0x4C000034) /* UHC Frame Interval */
-#define UHCFMR __REG(0x4C000038) /* UHC Frame Remaining */
-#define UHCFMN __REG(0x4C00003C) /* UHC Frame Number */
-#define UHCPERS __REG(0x4C000040) /* UHC Periodic Start */
-#define UHCLS __REG(0x4C000044) /* UHC Low Speed Threshold */
-
-#define UHCRHDA __REG(0x4C000048) /* UHC Root Hub Descriptor A */
-#define UHCRHDA_NOCP (1 << 12) /* No over current protection */
-
-#define UHCRHDB __REG(0x4C00004C) /* UHC Root Hub Descriptor B */
-#define UHCRHS __REG(0x4C000050) /* UHC Root Hub Status */
-#define UHCRHPS1 __REG(0x4C000054) /* UHC Root Hub Port 1 Status */
-#define UHCRHPS2 __REG(0x4C000058) /* UHC Root Hub Port 2 Status */
-#define UHCRHPS3 __REG(0x4C00005C) /* UHC Root Hub Port 3 Status */
-
-#define UHCSTAT __REG(0x4C000060) /* UHC Status Register */
-#define UHCSTAT_UPS3 (1 << 16) /* USB Power Sense Port3 */
-#define UHCSTAT_SBMAI (1 << 15) /* System Bus Master Abort Interrupt*/
-#define UHCSTAT_SBTAI (1 << 14) /* System Bus Target Abort Interrupt*/
-#define UHCSTAT_UPRI (1 << 13) /* USB Port Resume Interrupt */
-#define UHCSTAT_UPS2 (1 << 12) /* USB Power Sense Port 2 */
-#define UHCSTAT_UPS1 (1 << 11) /* USB Power Sense Port 1 */
-#define UHCSTAT_HTA (1 << 10) /* HCI Target Abort */
-#define UHCSTAT_HBA (1 << 8) /* HCI Buffer Active */
-#define UHCSTAT_RWUE (1 << 7) /* HCI Remote Wake Up Event */
-
-#define UHCHR __REG(0x4C000064) /* UHC Reset Register */
-#define UHCHR_SSEP3 (1 << 11) /* Sleep Standby Enable for Port3 */
-#define UHCHR_SSEP2 (1 << 10) /* Sleep Standby Enable for Port2 */
-#define UHCHR_SSEP1 (1 << 9) /* Sleep Standby Enable for Port1 */
-#define UHCHR_PCPL (1 << 7) /* Power control polarity low */
-#define UHCHR_PSPL (1 << 6) /* Power sense polarity low */
-#define UHCHR_SSE (1 << 5) /* Sleep Standby Enable */
-#define UHCHR_UIT (1 << 4) /* USB Interrupt Test */
-#define UHCHR_SSDC (1 << 3) /* Simulation Scale Down Clock */
-#define UHCHR_CGR (1 << 2) /* Clock Generation Reset */
-#define UHCHR_FHR (1 << 1) /* Force Host Controller Reset */
-#define UHCHR_FSBIR (1 << 0) /* Force System Bus Iface Reset */
-
-#define UHCHIE __REG(0x4C000068) /* UHC Interrupt Enable Register*/
-#define UHCHIE_UPS3IE (1 << 14) /* Power Sense Port3 IntEn */
-#define UHCHIE_UPRIE (1 << 13) /* Port Resume IntEn */
-#define UHCHIE_UPS2IE (1 << 12) /* Power Sense Port2 IntEn */
-#define UHCHIE_UPS1IE (1 << 11) /* Power Sense Port1 IntEn */
-#define UHCHIE_TAIE (1 << 10) /* HCI Interface Transfer Abort
- Interrupt Enable*/
-#define UHCHIE_HBAIE (1 << 8) /* HCI Buffer Active IntEn */
-#define UHCHIE_RWIE (1 << 7) /* Remote Wake-up IntEn */
-
-#define UHCHIT __REG(0x4C00006C) /* UHC Interrupt Test register */
-
/* Camera Interface */
#define CICR0 __REG(0x50000000)
#define CICR1 __REG(0x50000004)
@@ -2350,6 +2053,77 @@
#endif
+#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
+/*
+ * UHC: USB Host Controller (OHCI-like) register definitions
+ */
+#define UHC_BASE_PHYS (0x4C000000)
+#define UHCREV __REG(0x4C000000) /* UHC HCI Spec Revision */
+#define UHCHCON __REG(0x4C000004) /* UHC Host Control Register */
+#define UHCCOMS __REG(0x4C000008) /* UHC Command Status Register */
+#define UHCINTS __REG(0x4C00000C) /* UHC Interrupt Status Register */
+#define UHCINTE __REG(0x4C000010) /* UHC Interrupt Enable */
+#define UHCINTD __REG(0x4C000014) /* UHC Interrupt Disable */
+#define UHCHCCA __REG(0x4C000018) /* UHC Host Controller Comm. Area */
+#define UHCPCED __REG(0x4C00001C) /* UHC Period Current Endpt Descr */
+#define UHCCHED __REG(0x4C000020) /* UHC Control Head Endpt Descr */
+#define UHCCCED __REG(0x4C000024) /* UHC Control Current Endpt Descr */
+#define UHCBHED __REG(0x4C000028) /* UHC Bulk Head Endpt Descr */
+#define UHCBCED __REG(0x4C00002C) /* UHC Bulk Current Endpt Descr */
+#define UHCDHEAD __REG(0x4C000030) /* UHC Done Head */
+#define UHCFMI __REG(0x4C000034) /* UHC Frame Interval */
+#define UHCFMR __REG(0x4C000038) /* UHC Frame Remaining */
+#define UHCFMN __REG(0x4C00003C) /* UHC Frame Number */
+#define UHCPERS __REG(0x4C000040) /* UHC Periodic Start */
+#define UHCLS __REG(0x4C000044) /* UHC Low Speed Threshold */
+
+#define UHCRHDA __REG(0x4C000048) /* UHC Root Hub Descriptor A */
+#define UHCRHDA_NOCP (1 << 12) /* No over current protection */
+
+#define UHCRHDB __REG(0x4C00004C) /* UHC Root Hub Descriptor B */
+#define UHCRHS __REG(0x4C000050) /* UHC Root Hub Status */
+#define UHCRHPS1 __REG(0x4C000054) /* UHC Root Hub Port 1 Status */
+#define UHCRHPS2 __REG(0x4C000058) /* UHC Root Hub Port 2 Status */
+#define UHCRHPS3 __REG(0x4C00005C) /* UHC Root Hub Port 3 Status */
+
+#define UHCSTAT __REG(0x4C000060) /* UHC Status Register */
+#define UHCSTAT_UPS3 (1 << 16) /* USB Power Sense Port3 */
+#define UHCSTAT_SBMAI (1 << 15) /* System Bus Master Abort Interrupt*/
+#define UHCSTAT_SBTAI (1 << 14) /* System Bus Target Abort Interrupt*/
+#define UHCSTAT_UPRI (1 << 13) /* USB Port Resume Interrupt */
+#define UHCSTAT_UPS2 (1 << 12) /* USB Power Sense Port 2 */
+#define UHCSTAT_UPS1 (1 << 11) /* USB Power Sense Port 1 */
+#define UHCSTAT_HTA (1 << 10) /* HCI Target Abort */
+#define UHCSTAT_HBA (1 << 8) /* HCI Buffer Active */
+#define UHCSTAT_RWUE (1 << 7) /* HCI Remote Wake Up Event */
+
+#define UHCHR __REG(0x4C000064) /* UHC Reset Register */
+#define UHCHR_SSEP3 (1 << 11) /* Sleep Standby Enable for Port3 */
+#define UHCHR_SSEP2 (1 << 10) /* Sleep Standby Enable for Port2 */
+#define UHCHR_SSEP1 (1 << 9) /* Sleep Standby Enable for Port1 */
+#define UHCHR_PCPL (1 << 7) /* Power control polarity low */
+#define UHCHR_PSPL (1 << 6) /* Power sense polarity low */
+#define UHCHR_SSE (1 << 5) /* Sleep Standby Enable */
+#define UHCHR_UIT (1 << 4) /* USB Interrupt Test */
+#define UHCHR_SSDC (1 << 3) /* Simulation Scale Down Clock */
+#define UHCHR_CGR (1 << 2) /* Clock Generation Reset */
+#define UHCHR_FHR (1 << 1) /* Force Host Controller Reset */
+#define UHCHR_FSBIR (1 << 0) /* Force System Bus Iface Reset */
+
+#define UHCHIE __REG(0x4C000068) /* UHC Interrupt Enable Register*/
+#define UHCHIE_UPS3IE (1 << 14) /* Power Sense Port3 IntEn */
+#define UHCHIE_UPRIE (1 << 13) /* Port Resume IntEn */
+#define UHCHIE_UPS2IE (1 << 12) /* Power Sense Port2 IntEn */
+#define UHCHIE_UPS1IE (1 << 11) /* Power Sense Port1 IntEn */
+#define UHCHIE_TAIE (1 << 10) /* HCI Interface Transfer Abort
+ Interrupt Enable*/
+#define UHCHIE_HBAIE (1 << 8) /* HCI Buffer Active IntEn */
+#define UHCHIE_RWIE (1 << 7) /* Remote Wake-up IntEn */
+
+#define UHCHIT __REG(0x4C00006C) /* UHC Interrupt Test register */
+
+#endif /* CONFIG_PXA27x || CONFIG_PXA3xx */
+
/* PWRMODE register M field values */
#define PWRMODE_IDLE 0x1
diff --git a/include/asm-arm/arch-pxa/pxa2xx-regs.h b/include/asm-arm/arch-pxa/pxa2xx-regs.h
new file mode 100644
index 00000000000..9553b54fa5b
--- /dev/null
+++ b/include/asm-arm/arch-pxa/pxa2xx-regs.h
@@ -0,0 +1,84 @@
+/*
+ * linux/include/asm-arm/arch-pxa/pxa2xx-regs.h
+ *
+ * Taken from pxa-regs.h by Russell King
+ *
+ * Author: Nicolas Pitre
+ * Copyright: MontaVista Software Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __PXA2XX_REGS_H
+#define __PXA2XX_REGS_H
+
+/*
+ * Memory controller
+ */
+
+#define MDCNFG __REG(0x48000000) /* SDRAM Configuration Register 0 */
+#define MDREFR __REG(0x48000004) /* SDRAM Refresh Control Register */
+#define MSC0 __REG(0x48000008) /* Static Memory Control Register 0 */
+#define MSC1 __REG(0x4800000C) /* Static Memory Control Register 1 */
+#define MSC2 __REG(0x48000010) /* Static Memory Control Register 2 */
+#define MECR __REG(0x48000014) /* Expansion Memory (PCMCIA/Compact Flash) Bus Configuration */
+#define SXLCR __REG(0x48000018) /* LCR value to be written to SDRAM-Timing Synchronous Flash */
+#define SXCNFG __REG(0x4800001C) /* Synchronous Static Memory Control Register */
+#define SXMRS __REG(0x48000024) /* MRS value to be written to Synchronous Flash or SMROM */
+#define MCMEM0 __REG(0x48000028) /* Card interface Common Memory Space Socket 0 Timing */
+#define MCMEM1 __REG(0x4800002C) /* Card interface Common Memory Space Socket 1 Timing */
+#define MCATT0 __REG(0x48000030) /* Card interface Attribute Space Socket 0 Timing Configuration */
+#define MCATT1 __REG(0x48000034) /* Card interface Attribute Space Socket 1 Timing Configuration */
+#define MCIO0 __REG(0x48000038) /* Card interface I/O Space Socket 0 Timing Configuration */
+#define MCIO1 __REG(0x4800003C) /* Card interface I/O Space Socket 1 Timing Configuration */
+#define MDMRS __REG(0x48000040) /* MRS value to be written to SDRAM */
+#define BOOT_DEF __REG(0x48000044) /* Read-Only Boot-Time Register. Contains BOOT_SEL and PKG_SEL */
+
+/*
+ * More handy macros for PCMCIA
+ *
+ * Arg is socket number
+ */
+#define MCMEM(s) __REG2(0x48000028, (s)<<2 ) /* Card interface Common Memory Space Socket s Timing */
+#define MCATT(s) __REG2(0x48000030, (s)<<2 ) /* Card interface Attribute Space Socket s Timing Configuration */
+#define MCIO(s) __REG2(0x48000038, (s)<<2 ) /* Card interface I/O Space Socket s Timing Configuration */
+
+/* MECR register defines */
+#define MECR_NOS (1 << 0) /* Number Of Sockets: 0 -> 1 sock, 1 -> 2 sock */
+#define MECR_CIT (1 << 1) /* Card Is There: 0 -> no card, 1 -> card inserted */
+
+#define MDREFR_K0DB4 (1 << 29) /* SDCLK0 Divide by 4 Control/Status */
+#define MDREFR_K2FREE (1 << 25) /* SDRAM Free-Running Control */
+#define MDREFR_K1FREE (1 << 24) /* SDRAM Free-Running Control */
+#define MDREFR_K0FREE (1 << 23) /* SDRAM Free-Running Control */
+#define MDREFR_SLFRSH (1 << 22) /* SDRAM Self-Refresh Control/Status */
+#define MDREFR_APD (1 << 20) /* SDRAM/SSRAM Auto-Power-Down Enable */
+#define MDREFR_K2DB2 (1 << 19) /* SDCLK2 Divide by 2 Control/Status */
+#define MDREFR_K2RUN (1 << 18) /* SDCLK2 Run Control/Status */
+#define MDREFR_K1DB2 (1 << 17) /* SDCLK1 Divide by 2 Control/Status */
+#define MDREFR_K1RUN (1 << 16) /* SDCLK1 Run Control/Status */
+#define MDREFR_E1PIN (1 << 15) /* SDCKE1 Level Control/Status */
+#define MDREFR_K0DB2 (1 << 14) /* SDCLK0 Divide by 2 Control/Status */
+#define MDREFR_K0RUN (1 << 13) /* SDCLK0 Run Control/Status */
+#define MDREFR_E0PIN (1 << 12) /* SDCKE0 Level Control/Status */
+
+
+#ifdef CONFIG_PXA27x
+
+#define ARB_CNTRL __REG(0x48000048) /* Arbiter Control Register */
+
+#define ARB_DMA_SLV_PARK (1<<31) /* Be parked with DMA slave when idle */
+#define ARB_CI_PARK (1<<30) /* Be parked with Camera Interface when idle */
+#define ARB_EX_MEM_PARK (1<<29) /* Be parked with external MEMC when idle */
+#define ARB_INT_MEM_PARK (1<<28) /* Be parked with internal MEMC when idle */
+#define ARB_USB_PARK (1<<27) /* Be parked with USB when idle */
+#define ARB_LCD_PARK (1<<26) /* Be parked with LCD when idle */
+#define ARB_DMA_PARK (1<<25) /* Be parked with DMA when idle */
+#define ARB_CORE_PARK (1<<24) /* Be parked with core when idle */
+#define ARB_LOCK_FLAG (1<<23) /* Only Locking masters gain access to the bus */
+
+#endif
+
+#endif
diff --git a/include/asm-arm/arch-pxa/pxa2xx_spi.h b/include/asm-arm/arch-pxa/pxa2xx_spi.h
index acc7ec7a84a..3459fb26ce9 100644
--- a/include/asm-arm/arch-pxa/pxa2xx_spi.h
+++ b/include/asm-arm/arch-pxa/pxa2xx_spi.h
@@ -22,32 +22,8 @@
#define PXA2XX_CS_ASSERT (0x01)
#define PXA2XX_CS_DEASSERT (0x02)
-#if defined(CONFIG_PXA25x)
-#define CLOCK_SPEED_HZ 3686400
-#define SSP1_SerClkDiv(x) (((CLOCK_SPEED_HZ/2/(x+1))<<8)&0x0000ff00)
-#define SSP2_SerClkDiv(x) (((CLOCK_SPEED_HZ/(x+1))<<8)&0x000fff00)
-#define SSP3_SerClkDiv(x) (((CLOCK_SPEED_HZ/(x+1))<<8)&0x000fff00)
-#elif defined(CONFIG_PXA27x)
-#define CLOCK_SPEED_HZ 13000000
-#define SSP1_SerClkDiv(x) (((CLOCK_SPEED_HZ/(x+1))<<8)&0x000fff00)
-#define SSP2_SerClkDiv(x) (((CLOCK_SPEED_HZ/(x+1))<<8)&0x000fff00)
-#define SSP3_SerClkDiv(x) (((CLOCK_SPEED_HZ/(x+1))<<8)&0x000fff00)
-#endif
-
-#define SSP1_VIRT ((void *)(io_p2v(__PREG(SSCR0_P(1)))))
-#define SSP2_VIRT ((void *)(io_p2v(__PREG(SSCR0_P(2)))))
-#define SSP3_VIRT ((void *)(io_p2v(__PREG(SSCR0_P(3)))))
-
-enum pxa_ssp_type {
- SSP_UNDEFINED = 0,
- PXA25x_SSP, /* pxa 210, 250, 255, 26x */
- PXA25x_NSSP, /* pxa 255, 26x (including ASSP) */
- PXA27x_SSP,
-};
-
/* device.platform_data for SSP controller devices */
struct pxa2xx_spi_master {
- enum pxa_ssp_type ssp_type;
u32 clock_enable;
u16 num_chipselect;
u8 enable_dma;
diff --git a/include/asm-arm/arch-pxa/pxa3xx-regs.h b/include/asm-arm/arch-pxa/pxa3xx-regs.h
index 3900a0ca0bc..66d54119757 100644
--- a/include/asm-arm/arch-pxa/pxa3xx-regs.h
+++ b/include/asm-arm/arch-pxa/pxa3xx-regs.h
@@ -14,6 +14,92 @@
#define __ASM_ARCH_PXA3XX_REGS_H
/*
+ * Slave Power Managment Unit
+ */
+#define ASCR __REG(0x40f40000) /* Application Subsystem Power Status/Configuration */
+#define ARSR __REG(0x40f40004) /* Application Subsystem Reset Status */
+#define AD3ER __REG(0x40f40008) /* Application Subsystem Wake-Up from D3 Enable */
+#define AD3SR __REG(0x40f4000c) /* Application Subsystem Wake-Up from D3 Status */
+#define AD2D0ER __REG(0x40f40010) /* Application Subsystem Wake-Up from D2 to D0 Enable */
+#define AD2D0SR __REG(0x40f40014) /* Application Subsystem Wake-Up from D2 to D0 Status */
+#define AD2D1ER __REG(0x40f40018) /* Application Subsystem Wake-Up from D2 to D1 Enable */
+#define AD2D1SR __REG(0x40f4001c) /* Application Subsystem Wake-Up from D2 to D1 Status */
+#define AD1D0ER __REG(0x40f40020) /* Application Subsystem Wake-Up from D1 to D0 Enable */
+#define AD1D0SR __REG(0x40f40024) /* Application Subsystem Wake-Up from D1 to D0 Status */
+#define AGENP __REG(0x40f4002c) /* Application Subsystem General Purpose */
+#define AD3R __REG(0x40f40030) /* Application Subsystem D3 Configuration */
+#define AD2R __REG(0x40f40034) /* Application Subsystem D2 Configuration */
+#define AD1R __REG(0x40f40038) /* Application Subsystem D1 Configuration */
+
+/*
+ * Application Subsystem Configuration bits.
+ */
+#define ASCR_RDH (1 << 31)
+#define ASCR_D1S (1 << 2)
+#define ASCR_D2S (1 << 1)
+#define ASCR_D3S (1 << 0)
+
+/*
+ * Application Reset Status bits.
+ */
+#define ARSR_GPR (1 << 3)
+#define ARSR_LPMR (1 << 2)
+#define ARSR_WDT (1 << 1)
+#define ARSR_HWR (1 << 0)
+
+/*
+ * Application Subsystem Wake-Up bits.
+ */
+#define ADXER_WRTC (1 << 31) /* RTC */
+#define ADXER_WOST (1 << 30) /* OS Timer */
+#define ADXER_WTSI (1 << 29) /* Touchscreen */
+#define ADXER_WUSBH (1 << 28) /* USB host */
+#define ADXER_WUSB2 (1 << 26) /* USB client 2.0 */
+#define ADXER_WMSL0 (1 << 24) /* MSL port 0*/
+#define ADXER_WDMUX3 (1 << 23) /* USB EDMUX3 */
+#define ADXER_WDMUX2 (1 << 22) /* USB EDMUX2 */
+#define ADXER_WKP (1 << 21) /* Keypad */
+#define ADXER_WUSIM1 (1 << 20) /* USIM Port 1 */
+#define ADXER_WUSIM0 (1 << 19) /* USIM Port 0 */
+#define ADXER_WOTG (1 << 16) /* USBOTG input */
+#define ADXER_MFP_WFLASH (1 << 15) /* MFP: Data flash busy */
+#define ADXER_MFP_GEN12 (1 << 14) /* MFP: MMC3/GPIO/OST inputs */
+#define ADXER_MFP_WMMC2 (1 << 13) /* MFP: MMC2 */
+#define ADXER_MFP_WMMC1 (1 << 12) /* MFP: MMC1 */
+#define ADXER_MFP_WI2C (1 << 11) /* MFP: I2C */
+#define ADXER_MFP_WSSP4 (1 << 10) /* MFP: SSP4 */
+#define ADXER_MFP_WSSP3 (1 << 9) /* MFP: SSP3 */
+#define ADXER_MFP_WMAXTRIX (1 << 8) /* MFP: matrix keypad */
+#define ADXER_MFP_WUART3 (1 << 7) /* MFP: UART3 */
+#define ADXER_MFP_WUART2 (1 << 6) /* MFP: UART2 */
+#define ADXER_MFP_WUART1 (1 << 5) /* MFP: UART1 */
+#define ADXER_MFP_WSSP2 (1 << 4) /* MFP: SSP2 */
+#define ADXER_MFP_WSSP1 (1 << 3) /* MFP: SSP1 */
+#define ADXER_MFP_WAC97 (1 << 2) /* MFP: AC97 */
+#define ADXER_WEXTWAKE1 (1 << 1) /* External Wake 1 */
+#define ADXER_WEXTWAKE0 (1 << 0) /* External Wake 0 */
+
+/*
+ * AD3R/AD2R/AD1R bits. R2-R5 are only defined for PXA320.
+ */
+#define ADXR_L2 (1 << 8)
+#define ADXR_R5 (1 << 5)
+#define ADXR_R4 (1 << 4)
+#define ADXR_R3 (1 << 3)
+#define ADXR_R2 (1 << 2)
+#define ADXR_R1 (1 << 1)
+#define ADXR_R0 (1 << 0)
+
+/*
+ * Values for PWRMODE CP15 register
+ */
+#define PXA3xx_PM_S3D4C4 0x07 /* aka deep sleep */
+#define PXA3xx_PM_S2D3C4 0x06 /* aka sleep */
+#define PXA3xx_PM_S0D2C2 0x03 /* aka standby */
+#define PXA3xx_PM_S0D1C2 0x02 /* aka LCD refresh */
+#define PXA3xx_PM_S0D0C1 0x01
+
+/*
* Application Subsystem Clock
*/
#define ACCR __REG(0x41340000) /* Application Subsystem Clock Configuration Register */
diff --git a/include/asm-arm/arch-pxa/regs-ssp.h b/include/asm-arm/arch-pxa/regs-ssp.h
new file mode 100644
index 00000000000..991cb688db7
--- /dev/null
+++ b/include/asm-arm/arch-pxa/regs-ssp.h
@@ -0,0 +1,112 @@
+#ifndef __ASM_ARCH_REGS_SSP_H
+#define __ASM_ARCH_REGS_SSP_H
+
+/*
+ * SSP Serial Port Registers
+ * PXA250, PXA255, PXA26x and PXA27x SSP controllers are all slightly different.
+ * PXA255, PXA26x and PXA27x have extra ports, registers and bits.
+ */
+
+#define SSCR0 (0x00) /* SSP Control Register 0 */
+#define SSCR1 (0x04) /* SSP Control Register 1 */
+#define SSSR (0x08) /* SSP Status Register */
+#define SSITR (0x0C) /* SSP Interrupt Test Register */
+#define SSDR (0x10) /* SSP Data Write/Data Read Register */
+
+#define SSTO (0x28) /* SSP Time Out Register */
+#define SSPSP (0x2C) /* SSP Programmable Serial Protocol */
+#define SSTSA (0x30) /* SSP Tx Timeslot Active */
+#define SSRSA (0x34) /* SSP Rx Timeslot Active */
+#define SSTSS (0x38) /* SSP Timeslot Status */
+#define SSACD (0x3C) /* SSP Audio Clock Divider */
+
+/* Common PXA2xx bits first */
+#define SSCR0_DSS (0x0000000f) /* Data Size Select (mask) */
+#define SSCR0_DataSize(x) ((x) - 1) /* Data Size Select [4..16] */
+#define SSCR0_FRF (0x00000030) /* FRame Format (mask) */
+#define SSCR0_Motorola (0x0 << 4) /* Motorola's Serial Peripheral Interface (SPI) */
+#define SSCR0_TI (0x1 << 4) /* Texas Instruments' Synchronous Serial Protocol (SSP) */
+#define SSCR0_National (0x2 << 4) /* National Microwire */
+#define SSCR0_ECS (1 << 6) /* External clock select */
+#define SSCR0_SSE (1 << 7) /* Synchronous Serial Port Enable */
+#if defined(CONFIG_PXA25x)
+#define SSCR0_SCR (0x0000ff00) /* Serial Clock Rate (mask) */
+#define SSCR0_SerClkDiv(x) ((((x) - 2)/2) << 8) /* Divisor [2..512] */
+#elif defined(CONFIG_PXA27x)
+#define SSCR0_SCR (0x000fff00) /* Serial Clock Rate (mask) */
+#define SSCR0_SerClkDiv(x) (((x) - 1) << 8) /* Divisor [1..4096] */
+#define SSCR0_EDSS (1 << 20) /* Extended data size select */
+#define SSCR0_NCS (1 << 21) /* Network clock select */
+#define SSCR0_RIM (1 << 22) /* Receive FIFO overrrun interrupt mask */
+#define SSCR0_TUM (1 << 23) /* Transmit FIFO underrun interrupt mask */
+#define SSCR0_FRDC (0x07000000) /* Frame rate divider control (mask) */
+#define SSCR0_SlotsPerFrm(x) (((x) - 1) << 24) /* Time slots per frame [1..8] */
+#define SSCR0_ADC (1 << 30) /* Audio clock select */
+#define SSCR0_MOD (1 << 31) /* Mode (normal or network) */
+#endif
+
+#define SSCR1_RIE (1 << 0) /* Receive FIFO Interrupt Enable */
+#define SSCR1_TIE (1 << 1) /* Transmit FIFO Interrupt Enable */
+#define SSCR1_LBM (1 << 2) /* Loop-Back Mode */
+#define SSCR1_SPO (1 << 3) /* Motorola SPI SSPSCLK polarity setting */
+#define SSCR1_SPH (1 << 4) /* Motorola SPI SSPSCLK phase setting */
+#define SSCR1_MWDS (1 << 5) /* Microwire Transmit Data Size */
+#define SSCR1_TFT (0x000003c0) /* Transmit FIFO Threshold (mask) */
+#define SSCR1_TxTresh(x) (((x) - 1) << 6) /* level [1..16] */
+#define SSCR1_RFT (0x00003c00) /* Receive FIFO Threshold (mask) */
+#define SSCR1_RxTresh(x) (((x) - 1) << 10) /* level [1..16] */
+
+#define SSSR_TNF (1 << 2) /* Transmit FIFO Not Full */
+#define SSSR_RNE (1 << 3) /* Receive FIFO Not Empty */
+#define SSSR_BSY (1 << 4) /* SSP Busy */
+#define SSSR_TFS (1 << 5) /* Transmit FIFO Service Request */
+#define SSSR_RFS (1 << 6) /* Receive FIFO Service Request */
+#define SSSR_ROR (1 << 7) /* Receive FIFO Overrun */
+
+#define SSCR0_TIM (1 << 23) /* Transmit FIFO Under Run Interrupt Mask */
+#define SSCR0_RIM (1 << 22) /* Receive FIFO Over Run interrupt Mask */
+#define SSCR0_NCS (1 << 21) /* Network Clock Select */
+#define SSCR0_EDSS (1 << 20) /* Extended Data Size Select */
+
+/* extra bits in PXA255, PXA26x and PXA27x SSP ports */
+#define SSCR0_TISSP (1 << 4) /* TI Sync Serial Protocol */
+#define SSCR0_PSP (3 << 4) /* PSP - Programmable Serial Protocol */
+#define SSCR1_TTELP (1 << 31) /* TXD Tristate Enable Last Phase */
+#define SSCR1_TTE (1 << 30) /* TXD Tristate Enable */
+#define SSCR1_EBCEI (1 << 29) /* Enable Bit Count Error interrupt */
+#define SSCR1_SCFR (1 << 28) /* Slave Clock free Running */
+#define SSCR1_ECRA (1 << 27) /* Enable Clock Request A */
+#define SSCR1_ECRB (1 << 26) /* Enable Clock request B */
+#define SSCR1_SCLKDIR (1 << 25) /* Serial Bit Rate Clock Direction */
+#define SSCR1_SFRMDIR (1 << 24) /* Frame Direction */
+#define SSCR1_RWOT (1 << 23) /* Receive Without Transmit */
+#define SSCR1_TRAIL (1 << 22) /* Trailing Byte */
+#define SSCR1_TSRE (1 << 21) /* Transmit Service Request Enable */
+#define SSCR1_RSRE (1 << 20) /* Receive Service Request Enable */
+#define SSCR1_TINTE (1 << 19) /* Receiver Time-out Interrupt enable */
+#define SSCR1_PINTE (1 << 18) /* Peripheral Trailing Byte Interupt Enable */
+#define SSCR1_STRF (1 << 15) /* Select FIFO or EFWR */
+#define SSCR1_EFWR (1 << 14) /* Enable FIFO Write/Read */
+
+#define SSSR_BCE (1 << 23) /* Bit Count Error */
+#define SSSR_CSS (1 << 22) /* Clock Synchronisation Status */
+#define SSSR_TUR (1 << 21) /* Transmit FIFO Under Run */
+#define SSSR_EOC (1 << 20) /* End Of Chain */
+#define SSSR_TINT (1 << 19) /* Receiver Time-out Interrupt */
+#define SSSR_PINT (1 << 18) /* Peripheral Trailing Byte Interrupt */
+
+#define SSPSP_FSRT (1 << 25) /* Frame Sync Relative Timing */
+#define SSPSP_DMYSTOP(x) ((x) << 23) /* Dummy Stop */
+#define SSPSP_SFRMWDTH(x) ((x) << 16) /* Serial Frame Width */
+#define SSPSP_SFRMDLY(x) ((x) << 9) /* Serial Frame Delay */
+#define SSPSP_DMYSTRT(x) ((x) << 7) /* Dummy Start */
+#define SSPSP_STRTDLY(x) ((x) << 4) /* Start Delay */
+#define SSPSP_ETDS (1 << 3) /* End of Transfer data State */
+#define SSPSP_SFRMP (1 << 2) /* Serial Frame Polarity */
+#define SSPSP_SCMODE(x) ((x) << 0) /* Serial Bit Rate Clock Mode */
+
+#define SSACD_SCDB (1 << 3) /* SSPSYSCLK Divider Bypass */
+#define SSACD_ACPS(x) ((x) << 4) /* Audio clock PLL select */
+#define SSACD_ACDS(x) ((x) << 0) /* Audio clock divider select */
+
+#endif /* __ASM_ARCH_REGS_SSP_H */
diff --git a/include/asm-arm/arch-pxa/sharpsl.h b/include/asm-arm/arch-pxa/sharpsl.h
index 2b0fe773213..3b1d4a72d4d 100644
--- a/include/asm-arm/arch-pxa/sharpsl.h
+++ b/include/asm-arm/arch-pxa/sharpsl.h
@@ -16,7 +16,7 @@ int corgi_ssp_max1111_get(unsigned long data);
*/
struct corgits_machinfo {
- unsigned long (*get_hsync_len)(void);
+ unsigned long (*get_hsync_invperiod)(void);
void (*put_hsync)(void);
void (*wait_hsync)(void);
};
diff --git a/include/asm-arm/arch-pxa/spitz.h b/include/asm-arm/arch-pxa/spitz.h
index 4953dd324d4..bd14365f7ed 100644
--- a/include/asm-arm/arch-pxa/spitz.h
+++ b/include/asm-arm/arch-pxa/spitz.h
@@ -156,5 +156,3 @@ extern struct platform_device spitzscoop_device;
extern struct platform_device spitzscoop2_device;
extern struct platform_device spitzssp_device;
extern struct sharpsl_charger_machinfo spitz_pm_machinfo;
-
-extern void spitz_lcd_power(int on, struct fb_var_screeninfo *var);
diff --git a/include/asm-arm/arch-pxa/ssp.h b/include/asm-arm/arch-pxa/ssp.h
index ea200551a75..a012882c9ee 100644
--- a/include/asm-arm/arch-pxa/ssp.h
+++ b/include/asm-arm/arch-pxa/ssp.h
@@ -13,10 +13,37 @@
* PXA255 SSP, NSSP
* PXA26x SSP, NSSP, ASSP
* PXA27x SSP1, SSP2, SSP3
+ * PXA3xx SSP1, SSP2, SSP3, SSP4
*/
-#ifndef SSP_H
-#define SSP_H
+#ifndef __ASM_ARCH_SSP_H
+#define __ASM_ARCH_SSP_H
+
+#include <linux/list.h>
+
+enum pxa_ssp_type {
+ SSP_UNDEFINED = 0,
+ PXA25x_SSP, /* pxa 210, 250, 255, 26x */
+ PXA25x_NSSP, /* pxa 255, 26x (including ASSP) */
+ PXA27x_SSP,
+};
+
+struct ssp_device {
+ struct platform_device *pdev;
+ struct list_head node;
+
+ struct clk *clk;
+ void __iomem *mmio_base;
+ unsigned long phys_base;
+
+ const char *label;
+ int port_id;
+ int type;
+ int use_count;
+ int irq;
+ int drcmr_rx;
+ int drcmr_tx;
+};
/*
* SSP initialisation flags
@@ -31,6 +58,7 @@ struct ssp_state {
};
struct ssp_dev {
+ struct ssp_device *ssp;
u32 port;
u32 mode;
u32 flags;
@@ -50,4 +78,6 @@ int ssp_init(struct ssp_dev *dev, u32 port, u32 init_flags);
int ssp_config(struct ssp_dev *dev, u32 mode, u32 flags, u32 psp_flags, u32 speed);
void ssp_exit(struct ssp_dev *dev);
-#endif
+struct ssp_device *ssp_request(int port, const char *label);
+void ssp_free(struct ssp_device *);
+#endif /* __ASM_ARCH_SSP_H */
diff --git a/include/asm-arm/arch-pxa/uncompress.h b/include/asm-arm/arch-pxa/uncompress.h
index 178aa2e073a..dadf4c20b62 100644
--- a/include/asm-arm/arch-pxa/uncompress.h
+++ b/include/asm-arm/arch-pxa/uncompress.h
@@ -9,19 +9,21 @@
* published by the Free Software Foundation.
*/
-#define FFUART ((volatile unsigned long *)0x40100000)
-#define BTUART ((volatile unsigned long *)0x40200000)
-#define STUART ((volatile unsigned long *)0x40700000)
-#define HWUART ((volatile unsigned long *)0x41600000)
+#include <linux/serial_reg.h>
+#include <asm/arch/pxa-regs.h>
+
+#define __REG(x) ((volatile unsigned long *)x)
#define UART FFUART
static inline void putc(char c)
{
- while (!(UART[5] & 0x20))
+ if (!(UART[UART_IER] & IER_UUE))
+ return;
+ while (!(UART[UART_LSR] & LSR_TDRQ))
barrier();
- UART[0] = c;
+ UART[UART_TX] = c;
}
/*
diff --git a/include/asm-arm/arch-pxa/zylonite.h b/include/asm-arm/arch-pxa/zylonite.h
index f58b59162b8..5f717d64ea7 100644
--- a/include/asm-arm/arch-pxa/zylonite.h
+++ b/include/asm-arm/arch-pxa/zylonite.h
@@ -3,9 +3,18 @@
#define ZYLONITE_ETH_PHYS 0x14000000
+#define EXT_GPIO(x) (128 + (x))
+
/* the following variables are processor specific and initialized
* by the corresponding zylonite_pxa3xx_init()
*/
+struct platform_mmc_slot {
+ int gpio_cd;
+ int gpio_wp;
+};
+
+extern struct platform_mmc_slot zylonite_mmc_slot[];
+
extern int gpio_backlight;
extern int gpio_eth_irq;