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path: root/Documentation/devicetree/bindings/clock/sunxi.txt
AgeCommit message (Expand)Author
2014-02-18clk: sunxi: Add new clock compatiblesMaxime Ripard
2014-02-18clk: sunxi: Add Allwinner A20/A31 GMAC clock unitChen-Yu Tsai
2014-02-18clk: sunxi: Add support for PLL6 on the A31Maxime Ripard
2014-02-18clk: sunxi: Add USB clock register defintionsRoman Byshko
2014-02-03clk: sunxi: update clock-output-names dt binding documentationChen-Yu Tsai
2013-12-28clk: sunxi: Allwinner A20 output clock supportChen-Yu Tsai
2013-12-28clk: sunxi: mod0 supportEmilio López
2013-12-28clk: sunxi: add PLL5 and PLL6 supportEmilio López
2013-12-28clk: sunxi: add gating support to PLL1Emilio López
2013-10-11Documentation: dt: Remove clock gates IDs list for Allwinner SoCsMaxime Ripard
2013-08-26clk: sunxi: Add Allwinner A20 gatesMaxime Ripard
2013-08-26clk: sunxi: Add A31 clocks supportMaxime Ripard
2013-08-26clk: sunxi: Add A10s gatesMaxime Ripard
2013-05-28clk: sun5i: Add compatibles for Allwinner A13Maxime Ripard
2013-04-04clk: sunxi: Add support for AXI, AHB, APB0 and APB1 gatesEmilio López
2013-03-27clk: sunxi: rename compatible stringsEmilio López
2013-03-27clk: arm: sunxi: Add a new clock driver for sunxi SOCsEmilio López
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