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path: root/arch/arm/mm/cache-l2x0.c
AgeCommit message (Expand)Author
2013-12-29ARM: 7922/1: l2x0: add Marvell Tauros3 supportSebastian Hesselbarth
2013-09-05Merge branches 'debug-choice', 'devel-stable' and 'misc' into for-linusRussell King
2013-08-20ARM: 7821/1: DT: binding fixup to align with vendor-prefixes.txtChristian Daudt
2013-08-20ARM: 7820/1: mm: cache-l2x0: Print the cache size in kBFabio Estevam
2013-08-12ARM: l2x0: use -st dsb option for ordering writel_relaxed with unlockWill Deacon
2013-05-15ARM: 7716/1: bcm281xx: Add L2 support for Rev A2 chipsChristian Daudt
2013-04-03ARM: 7682/1: cache-l2x0: fix masking of RTL revision numbering and set_debug ...Rob Herring
2013-01-07ARM: 7616/1: cache-l2x0: aurora: Use writel_relaxed instead of writelGregory CLEMENT
2013-01-07ARM: 7615/1: cache-l2x0: aurora: Invalidate during clean operation with WT en...Gregory CLEMENT
2013-01-02ARM: 7608/1: l2x0: Only set .set_debug on PL310 r3p0 and earlierRob Herring
2012-11-06ARM: 7547/4: cache-l2x0: add support for Aurora L2 cache ctrlGregory CLEMENT
2012-10-18ARM: 7545/1: cache-l2x0: make outer_cache_fns a field of l2x0_of_dataGregory CLEMENT
2012-10-07Merge branch 'for-linus' of git://git.linaro.org/people/rmk/linux-armLinus Torvalds
2012-09-15ARM: 7507/1: cache-l2x0.c: save the final aux ctrl value for resumingYilu Mao
2012-09-11ARM: cache-l2x0: add a const qualifierUwe Kleine-König
2012-04-23ARM: 7398/1: l2x0: only write to debug registers on PL310Will Deacon
2012-04-23ARM: 7397/1: l2x0: only apply workaround for erratum #753970 on PL310Will Deacon
2012-01-20ARM: cache-l2x0.c: consistently use u32Russell King
2011-11-21ARM: 7162/1: errata: tidy up Kconfig options for PL310 errata workaroundsWill Deacon
2011-10-26Merge branch 'core-locking-for-linus' of git://git.kernel.org/pub/scm/linux/k...Linus Torvalds
2011-10-17ARM: 7114/1: cache-l2x0: add resume entry for l2 in secure modeBarry Song
2011-10-17ARM: 7090/1: CACHE-L2X0: filter start address can be 0 and is often 0Barry Song
2011-10-17ARM: 7089/1: L2X0: add explicit cpu_relax() for busy wait loopBarry Song
2011-10-17ARM: 7009/1: l2x0: Add OF based initializationRob Herring
2011-09-13locking, ARM: Annotate low level hw locks as rawThomas Gleixner
2011-09-07ARM: 7080/1: l2x0: make sure I&D are not locked down on initLinus Walleij
2011-07-06ARM: 6987/1: l2x0: fix disabling function to avoid deadlockWill Deacon
2011-03-16Merge branch 'misc' into develRussell King
2011-03-09ARM: 6795/1: l2x0: Errata fix for flush by Way operation can cause data corruptiSantosh Shilimkar
2011-02-19ARM: 6741/1: errata: pl310 cache sync operation may be faultySrinidhi Kasagar
2010-10-26ARM: l2x0: Optimise the range based operationsSantosh Shilimkar
2010-10-26ARM: l2x0: Determine the cache sizeSantosh Shilimkar
2010-10-26arm: Implement l2x0 cache disable functionsThomas Gleixner
2010-10-26ARM: Improve the L2 cache performance when PL310 is usedCatalin Marinas
2010-07-29ARM: 6272/1: Convert L2x0 to use the IO relaxed operationsCatalin Marinas
2010-07-09ARM: 6210/1: Do not rely on reset defaults of L2X0_AUX_CTRLSascha Hauer
2010-05-17Merge branch 'devel-stable' into develRussell King
2010-05-15ARM: 6094/1: Extend cache-l2x0 to support the 16-way PL310Jason McMullan
2010-03-25ARM: 5995/1: ARM: Add L2x0 outer_sync() support (3/4)Catalin Marinas
2010-02-15ARM: 5919/1: ARM: L2 : Errata 588369: Clean & Invalidate do not invalidate cl...Santosh Shilimkar
2010-02-15ARM: 5916/1: ARM: L2 : Add maintainace by line helper functionsSantosh Shilimkar
2009-12-14Merge branch 'pending-l2x0' into cacheRussell King
2009-12-14ARM: cache-l2x0: make better use of background cache handlingRussell King
2009-12-14ARM: cache-l2x0: avoid taking spinlock for every iterationRussell King
2009-12-03ARM: 5845/1: l2x0: check whether l2x0 already enabledSrinidhi Kasagar
2008-09-06[ARM] Convert asm/io.h to linux/io.hRussell King
2007-09-17[ARM] 4568/1: fix l2x0 cache invalidate handling of unaligned addressesRui Sousa
2007-07-20[ARM] 4500/1: Add locking around the background L2x0 cache operationsCatalin Marinas
2007-02-11[ARM] 4135/1: Add support for the L210/L220 cache controllersCatalin Marinas
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