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path: root/drivers/gpu/drm/i915/i915_reg.h
AgeCommit message (Expand)Author
2013-05-07Revert "drm/i915: Calculate correct stolen size for GEN7+"Ben Widawsky
2013-04-23drm/i915: Make data/link N value power of twoVille Syrjälä
2013-04-18drm/i915: preserve the PBC bits of TRANS_CHICKEN2Paulo Zanoni
2013-04-18drm/i915: set CPT FDI RX polarity bits based on VBTPaulo Zanoni
2013-04-18drm/i915: Scale ring, rather than ia, frequency on HaswellChris Wilson
2013-04-18drm/i915: Increase max fence pitch limit to 256KB on IVB+Ville Syrjälä
2013-04-18drm/i915: Configure GAM_ECOCHK appropriatly for Gen7Ville Syrjälä
2013-04-18drm/i915: Add ECOBITS_SNB_BITVille Syrjälä
2013-04-08drm/i915: Don't wait for PCH on resetBen Widawsky
2013-04-02drm/i915: add Punit read/write routines for VLV v2Jesse Barnes
2013-04-02drm/i915: panel power sequencing for VLV eDP v2Jesse Barnes
2013-04-02drm/i915: sprite support for ValleyView v4Jesse Barnes
2013-04-02drm/i915: fix ILK GPU reset for renderJesse Barnes
2013-03-27drm/i915: wire up SDVO hpd support on cpt/pptDaniel Vetter
2013-03-26DRM/i915: Convert HPD interrupts to make use of HPD pin assignment in encoder...Egbert Eich
2013-03-26drm/i915: HSW PM Frequency bits fixRodrigo Vivi
2013-03-23drm/i915: Implement WaSwitchSolVfFArbitrationPriorityBen Widawsky
2013-03-23drm/i915: DSPFW and BLC regs are in the display offset rangeJesse Barnes
2013-03-23drm/i915: add media well to VLV force wake routines v2Jesse Barnes
2013-03-19Merge tag 'v3.9-rc3' into drm-intel-next-queuedDaniel Vetter
2013-03-19drm/i915: allow force wake at init time on VLV v2Jesse Barnes
2013-03-06drm/i915: Fix incorrect definition of ADPA HSYNC and VSYNC bitsPatrik Jakobsson
2013-03-04drm/i915: rename some HDMI bit definitionsPaulo Zanoni
2013-03-04drm/i915: remove duplicated SDVO/HDMI bit definitionsPaulo Zanoni
2013-03-04drm/i915: unify the definitions of the HDMI/SDVO registerPaulo Zanoni
2013-03-04drm/i915: clarify confusion between SDVO and HDMI registersPaulo Zanoni
2013-03-03drm/i915: Use cpu_transcoder for HSW_TVIDEO_DIP_* instead of pipeRodrigo Vivi
2013-02-20drm/i915: Refactor gen2 to gen4 vblank interrupt handlingVille Syrjälä
2013-02-20drm/i915: use FPGA_DBG for the "unclaimed register" checksPaulo Zanoni
2013-02-20drm/i915: Implement pipe CSC based limited range RGB outputVille Syrjälä
2013-02-20drm/i915: Fix PIPE_CONTROL DW/QW write through global GTT on IVB+Ville Syrjälä
2013-02-20drm/i915: Preserve the DDI link reversal configurationDamien Lespiau
2013-02-20drm/i915: Preserve the FDI line reversal override bit on CPTDamien Lespiau
2013-02-20drm/i915: detect wrong MCH watermark valuesDaniel Vetter
2013-02-15drm/i915: unify HDMI/DP hpd definitionsDaniel Vetter
2013-02-14drm/i915: Fix RC6VIDS encode/decodeBen Widawsky
2013-02-08Merge branch 'fbcon-locking-fixes' of ssh://people.freedesktop.org/~airlied/l...Dave Airlie
2013-01-31drm/i915: Introduce i915_vgacntrl_reg()Ville Syrjälä
2013-01-31drm/i915: Fix CAGF for HSWBen Widawsky
2013-01-28drm/i915: Implement WaVSRefCountFullforceMissDisableBen Widawsky
2013-01-26drm/i915: fix intel_init_power_wellsPaulo Zanoni
2013-01-26drm/i915: SWF screatch registers need an offset on VLVVille Syrjälä
2013-01-26drm/i915: Include display_mmio_offset in sequencer index/data registersVille Syrjälä
2013-01-26drm/i915: PLL registers need an offset on VLVVille Syrjälä
2013-01-24drm/i915: DPIO registers are VLV only and need an offsetVille Syrjälä
2013-01-24drm/i915: Spell out VLV_DISPLAY_BASE for interrupt registersVille Syrjälä
2013-01-24drm/i915: Make VLV_GUNIT_CLOCK_GATE register value more readableVille Syrjälä
2013-01-24drm/i915: FB_BLC_SELF_VLV is VLV only and needs an offsetVille Syrjälä
2013-01-24drm/i915: Pipe palette registers need an offset on VLVVille Syrjälä
2013-01-24drm/i915: Pipe timing registers need an offset on VLVVille Syrjälä
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