summaryrefslogtreecommitdiffstats
path: root/arch/blackfin/mach-common/cacheinit.S
blob: 7924a90d9658ef900d04aa390ec9f13a514b68fb (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
/*
 * File:         arch/blackfin/mach-common/cacheinit.S
 * Based on:
 * Author:       LG Soft India
 *
 * Created:      ?
 * Description:  cache initialization
 *
 * Modified:
 *               Copyright 2004-2006 Analog Devices Inc.
 *
 * Bugs:         Enter bugs at http://blackfin.uclinux.org/
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, see the file COPYING, or write
 * to the Free Software Foundation, Inc.,
 * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
 */

/* This function sets up the data and instruction cache. The
 * tables like icplb table, dcplb table and Page Descriptor table
 * are defined in cplbtab.h. You can configure those tables for
 * your suitable requirements
 */

#include <linux/linkage.h>
#include <asm/blackfin.h>

.text

#if defined(CONFIG_BLKFIN_CACHE)
ENTRY(_bfin_icache_init)

	/* Initialize Instruction CPLBS */

	I0.L = (ICPLB_ADDR0 & 0xFFFF);
	I0.H = (ICPLB_ADDR0 >> 16);

	I1.L = (ICPLB_DATA0 & 0xFFFF);
	I1.H = (ICPLB_DATA0 >> 16);

	I2.L = _icplb_table;
	I2.H = _icplb_table;

	r1 = -1;	/* end point comparison */
	r3 = 15;	/* max counter */

/* read entries from table */

.Lread_iaddr:
	R0 = [I2++];
	CC = R0 == R1;
	IF CC JUMP .Lidone;
	[I0++] = R0;

.Lread_idata:
	R2 = [I2++];
	[I1++] = R2;
	R3 = R3 + R1;
	CC = R3 == R1;
	IF !CC JUMP .Lread_iaddr;

.Lidone:
	/* Enable Instruction Cache */
	P0.l = (IMEM_CONTROL & 0xFFFF);
	P0.h = (IMEM_CONTROL >> 16);
	R1 = [P0];
	R0 = (IMC | ENICPLB);
	R0 = R0 | R1;

	/* Anomaly 05000125 */
	CLI R2;
	SSYNC;		/* SSYNC required before writing to IMEM_CONTROL. */
	.align 8;
	[P0] = R0;
	SSYNC;
	STI R2;
	RTS;

ENDPROC(_bfin_icache_init)
#endif

#if defined(CONFIG_BLKFIN_DCACHE)
ENTRY(_bfin_dcache_init)

	/* Initialize Data CPLBS */

	I0.L = (DCPLB_ADDR0 & 0xFFFF);
	I0.H = (DCPLB_ADDR0 >> 16);

	I1.L = (DCPLB_DATA0 & 0xFFFF);
	I1.H = (DCPLB_DATA0 >> 16);

	I2.L = _dcplb_table;
	I2.H = _dcplb_table;

	R1 = -1;	/* end point comparison */
	R3 = 15;	/* max counter */

	/* read entries from table */
.Lread_daddr:
	R0 = [I2++];
	cc = R0 == R1;
	IF CC JUMP .Lddone;
	[I0++] = R0;

.Lread_ddata:
	R2 = [I2++];
	[I1++] = R2;
	R3 = R3 + R1;
	CC = R3 == R1;
	IF !CC JUMP .Lread_daddr;
.Lddone:
	P0.L = (DMEM_CONTROL & 0xFFFF);
	P0.H = (DMEM_CONTROL >> 16);
	R1 = [P0];

	R0 = DMEM_CNTR;

	R0 = R0 | R1;
	/* Anomaly 05000125 */
	CLI R2;
	SSYNC;		/* SSYNC required before writing to DMEM_CONTROL. */
	.align 8;
	[P0] = R0;
	SSYNC;
	STI R2;
	RTS;

ENDPROC(_bfin_dcache_init)
#endif