summaryrefslogtreecommitdiffstats
path: root/include/asm-arm/arch-mxc/board-mx27ads.h
blob: 61e66dac90efbce6a8c700820b3edebfa082a9f0 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
/*
 * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
 */

/*
 * The code contained herein is licensed under the GNU General Public
 * License. You may obtain a copy of the GNU General Public License
 * Version 2 or later at the following locations:
 *
 * http://www.opensource.org/licenses/gpl-license.html
 * http://www.gnu.org/copyleft/gpl.html
 */

#ifndef __ASM_ARCH_MXC_BOARD_MX27ADS_H__
#define __ASM_ARCH_MXC_BOARD_MX27ADS_H__

/* external interrupt multiplexer */
#define MXC_EXP_IO_BASE		(MXC_GPIO_BASE + MXC_MAX_GPIO_LINES)

#define MXC_VIRTUAL_INTS_BASE	(MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES)
#define MXC_SDIO1_CARD_IRQ	MXC_VIRTUAL_INTS_BASE
#define MXC_SDIO2_CARD_IRQ	(MXC_VIRTUAL_INTS_BASE + 1)
#define MXC_SDIO3_CARD_IRQ	(MXC_VIRTUAL_INTS_BASE + 2)

#define MXC_MAX_BOARD_INTS      (MXC_MAX_EXP_IO_LINES + \
				MXC_MAX_VIRTUAL_INTS)

/*
 * MXC UART EVB board level configurations
 */

#define MXC_LL_EXTUART_PADDR	(CS4_BASE_ADDR + 0x20000)
#define MXC_LL_EXTUART_VADDR	(CS4_BASE_ADDR_VIRT + 0x20000)
#define MXC_LL_EXTUART_16BIT_BUS

#define MXC_LL_UART_PADDR       UART1_BASE_ADDR
#define MXC_LL_UART_VADDR       AIPI_IO_ADDRESS(UART1_BASE_ADDR)

/*
 * @name Memory Size parameters
 */

/*
 * Size of SDRAM memory
 */
#define SDRAM_MEM_SIZE          SZ_128M

/*
 * PBC Controller parameters
 */

/*
 * Base address of PBC controller, CS4
 */
#define PBC_BASE_ADDRESS        0xEB000000
#define PBC_REG_ADDR(offset)    (PBC_BASE_ADDRESS + (offset))

/*
 * PBC Interupt name definitions
 */
#define PBC_GPIO1_0  0
#define PBC_GPIO1_1  1
#define PBC_GPIO1_2  2
#define PBC_GPIO1_3  3
#define PBC_GPIO1_4  4
#define PBC_GPIO1_5  5

#define PBC_INTR_MAX_NUM 6
#define PBC_INTR_SHARED_MAX_NUM 8

/* When the PBC address connection is fixed in h/w, defined as 1 */
#define PBC_ADDR_SH             0

/* Offsets for the PBC Controller register */
/*
 * PBC Board version register offset
 */
#define PBC_VERSION_REG         PBC_REG_ADDR(0x00000 >> PBC_ADDR_SH)
/*
 * PBC Board control register 1 set address.
 */
#define PBC_BCTRL1_SET_REG      PBC_REG_ADDR(0x00008 >> PBC_ADDR_SH)
/*
 * PBC Board control register 1 clear address.
 */
#define PBC_BCTRL1_CLEAR_REG    PBC_REG_ADDR(0x0000C >> PBC_ADDR_SH)
/*
 * PBC Board control register 2 set address.
 */
#define PBC_BCTRL2_SET_REG      PBC_REG_ADDR(0x00010 >> PBC_ADDR_SH)
/*
 * PBC Board control register 2 clear address.
 */
#define PBC_BCTRL2_CLEAR_REG    PBC_REG_ADDR(0x00014 >> PBC_ADDR_SH)
/*
 * PBC Board control register 3 set address.
 */
#define PBC_BCTRL3_SET_REG      PBC_REG_ADDR(0x00018 >> PBC_ADDR_SH)
/*
 * PBC Board control register 3 clear address.
 */
#define PBC_BCTRL3_CLEAR_REG    PBC_REG_ADDR(0x0001C >> PBC_ADDR_SH)
/*
 * PBC Board control register 3 set address.
 */
#define PBC_BCTRL4_SET_REG      PBC_REG_ADDR(0x00020 >> PBC_ADDR_SH)
/*
 * PBC Board control register 4 clear address.
 */
#define PBC_BCTRL4_CLEAR_REG    PBC_REG_ADDR(0x00024 >> PBC_ADDR_SH)
/*PBC_ADDR_SH
 * PBC Board status register 1.
 */
#define PBC_BSTAT1_REG          PBC_REG_ADDR(0x00028 >> PBC_ADDR_SH)
/*
 * PBC Board interrupt status register.
 */
#define PBC_INTSTATUS_REG       PBC_REG_ADDR(0x0002C >> PBC_ADDR_SH)
/*
 * PBC Board interrupt current status register.
 */
#define PBC_INTCURR_STATUS_REG  PBC_REG_ADDR(0x00034 >> PBC_ADDR_SH)
/*
 * PBC Interrupt mask register set address.
 */
#define PBC_INTMASK_SET_REG     PBC_REG_ADDR(0x00038 >> PBC_ADDR_SH)
/*
 * PBC Interrupt mask register clear address.
 */
#define PBC_INTMASK_CLEAR_REG   PBC_REG_ADDR(0x0003C >> PBC_ADDR_SH)
/*
 * External UART A.
 */
#define PBC_SC16C652_UARTA_REG  PBC_REG_ADDR(0x20000 >> PBC_ADDR_SH)
/*
 * UART 4 Expanding Signal Status.
 */
#define PBC_UART_STATUS_REG     PBC_REG_ADDR(0x22000 >> PBC_ADDR_SH)
/*
 * UART 4 Expanding Signal Control Set.
 */
#define PBC_UCTRL_SET_REG       PBC_REG_ADDR(0x24000 >> PBC_ADDR_SH)
/*
 * UART 4 Expanding Signal Control Clear.
 */
#define PBC_UCTRL_CLR_REG       PBC_REG_ADDR(0x26000 >> PBC_ADDR_SH)
/*
 * Ethernet Controller IO base address.
 */
#define PBC_CS8900A_IOBASE_REG  PBC_REG_ADDR(0x40000 >> PBC_ADDR_SH)
/*
 * Ethernet Controller Memory base address.
 */
#define PBC_CS8900A_MEMBASE_REG PBC_REG_ADDR(0x42000 >> PBC_ADDR_SH)
/*
 * Ethernet Controller DMA base address.
 */
#define PBC_CS8900A_DMABASE_REG PBC_REG_ADDR(0x44000 >> PBC_ADDR_SH)

/* PBC Board Version Register bit definition */
#define PBC_VERSION_ADS         0x8000	/* Bit15=1 means version for ads */
#define PBC_VERSION_EVB_REVB    0x4000	/* BIT14=1 means version for evb revb */

/* PBC Board Control Register 1 bit definitions */
#define PBC_BCTRL1_ERST         0x0001	/* Ethernet Reset */
#define PBC_BCTRL1_URST         0x0002	/* Reset External UART controller */
#define PBC_BCTRL1_FRST         0x0004	/* FEC Reset */
#define PBC_BCTRL1_ESLEEP       0x0010	/* Enable ethernet Sleep */
#define PBC_BCTRL1_LCDON        0x0800	/* Enable the LCD */

/* PBC Board Control Register 2 bit definitions */
#define PBC_BCTRL2_VCC_EN       0x0004	/*   Enable VCC */
#define PBC_BCTRL2_VPP_EN       0x0008	/*   Enable Vpp */
#define PBC_BCTRL2_ATAFEC_EN    0X0010
#define PBC_BCTRL2_ATAFEC_SEL   0X0020
#define PBC_BCTRL2_ATA_EN       0X0040
#define PBC_BCTRL2_IRDA_SD      0X0080
#define PBC_BCTRL2_IRDA_EN      0X0100
#define PBC_BCTRL2_CCTL10       0X0200
#define PBC_BCTRL2_CCTL11       0X0400

/* PBC Board Control Register 3 bit definitions */
#define PBC_BCTRL3_HSH_EN       0X0020
#define PBC_BCTRL3_FSH_MOD      0X0040
#define PBC_BCTRL3_OTG_HS_EN    0X0080
#define PBC_BCTRL3_OTG_VBUS_EN  0X0100
#define PBC_BCTRL3_FSH_VBUS_EN  0X0200
#define PBC_BCTRL3_USB_OTG_ON   0X0800
#define PBC_BCTRL3_USB_FSH_ON   0X1000

/* PBC Board Control Register 4 bit definitions */
#define PBC_BCTRL4_REGEN_SEL    0X0001
#define PBC_BCTRL4_USER_OFF     0X0002
#define PBC_BCTRL4_VIB_EN       0X0004
#define PBC_BCTRL4_PWRGT1_EN    0X0008
#define PBC_BCTRL4_PWRGT2_EN    0X0010
#define PBC_BCTRL4_STDBY_PRI    0X0020

#ifndef __ASSEMBLY__
/*
 * Enumerations for SD cards and memory stick card. This corresponds to
 * the card EN bits in the IMR: SD1_EN | MS_EN | SD3_EN | SD2_EN.
 */
enum mxc_card_no {
	MXC_CARD_SD2 = 0,
	MXC_CARD_SD3,
	MXC_CARD_MS,
	MXC_CARD_SD1,
	MXC_CARD_MIN = MXC_CARD_SD2,
	MXC_CARD_MAX = MXC_CARD_SD1,
};
#endif

#define MXC_CPLD_VER_1_50       0x01

/*
 * PBC BSTAT Register bit definitions
 */
#define PBC_BSTAT_PRI_INT       0X0001
#define PBC_BSTAT_USB_BYP       0X0002
#define PBC_BSTAT_ATA_IOCS16    0X0004
#define PBC_BSTAT_ATA_CBLID     0X0008
#define PBC_BSTAT_ATA_DASP      0X0010
#define PBC_BSTAT_PWR_RDY       0X0020
#define PBC_BSTAT_SD3_WP        0X0100
#define PBC_BSTAT_SD2_WP        0X0200
#define PBC_BSTAT_SD1_WP        0X0400
#define PBC_BSTAT_SD3_DET       0X0800
#define PBC_BSTAT_SD2_DET       0X1000
#define PBC_BSTAT_SD1_DET       0X2000
#define PBC_BSTAT_MS_DET        0X4000
#define PBC_BSTAT_SD3_DET_BIT   11
#define PBC_BSTAT_SD2_DET_BIT   12
#define PBC_BSTAT_SD1_DET_BIT   13
#define PBC_BSTAT_MS_DET_BIT    14
#define MXC_BSTAT_BIT(n)        ((n == MXC_CARD_SD2) ? PBC_BSTAT_SD2_DET : \
				 ((n == MXC_CARD_SD3) ? PBC_BSTAT_SD3_DET : \
				 ((n == MXC_CARD_SD1) ? PBC_BSTAT_SD1_DET : \
				 ((n == MXC_CARD_MS) ? PBC_BSTAT_MS_DET : \
					0x0))))

/*
 * PBC UART Control Register bit definitions
 */
#define PBC_UCTRL_DCE_DCD       0X0001
#define PBC_UCTRL_DCE_DSR       0X0002
#define PBC_UCTRL_DCE_RI        0X0004
#define PBC_UCTRL_DTE_DTR       0X0100

/*
 * PBC UART Status Register bit definitions
 */
#define PBC_USTAT_DTE_DCD       0X0001
#define PBC_USTAT_DTE_DSR       0X0002
#define PBC_USTAT_DTE_RI        0X0004
#define PBC_USTAT_DCE_DTR       0X0100

/*
 * PBC Interupt mask register bit definitions
 */
#define PBC_INTR_SD3_R_EN_BIT   4
#define PBC_INTR_SD2_R_EN_BIT   0
#define PBC_INTR_SD1_R_EN_BIT   6
#define PBC_INTR_MS_R_EN_BIT    5
#define PBC_INTR_SD3_EN_BIT     13
#define PBC_INTR_SD2_EN_BIT     12
#define PBC_INTR_MS_EN_BIT      14
#define PBC_INTR_SD1_EN_BIT     15

#define PBC_INTR_SD2_R_EN       0x0001
#define PBC_INTR_LOW_BAT        0X0002
#define PBC_INTR_OTG_FSOVER     0X0004
#define PBC_INTR_FSH_OVER       0X0008
#define PBC_INTR_SD3_R_EN       0x0010
#define PBC_INTR_MS_R_EN        0x0020
#define PBC_INTR_SD1_R_EN       0x0040
#define PBC_INTR_FEC_INT        0X0080
#define PBC_INTR_ENET_INT       0X0100
#define PBC_INTR_OTGFS_INT      0X0200
#define PBC_INTR_XUART_INT      0X0400
#define PBC_INTR_CCTL12         0X0800
#define PBC_INTR_SD2_EN         0x1000
#define PBC_INTR_SD3_EN         0x2000
#define PBC_INTR_MS_EN          0x4000
#define PBC_INTR_SD1_EN         0x8000



/* For interrupts like xuart, enet etc */
#define EXPIO_PARENT_INT        IOMUX_TO_IRQ(MX27_PIN_TIN)
#define MXC_MAX_EXP_IO_LINES    16

/*
 * This corresponds to PBC_INTMASK_SET_REG at offset 0x38.
 *
 */
#define EXPIO_INT_LOW_BAT       (MXC_EXP_IO_BASE + 1)
#define EXPIO_INT_OTG_FS_OVR    (MXC_EXP_IO_BASE + 2)
#define EXPIO_INT_FSH_OVR       (MXC_EXP_IO_BASE + 3)
#define EXPIO_INT_RES4          (MXC_EXP_IO_BASE + 4)
#define EXPIO_INT_RES5          (MXC_EXP_IO_BASE + 5)
#define EXPIO_INT_RES6          (MXC_EXP_IO_BASE + 6)
#define EXPIO_INT_FEC           (MXC_EXP_IO_BASE + 7)
#define EXPIO_INT_ENET_INT      (MXC_EXP_IO_BASE + 8)
#define EXPIO_INT_OTG_FS_INT    (MXC_EXP_IO_BASE + 9)
#define EXPIO_INT_XUART_INTA    (MXC_EXP_IO_BASE + 10)
#define EXPIO_INT_CCTL12_INT    (MXC_EXP_IO_BASE + 11)
#define EXPIO_INT_SD2_EN        (MXC_EXP_IO_BASE + 12)
#define EXPIO_INT_SD3_EN        (MXC_EXP_IO_BASE + 13)
#define EXPIO_INT_MS_EN         (MXC_EXP_IO_BASE + 14)
#define EXPIO_INT_SD1_EN        (MXC_EXP_IO_BASE + 15)

/*
 * This is System IRQ used by CS8900A for interrupt generation
 * taken from platform.h
 */
#define CS8900AIRQ              EXPIO_INT_ENET_INT
/* This is I/O Base address used to access registers of CS8900A on MXC ADS */
#define CS8900A_BASE_ADDRESS    (PBC_CS8900A_IOBASE_REG + 0x300)

#define MXC_PMIC_INT_LINE       IOMUX_TO_IRQ(MX27_PIN_TOUT)

/*
* This is used to detect if the CPLD version is for mx27 evb board rev-a
*/
#define PBC_CPLD_VERSION_IS_REVA() \
	((__raw_readw(PBC_VERSION_REG) & \
	(PBC_VERSION_ADS | PBC_VERSION_EVB_REVB))\
	== 0)

/* This is used to active or inactive ata signal in CPLD .
 *  It is dependent with hardware
 */
#define PBC_ATA_SIGNAL_ACTIVE() \
	__raw_writew(           \
		PBC_BCTRL2_ATAFEC_EN|PBC_BCTRL2_ATAFEC_SEL|PBC_BCTRL2_ATA_EN, \
		PBC_BCTRL2_CLEAR_REG)

#define PBC_ATA_SIGNAL_INACTIVE() \
	__raw_writew(  \
		PBC_BCTRL2_ATAFEC_EN|PBC_BCTRL2_ATAFEC_SEL|PBC_BCTRL2_ATA_EN, \
		PBC_BCTRL2_SET_REG)

#define MXC_BD_LED1             (1 << 5)
#define MXC_BD_LED2             (1 << 6)
#define MXC_BD_LED_ON(led) \
	__raw_writew(led, PBC_BCTRL1_SET_REG)
#define MXC_BD_LED_OFF(led) \
	__raw_writew(led, PBC_BCTRL1_CLEAR_REG)

/* to determine the correct external crystal reference */
#define CKIH_27MHZ_BIT_SET      (1 << 3)

#endif				/* __ASM_ARCH_MXC_BOARD_MX27ADS_H__ */