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authorBoris BREZILLON <boris.brezillon@free-electrons.com>2014-09-02 09:50:17 +0200
committerMike Turquette <mturquette@linaro.org>2014-09-02 15:37:22 -0700
commit13a6073d4c5db3103011eebe8c68b049323ced20 (patch)
treea9e2dee2d3c352d77e7275b28d853eca06fb13ab /tools/perf/scripts/python/syscall-counts.py
parent87e2ed338f1b56798807ccf12eb6112d25062202 (diff)
clk: at91: rework rm9200 USB clock to propagate set_rate to the parent clk
The RM9200 USB clock is actually connected to a single parent (the PLLB) on which we can apply a specific divider. The USB clock divider does not allow for fine grained control on the USB clock frequency, hence propagating the set_rate request to the parent is the only choice we have to properly configure the USB clock rate. Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com> Reported-by: Gaël PORTAY <gael.portay@gmail.com> Tested-by: Gaël PORTAY <gael.portay@gmail.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
Diffstat (limited to 'tools/perf/scripts/python/syscall-counts.py')
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